JPS622739B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a code error detection circuit used for monitoring line quality of a multilevel digital signal transmission line for telecommunications.

[Conventional technology and its problems]

Digital transmission technology has developed dramatically in recent years, and multilevel digital transmission is about to be put into practical use.
When configuring a multilevel digital transmission line, the line quality is monitored and if quality deterioration occurs due to equipment deterioration, transmission line distortion, or noise, line monitoring such as line switching is performed. A control system is essential.

Since the line quality of a digital signal line is usually evaluated by the bit error rate, some sort of bit error detection circuit is required to configure a line monitoring control system.

Conventional examples of code error detection circuits compatible with the above-mentioned uses include the following. That is,
A main discriminating and reproducing circuit converts an input signal into a digital signal, and a sub discriminating and reproducing circuit converts the input signal into a digital signal at a discriminating and reproducing level that is shifted by a certain value from the optimum value. It is applied to a circuit and obtains a code error signal at its output.

According to this method, the means for forcibly deteriorating the code error rate is a method of shifting the discrimination reproduction level of the sub discrimination reproduction circuit from the optimum value. In other words, since a fixed DC level is given as an interference signal,
It becomes very sensitive to DC level fluctuations that occur within the circuit. For this reason, even when used for normal binary digital transmission, there was a problem in stable operation of the circuit. Therefore, if this method is applied as is to multilevel digital transmission, the stability of the circuit will deteriorate further and stable operation cannot be expected.

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks, and aims to provide a new code error detection circuit that has high circuit stability, a simple circuit configuration, and can be applied to multilevel digital transmission.

[Means for solving problems]

The present invention includes at least two first and second multipliers for converting a multi-value input signal into a binary signal;
means for identifying and reproducing the output of the first multiplier; and means for identifying and reproducing the output signal by adding or subtracting the output of the second multiplier to the output of the first multiplier at a certain amplitude ratio. and means for calculating the exclusive OR of the output signals of the two identification and reproducing means.

〔Example〕

This will be explained in detail below using the drawings.

Figure 1 shows a conventional example of a code error detection circuit.
and 2 is a discriminator, and 3 is an exclusive OR circuit. The binary input signal is discriminated by a discriminator 1 at an optimum discrimination level to obtain a main signal. On the other hand, the input signal is discriminated in the discriminator 2 at a level that is shifted by a certain value from the optimum discrimination level in order to make the code errors of the output signal of the discriminator 2 more than the code errors of the discriminator 1. Next, when the output signals of the discriminators 1 and 2 are applied to the exclusive OR circuit 3, it is possible to detect a code error in the difference between the two in its output.

According to this method, code errors can be detected with a simple circuit configuration, but in order to forcibly increase the number of code errors in the discriminator 2, a method for identifying at a level that is shifted by a certain value from the optimal discrimination level is used. As a result, the circuit operation becomes unstable due to DC level fluctuations within the circuit.

To add a little more explanation, the relationship between the code error in the classifier and the classification level exhibits the characteristics shown in FIG. In other words, if we compare the rate of change in code errors when the discrimination level is near the optimum value (point A) and the rate of change in code errors at the point where the discrimination level deviates from the optimum value (point B), the latter is significantly higher. At point B, the code error changes greatly even with a slight change in the discrimination level. Therefore, in the state of the discriminator 2, compared to the state of the discriminator 1 in normal use, the allowable value for DC fluctuations in the circuit is significantly restricted, and there is a drawback that the circuit becomes unstable due to fluctuations in the DC level.

The above explanation has been made regarding the case where a binary signal is used as the input signal, but the above-mentioned drawbacks will further increase when a multi-value signal is used.

FIG. 3 is a block diagram of a code error detection circuit according to an embodiment of the present invention. This example is a circuit for detecting code errors in four-value digital transmission.

The two input signals are independent four-value signals, and are input to both wave rectifiers 4 and 5, respectively. Each of its outputs is connected to the inputs of discriminators 6 and 8 and branched, with only one output passing through attenuator 10 and being led to the input of adder 9.
The output of the adder 9 is given to the discriminator 7, and its output and the output of the discriminator 6 are given to the input of the exclusive OR circuit 11.

The operation of the circuit configured in this way will be explained with reference to the waveform diagram shown in FIG. Figure 4 A, B, C
shows the waveform of the point with the corresponding symbol shown in FIG. 3 as an eye pattern. In the figure, T represents one time slot.

The input signal -1 or -2 is ± as shown in Figure 4A.
The signal has four values of 3 and ±1, and there is no correlation between the code strings between the two. Input signal-2 is a signal from another route.

Both input signals are input to two multipliers, that is, two double-wave rectifier circuits 4 and 5, respectively.
Here, it is turned back at level 0, and a signal B is obtained as an output. Further, the output signal is discriminated by a discriminator 6 or 8 at a discrimination level of +2 to obtain a main signal -1 or 2 of the binary digital signal.

On the other hand, the output signal of the double wave rectifier circuit 5 is transmitted to the attenuator 10.
The output signals of the double-wave rectifier circuit 4 are directly input to the adder 9 and added together to obtain the four-level signal shown in FIG. 4C. Here, if the attenuation ratio of the attenuator 10 is m (m<1), the output of the double wave rectifier circuit 4 has two levels of +3 and +1,
Since the output of the double-wave rectifier circuit 5 has two levels of +3m and +m, the output signal of the adder 9 is
Take the four values of +3m, 3+m, 1+3m, 1+m,
Compared to the output level of the double-wave rectifier circuit 4, the signal has deteriorated by half the difference between the maximum level and the minimum level, that is, (3+m)-(1+3m)/2=1-m. The code errors of the output signal identified at the average discrimination level (2+2m) are greater than the code errors of the discriminator 6 by the above-mentioned (1-m).
Therefore, when both are processed by the exclusive OR circuit 11, the sign error of the difference between the two is obtained as an output.

The present invention can also be applied to multi-value digital transmission of four or more values, in which case the multiplication order of the multiplier (double-wave rectifier circuit) for obtaining a binary signal may be increased. Further, in the above example, it has been described that the output of each double-wave rectifier circuit is provided to the adder, but the present invention can also be implemented by replacing this with a subtracter.

[Effects of the Invention] As described above, the present invention uses a method of forcibly increasing code errors by using a signal from another route as an interference wave and equivalently degrading the signal level of that signal. , the stability of the circuit due to DC level fluctuations corresponds equivalently to point C in FIG. That is, according to the present invention, it is possible to realize a code error detection circuit that has a simple circuit configuration and is stable against DC level fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional example of a code error detection circuit. FIG. 2 is a diagram showing an example of characteristics of code error versus identification level.
FIG. 3 is a block diagram of a code error detection circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing signal waveforms at various parts in FIG. 3. 1, 2...discriminator, 3...exclusive OR circuit, 4,
5... Double-wave rectifier circuit, 6, 7, 8... Discriminator, 9... Adder, 10... Attenuator, 11... Exclusive OR circuit.

Claims (1)

[Claims] 1. At least two first and second multipliers 4, 5 for converting a multi-value input signal into a binary signal; and a means 6 for identifying and reproducing the output of the first multiplier. , means 7, 9, 10 for identifying and reproducing the output signal by adding or subtracting the output of the second multiplying means to the output of the first multiplying means at a certain amplitude ratio; and the two identifying and reproducing means. A code error detection circuit for a multivalued digital signal, comprising means 11 for calculating an exclusive OR of output signals.