JPS62273607A - Timing signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain a desired timing signal by generating a binary timing signal in response to a variable voltage outputted in response to a control signal and connecting a diode in parallel with a resistor deciding a time constant for variable voltage generation. CONSTITUTION:A control signal (a) goes to 'L' at reproduction, a signal (d) goes to 'L' via inverters 3, 4 and outputs of inverters 5, 7 go respectively to 'L', 'H'. The signal (a) is at 'H' at the recording and signals (b), (c) are inverted to 'L', a capacitor C3 is discharged instantly by a diode D1 and in selecting the components as R2C4<R4R5, a delay to 'L' level of the signal (e) is caused by a resistor R2, a signal (g) charges a capacitor C5 via a resistor R4 and inverted into 'H' with further delay. As a result, the capacitor C1 turns on a switch SW2 and turns off a switch SW1 after the sufficient charge thereby preventing the transient current to a head HD. At the changeover from the recording to the reproduction, is selecting the components as R1C3>(R2+R3)C4, the control drive is applied in the order of the switches SW1, SW2 and a recording amplifier A and the charge/discharge current of the C2 does not flow to the head. The time constant of each circuit is set optionally independently and the leading of three outputs of the inverters 4, 5, 7 is set optionally to the control signal (a).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing signal generator that sends out a timing signal in response to a control signal of a predetermined level.

[Prior Art] FIG. 4 shows an example of a conventionally known simple timing signal generation circuit. In this figure, A3 and A4 are operational amplifiers, (i) is a control signal, and (k) is a timing signal that is sent out with a delay of Td from the time when the control signal is applied.

[Problems to be Solved by the Invention] However, in the timing signal generation circuit shown in FIG. 4, the timing signal is only generated after a certain period of time in response to the applied control signal. The disadvantage is that it is not possible to obtain a timing signal according to

It is also possible to obtain a desired timing signal using a microcomputer or the like, but this increases the number of complex signal exchanges and has the disadvantage that the entire circuit becomes dog-shaped.

SUMMARY OF THE INVENTION In view of the above-mentioned points, an object of the present invention is to provide a timing signal generator configured to be able to obtain a desired timing signal with a simple configuration.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a timing signal generator that transmits a timing signal in response to a control signal of a predetermined level. a variable voltage generation circuit that gradually increases or decreases the output voltage, and a binarization circuit that generates a binary timing signal according to the output voltage of the variable voltage generation circuit, and determines a time constant of the variable voltage generation circuit. A diode is connected in parallel to the resistor.

[Function] By configuring as described above, the time constant of the variable voltage generation circuit can be determined independently for the increasing direction and decreasing direction of the output voltage, and accordingly, a desired timing signal can be obtained. is now possible.

[Example] Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is a block diagram showing the entire recording and reproducing apparatus to which the timing signal generating apparatus of the present invention is applied. In this figure, HD is a recording/reproducing head, A is a recording amplifier (hereinafter referred to as a recording amplifier), A2 is a reproduction amplifier (hereinafter referred to as a reproduction amplifier), SWl and SW are switches, and C1
and C2 is a coupling capacitor.

In the circuit shown in Fig. 1, switch SW2 is used during recording.
is in a closed state (hereinafter referred to as ON), and switch SW1 is set in an open state (hereinafter referred to as OFF), and a recording current flows from recording amplifier A1 to head HD. Also, during playback, switch SWl is ON, switch SW
2 is turned off, and the reproduction signal obtained from the head HD is sent to the reproduction amplifier A2.

FIG. 2 is a detailed block diagram of the timing control circuit CNT shown in FIG. 1. In other words, in this diagram, in addition to controlling the 0N10FF of switches SW1 and SW2,
This is a circuit configuration for controlling ON10FF of the power supply of the recording amplifier A1. 3° 4.5, 6.7 shown in this diagram
are inverters each made of CMO3 or the like.

FIG. 3 is a waveform diagram illustrating the circuit operation of FIG. 2.

Waveforms (a) to (h) in FIG. 3 correspond to signals (a) to (h) in FIG. 2, respectively.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 to 3.

First, the operation when switching from the reproduction state to the recording state will be explained.

The inverter 3 shown in FIG. 2 is externally supplied with a control signal a for switching between a recording state and a reproducing state. In the reproduction state, the control signal a supplied from the outside is at a low level. At this time, the output signal S of the inverter 3 is at a high level, the input signal C of the inverter 4 is at a high level, and the output signal d of the inverter 4 is at a low level. Further, the human power signal e of the inverter 5 is at a high level, the output signal f of the inverter 5 is at a low level, the human power signal g of the inverter is at a low level, and the output signal of the inverter is at a high level.

Here, the power supply of the recording amplifier A1 is the signal d, the switch SW,
is the signal, and switch SW2 is set to 0N10FF by the signal f.
(ON when these signals are high level, OFF when these signals are low level).

Next, when the external control signal a switches to high level (that is, when the operating mode switches from the playback state to the recording state), the signals S and C immediately switch from the high level to the low level, and the signal d immediately changes from low level to high level. This is diode D
This is because the charge stored in the capacitor C3 is discharged through the capacitor C3. This timing is 1. (See Figure 3).

In addition, the human power signal e of the inverter 5 tries to change from high level to low level, but since it requires time to discharge the electric charge stored in the capacitor C4 via the resistor R2, as shown in FIG. As such, there is a delay in the fall of the waveform. As a result, the output signal f of the inverter 5 is
It changes from low level to high level at timing t2 delayed from tl.

Next, the input signal g of the inverter tries to change from low level to high level, but capacitor C5 is connected to resistor R4.
Since it takes time to charge the battery via the battery, there is a delay in the rise of the waveform, as shown in FIG. As a result, the output signal of the inverter transitions from high level to low level at timing t3 delayed from tl. Here, by setting R2X Ca < R4X Cs, the timing t can be set after t2.

As mentioned above, when switching from the playback state to the recording state, recording amplifier A is turned on at timing tl, then switch SW2 is turned on at timing t2, and then switch SW is turned on at timing t. Turn off. As a result, the transient current generated by charging the capacitor C3 when the recording amplifier A1 is turned on is reduced by the switch SW1.
It flows into the ground point through the head and does not flow into the head HD.

Also, when the capacitor CI is sufficiently charged, switch SW is turned on, and then switch SW is turned off.
12.1. By setting , transient current associated with switching these switches will not flow to the head HD.

Next, the operation when the recording/reproducing apparatus is switched from the recording state to the reproducing state will be described.

In the recording state, control signal a is high level,
Signal S is low level, signal C is low level, signal d is high level, and signal e is low level.

The signal f is at a high level, the signal g is at a high level, and the signal is at a low level. In this state, when the control signal a supplied from the outside changes from high level to low level at timing t4, signal A immediately changes to high level, signal g to low level, and signal 2 to high level. This is because the charge stored in the capacitor C5 is discharged via the diode D3.

However, the input signal C of the inverter 4 has a waveform as shown in FIG. 3 because it takes time to charge the capacitor C3 via the resistor R1. Therefore, the output signal d of the inverter 4 returns from high level to low level at timing t6.

Also, the human power signal e of the inverter 5 has a waveform as shown in FIG. 3 because it takes time to charge the capacitor C4 via the resistors R2 and R3. Therefore, the output signal f from the inverter 5 returns from high level to low level at the timing ts. Here, RI XC3>
By setting in advance so that (R2+R3)XC4, it is possible to satisfy ta < ts < ta. As described above, the charging time constant and the discharging time constant of each charging/discharging circuit are independently and arbitrarily set. Accordingly, the rise and fall timings of the three timing signals output from the inverter 4°5.7 can be set arbitrarily with respect to the control signal manually input to the inverter 3.

For example, in the above-mentioned recording and reproducing apparatus, when switching from the recording state to the reproducing state, switch SW is first turned ON at timing t4, then switch SW2 is turned OFF at timing t, and then recording is started at timing t6. The power of amplifier A1 is turned off.

As a result, the transient current generated by the discharge of the capacitor C1 when the power of the recording amplifier A1 is turned off is transferred to the switch SW.
Since it flows into the grounding point via the head, it does not flow into the head HD. Further, the DC potential of the head side input terminal of the capacitor C2 changes after the switch SW1 is turned ON.
Since w2 is OFF, it is always grounded. Therefore, the charge stored in the capacitor C2 is not discharged, and no current flows through the head HD due to charging and discharging of the capacitor C2.

[Effects of the Invention] As described above, according to the present invention, a desired timing signal can be easily obtained by applying a control signal of a predetermined level, so that controllers for various devices can be realized simply and at low cost. The special effect of being able to do this is obtained.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a recording/reproducing apparatus to which the timing signal generating device of the present invention is applied, FIG. 2 is a detailed block diagram of the timing control circuit shown in FIG. 1, and FIG. 3 shows the operation of FIG. 2. The waveform diagram shown in FIG. 4 is a diagram showing the prior art. A...Recording amplifier, A2...Reproduction amplifier, HD...Recording/reproduction head, 3-7...Inverter, R1, R2, R3, Ra...Resistor, Dr, D2, Ds , D4...
diode. Figure 1 Figure 3 Td Figure 4

Claims (1)

[Scope of Claims] 1) A timing signal generation device that sends out a timing signal in response to a control signal at a predetermined level, comprising: a variable voltage generation circuit that gradually increases or decreases an output voltage in response to application of the control signal; , comprising a binarization circuit that generates a binary timing signal according to the output voltage of the variable voltage generation circuit, and a diode is connected in parallel to a resistor that determines a time constant of the variable voltage generation circuit. Timing signal generator.