JPS62272756A - Pseudo halftone processer - Google Patents

Abstract

PURPOSE:To improve the resolution of a binary picture such as a character by deciding it as a white or black edge when the density difference between an object picture element and a reference picture element exceeds a prescribed value and outputting a white or black pattern independently of the output data of a dither processing section so as to detect the white or black edge thereby emphasizing the edge. CONSTITUTION:The density difference among a binarization object picture element data C, andreference picture data A, B is obtained. When the density difference S satisfies the relation of S>=alpha (alpha= a natural number being a parameter for detecting an edge), a data representing the white edge is stored corresponding to the picture data A, B and C. In inputting the addresses A, B, C satisfying said relation, a signal representing the white edge is outputted from a signal OUT 1. When the density difference S satisfies the relation of S<=-alpha, a signal representing the black edge is outputted from the signal OUT 1 similarly as above. The decision above is applied to all reference picture elements for the main and subscanning and in detecting an edge even at one location, the object picture element is outputted as a white or black level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pseudo intermediate processing device that binarizes halftone image data to express halftones in a pseudo manner.

2. Description of the Related Art A conventional pseudo-halftone processing device generally includes a main scanning counter 1 for counting the number of pixels in the main scanning direction and a sub-scanning counter 1 for counting the number of lines in the sub-scanning direction, as shown in FIG. Input the respective count values of counter 2, main scanning counter 1, and sub-scanning counter 2, and use this input data to create a 4×4 Bayer r-type dither pattern m as shown in FIG.
The comparator 4 inputs the dither pattern m generated by the decoder 3 and the multivalued image data k obtained by a predetermined image reading means, and compares the magnitude of the two.

Then, using the dither pattern m as a threshold value for binarization, the comparator 4 determines that the multi-valued image data k is equal to or larger than the threshold value (k
≧m), it becomes °'white'°, and conversely, when it is small (kpm), it becomes black, so that a pseudo-halftone is expressed by 3 /, -2 (Takahiko Fukinuki) Author: "Image Signal Processing for Fax and OA" (Nikkan Kogyo Shimbun). For example, image data k having a 16-gradation halftone pattern as shown in FIG. overlay the dither pattern m.)
When binarized, the binarized processed data (
In the figure, circles are black pixels, and frames without circles are white pixels.

) is obtained.

Problems to be Solved by the Invention However, with this configuration, it is possible to express a halftone image in a pseudo manner, but for example, as shown in FIG. There is a problem in that the image quality decreases, making it difficult to read.

The above-mentioned problem arises for the following reasons. In other words, as shown in Figure 7, the threshold value for binarization is different for each pixel within a 4x4 area, for example, and the white/black pattern obtained by binarization is dispersed. arise.

The present invention has been made in view of the above-mentioned problems, and allows characters to
An object of the present invention is to provide a pseudo halftone processing device that can improve the resolution of a binary image such as a screen.

Means for Solving the Problems In order to achieve the above object, the present invention provides a dither processing unit that binarizes image data quantized to 2n gradations, converts it into pseudo halftones, and outputs it as dither data. an image data timing adjustment unit that retrieves predetermined pixel data (target pixel) data and pixel data adjacent to the predetermined pixel (reference pixel) data stored in an image data storage unit that sequentially stores the image data; an arithmetic processing unit that takes in pixel data and dither data, considers the target pixel as white or black when the density difference between the target pixel and the reference pixel exceeds a predetermined value, and outputs this white/black information with priority over the dither data; It is equipped with

If the density difference between the target pixel and the reference pixel exceeds a predetermined value, 5.
, -1., it is determined that it is a white or black edge, and when this edge determination is made, a white or black pattern is output regardless of the output data of the dither processing section. Then, white or black edges are detected and the relevant portions are emphasized to improve the resolution of binary images such as characters.

Embodiment FIG. 1 is a block diagram showing a pseudo halftone processing apparatus according to an embodiment of the present invention.

This pseudo-halftone processing device consists of an image data storage circuit (hereinafter referred to as a storage circuit) 1 that sequentially stores multivalued image data k quantized into 2n gradations (16 gradations in this example).
1, and a dither processing unit 12 that performs dither processing on the multivalued image data k (P (i, J)), performs binarization, converts it into pseudo halftone data, and outputs it as dither data D;
A predetermined pixel (binarization processing target pixel, hereinafter referred to as target pixel) stored in the storage section 11. an image data timing adjustment circuit 6 that extracts the data of the target pixel and the data of the pixel adjacent to the target pixel (reference pixel) and outputs these;
・ ・ (hereinafter referred to as timing adjustment section) 13, target pixel data P (i, j) inputted from the timing adjustment section 13 and having a positional relationship as shown in FIG. j-1), P(i, j+1), P(
i=1, j), P(i+1, j) and dither processing section 1
The arithmetic processing circuit 14 outputs a predetermined arithmetic result in accordance with the binary dither data D input from 2.

The storage circuit 11 stores two lines of image data k.
AM21, a main scanning counter 22 that counts the number of pixels in the main scanning direction in synchronization with the image data k, and the pixel data taken out by the timing adjustment section 13, which is inputted to the RAM 2 according to the timing signal (2); The image data stored in the RAM 21 is stored at the address ADR issued by the main scanning counter 22.
The timing adjustment unit 1 sequentially extracts the image data 1 as image data 1.
It says to enter 3.

The dither processing unit 12 is configured as shown in FIG. This is the address D of the arithmetic processing unit 14.

The timing adjustment section 13 is set to lock C as shown in FIG.
It is equipped with three stages of series flip-flops 24, 25, and 26 synchronized by LK2, and the multi-level image data k and the image data output from the RAM 21 are input to the first stage flip-flop U. ing. Reference pixel data P (i,
j+1), P(i-1, j+1) to the gate buffer B, and also outputs the target pixel data P(i, j) of the output of the second stage flip-flop 5 to the dither processing unit 12. , the reference pixel data P(j, j+1) from the first stage flip-flops, and the reference pixel data P(l+1, j), P(i
−1, j), target pixel data P(i, j), and reference pixel data P(i, j) from the third stage clip-flop unit.
-1) are output to the arithmetic processing unit 14, respectively.

The arithmetic processing unit 14 uses reference pixel data P(i, j+1), P
It has a data selector 27 that inputs (l+1,j), and a data selector path that inputs reference pixel data P(i,j-1), P(i-1,j). These data selectors 27 use timing signals as shown in FIG.
The input data is output in sequence according to the input data. The data output from the data selector 27 and the data selector path are outputted from the arithmetic processing unit 14 as addresses A and B, respectively.
The 29 ROMs provided are man-powered.

In addition to the addresses A, B, and D mentioned above, the ROM 29 receives target pixel data P(i, j) outputted from the second flip-flop 5 as an address C. On the other hand, the ROM 29 is pre-stored with data set in the following manner, and this data can be taken out using addresses A, . . . B1C5D. In this case, for example, the upper bit,
Addresses A, B, C, and D of the lower bits are distributed and predetermined data is specified by a combination of these addresses. However, the designated extraction of predetermined data using addresses A, B, and CXD is not limited to this method.

The multilevel image data has 16 gradations in this embodiment, and the following calculations are performed on this limited gradation deposit, and predetermined data is stored in the ROM 29 based on the calculation results.

Binarization target pixel data C (target pixel data P(i, j) corresponds to address C, abbreviated as ICI for convenience) and reference pixel data A (reference pixel data P(i, j+1), P
(l+1,j); for convenience, it is abbreviated as "°A" corresponding to address A), reference pixel data B (
The density difference between the reference pixel data P (i, j-1) and P (j-1, j) (abbreviated as I B 1 for convenience) -8 = C - A, C - B is calculated. 0 When this density difference S satisfies the relationship S> α (α - natural number, parameter for edge detection), data indicating a white edge (for example, "1") is assigned to each image data A, B, C. 10 ·− that satisfies the above relationship.

When addresses A, B, and C are input, a signal ('1') indicating a white edge is output from signal 0UT1.

Furthermore, when the density difference S satisfies the relationship S<-α, data ('O') indicating a black edge is stored in association with each image data A, B, and C, and the above relationship is stored. When addresses A, B, and C that satisfy the requirements are input, the signal indicating a black edge (0
“) is now output.

Furthermore, if binary image data D corresponding to address D is stored and the density difference S satisfies the relationship ISl+α, binary image data D is output as signal OUT 1 by address D. ing.

Note that the ROM 29 outputs a mode selection signal 0UT2 in addition to the signal 0UT1. The mode selection signal 0UT2 is latched according to the timing signal ■ and is stored in the ROM2911 l.
-7 is fed back to the address CNTL, and this address CNTL is cleared by the timing signal ■ set at a timing shifted from the timing signal ■, as shown in FIG.

By setting the ROM 29 as described above, the ROM 29 outputs the signal 0UT1 in accordance with the procedure shown in FIG. 4, for example. That is, if the address CNTL is either mode '00' or 'old''10', a processing route is first set (step (hereinafter referred to as ST) 1). Here, if the mode is '00',
Proceeding to Sr1, the density difference 5=C-A is compared with the edge detection parameter α. Here, ISlα
If so, the process advances to Sr1, where the density difference 5=C-B is compared with the edge detection parameter α, and if IS1 is α, binary image data D is outputted as a signal OUT by address D. STI mode 10', Sr1
If -α>S in Sr1 and -α>S in Sr1, the signal 0UT1
outputs °0' indicating a black edge. Also,
When STI is set to mode '01', Sr1 is set to S>+α, and Sr1 is set to S>+α, signal 0UT1 outputs 1' indicating a white edge.

Note that the inputs of addresses A1B, C, and D, the mode selection signal 0UT2, and the address CNTL are sequentially switched according to the timing of each signal shown in FIG. white or black edges are detected at points of change (eg, the outline of a character). The above determination is made for all reference pixels in the main scanning and sub-scanning, and if an edge is detected at even one location, the target pixel is output as white or black.

When pseudo intermediate processing is applied to the character pattern expressed in 16 gradations as shown in FIG. 9 as described above using the edge detection parameter α-7, the result is shown in FIG.

In this result, the characters are clearer than the conventional processing result shown in FIG.

In this embodiment, a ROM is used in the arithmetic processing unit, and the density difference 13,<-4 obtained by performing arithmetic processing on the target pixel data and reference pixel data estimated to be input is compared with a reference value. While setting black or white data according to the comparison result, this black or white data is stored as a combination of target pixel data and reference pixel data, and the address of this black or white data is stored as a combination of target pixel data and reference pixel data. When data and reference pixel data are input, the results of arithmetic processing are outputted immediately, but instead, a general-purpose IC may be used to perform arithmetic processing each time according to the input signal.

In addition, in this embodiment, the binarization target pixel P is used as a reference pixel.
Pixels P(i, J+1), P(i-1, j), P(i+1) adjacent to (i, j) in the main scanning direction and sub-scanning direction
, j), but the binarization target pixel P(i, D
Other pixels adjacent to P(1-1, j-1), P(i=1
, j+1), P(i+1, j-1), P(i+1, J+
1) may be used as a reference pixel, and this reference pixel data may be used for calculations with target pixel data. Furthermore, P(
Of course, by performing the above calculation using all the pixels (8 pixels) adjacent to i, j) as reference images, effects greater than those of this embodiment can be obtained. Furthermore, by using the n-bit reference pixel data and the upper few bits, it is possible to reduce the scale of the multiple circuits, and a result equivalent to the above-mentioned result can be obtained.

Effects of the Invention As is clear from the above explanation, the present invention calculates the density difference between a pixel to be binarized and a reference pixel adjacent to this pixel, and if the density difference is greater than a predetermined value, a white or black edge is detected. When this edge determination is performed, priority is given to dither processing and output is given to the target pixel, making it easy to emphasize edges and improve the resolution of binary images such as characters. .

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a pseudo halftone processing device according to an embodiment of the present invention, Fig. 2 is a timing chart of signals of the same device, and Fig. 3 shows the positional relationship between pixels to be binarized and reference pixels. 4 is a flowchart showing the process by which data is output from the ROM of the device shown in FIG. 1, FIG. 5 is a conceptual diagram showing an example of the processing result by the device shown in FIG. 1, and FIG. A block diagram showing an example of a pseudo-157.7 halftone processing device, FIG. 7 is a diagram showing a Bayer r-type dither pattern used in the device, and FIG. 8 is an example of a processing result by the device in FIG. 6. The conceptual diagram, FIG. 9, corresponds to the processing results of FIGS. 5 and 8, and is a conceptual diagram showing halftone patterns input to each of the apparatuses of FIGS. 1 and 6. 11... Memory circuit, 12... Dither processing section, 13.
. . . Image data timing adjustment section, 14 . . . Arithmetic processing section, 29 . . . ROM. Name of agent: Patent attorney Toshio Nakao Haga 1st person
5 Figure 6 Figure 7 Figure 7 Fresh grass 1 Figure 8 Figure 9

Claims (1)

[Scope of Claims] An image data storage unit that sequentially stores image data quantized into 2^n gradations, and which binarizes the image data and outputs it as dither data converted into pseudo halftone data. a dither processing unit, predetermined pixel (target pixel) data stored in the image data storage unit, and a pixel adjacent to the target pixel (reference pixel);
an image data timing adjustment unit that extracts and outputs data, and takes in the target pixel data, the reference pixel data, and the dither data obtained by the dither processing unit, and the density difference between the target pixel and the reference pixel exceeds a predetermined value. and an arithmetic processing unit that regards a target pixel as white or black and outputs this information with priority over the dither data.