JPS62272712A - Filter - Google Patents

Abstract

PURPOSE:To prevent the increase in the memory capacity and to attain stable operation by arranging the plural number of ROMs, and shifting the phase of a signal supplying an address of the ROMs. CONSTITUTION:An NRZ signal inputted to a data input port 1 is inputted to an N-bit shift register 2, where the signal is shifted by one by bit at T sec each and stored therein. The content of storage of the shift register 2 is fed to ROMs #151, #252 to form part of addresses of ROMs 51, 52. A signal of M3=M2-1-bit except the LSB-bit among M2-bit of an output signal of a binary counter 4 is supplied as a part of the address of the ROM #151. Simultaneously, all the said M3 bits are fed to a phase shifter 8, where the signal (M3-bit) whose phase is retarded by phi si given to the ROM #252 to part of the address. Thus, the operating speed of the ROMs 51, 52 is halved and the capacity of the ROMs is halved.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a filter that shapes the waveform of digital data and outputs a desired time domain waveform.

[Conventional technology]

FIG. 10 shows, for example, the International Conference on Digital Satellite Communications (lCD5C).
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FIG. 1 is a configuration diagram of a conventional filter shown in Yoto, 1975, PP 87-90-. In the figure, 1
is the data input port for NRZ (Non return to zero) data, 2 is this data input port 1
The same clock rate as the NRZ signal input from) f. L indicates an N-bit shift register for sequential storage; 3 indicates the clock rate f; Clock Mllf that is Ml times L. L
The clock input port 4 receives the input from the clock input port 3, which is operated by the clock input from the clock input port 3. A read bit binary counter 5 outputs L-bit digital data written to the address by (N0Ml) address signals from the binary counter 4 and the N-bit shift register 2.
Memory (read-only memory.

ROM), 6 is an L-bit D/A converter that receives L-bit data from the ROM 5 and outputs an analog signal, and 7 is an output port that outputs the analog signal from the D/A converter 6.

Next, the operation will be explained. First, the parameters of this filter are determined as follows. N: Duration of impulse response (unit, bit) 2Mt: Number of samples per 1 bit of data (M, = 2'm: M,: number u). Therefore, the NRZ signal input to the data input port 1 is input to the shift register 2 of the N-bireto. Impulse response is N bits (or NT).

'r-/, 1b/. (time), so there are at most 2N different waveforms during the L1 basic time slot T time. Also, since the number of samples per 1 bit of data is M+, 2N-MI words are required to completely represent the output waveform. Here, since the number of output bits of the ROM 5, that is, the number of pits in each word, is L bits, the total memory size of the ROM 5 is 2"M.
It becomes l@L bit.

The ROM 5 uses an N-bit input data sequence and a total (N+Mi) bit signal of M2 bits from the binary counter 4 as an address signal, and corresponds to each address.
Store the amplitude value of the output waveform in L bits each'), T/
Data is output to the D/A converter 6 for each Ml. That is, the operating speed of the ROM 5 operates in synchronization with the clock Ml@foL of the clock input port 3.

Among the address signals of ROM 5, binary counter 4
The M3 bit signal supplied from the shift register 2
Its change is Ml times faster than the N-bit signal from
ntntt: the least significant bit) is counted up one by one.

FIG. 10 shows N=4. M Mayuzumi = 3. An example of the configuration when L=6 bits is shown, and FIG. 11 shows a single pulse response as an example of an analog signal output from the output port door. In Figure 11, the number of samples per bit MI
The case where =2M2=8 is shown. Also, ROM
By changing the memory contents corresponding to address 5, it is possible to obtain an arbitrary output time domain waveform, and it is also possible to obtain an output waveform free from code amount interference, which is often used in data transmission.

[Problem that the invention seeks to solve]

Since the conventional filter is configured as described above, when the input data rate increases, the sampling clock must be increased accordingly, and the ROM is required to operate at high speed.

In addition, if the duration of the impulse response is long, the ROM
With the increase in the number of addresses in
There were problems such as the need for

This invention was developed in order to eliminate the problems of the conventional ones as described above, and does not recognize the need to increase the sampling clock even when the input data rate increases, and requires high-speed operation of the ROM. It is an object of the present invention to provide a filter that operates stably without requiring an increase in memory capacity due to an increase in the number of addresses.

[Means for solving problems]

The filter according to the present invention is a shift register.

In addition to a filter consisting of a ROM, a D/A converter, and a binary counter, a plurality of phase shifters and ROMs that change the phase of the clock by a certain amount are prepared, and the plurality of ROs described above are prepared.
The output data of M is selected by a data selector and the result is used as a filter output.

Further, a filter according to another aspect of the present invention is one in which a low-pass filter is attached to the output stage of the above filter.

[For production]

The filter according to the present invention processes data written in multiple ROMs in parallel by using a signal having a phase different from that of the input data sequence as an address, and operates at an equivalently higher clock rate. Hello, ROM
To stably perform high-speed operation as a filter without requiring high-speed operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In the figure, the same parts as in Figure 1O are designated by the same reference numerals.
In the figure, reference numerals 51 and 52 designate a ROM 51 whose addresses are the outputs of the shift register 2 and the binary counter 4 as a first storage means, and 52 a second storage means. 8 is
A phase shifter 9 delays the phase of the output signal of the binary counter 4 by a certain amount φ and outputs it as part of the address of ROM#252, ROM#151, R2M1752
This is a data selector that alternately selects the output data of and outputs the data to the D/A converter 6.

Next, the operation of this invention will be explained. First, the NRZ signal input to the data input port 1 is input to the N-bit shift register 2, where it is shifted by 1 bit every T seconds and stored. The memory contents of this shift register 2 are ROM
Sent to $151 and ROM#252, each ROM5
1.52 forms part of the address. On the other hand, the frequency of the clock input from clock input port 3 is Ml@f
o, but the LSB (that is, the fastest changing) bit of the output signal M2 bits of the binary counter 4 is removed, and the M3=Mz −1 bit signal is sent to the ROM#151.
given as part of the address. Also, at the same time, the above M3
All the bits are given to the phase shifter 8, and the signal M3 bit, whose phase is delayed by φ, is given to the R2M1752 and becomes part of the address. ROM#l 5 in Figure 2
1 and R2M1752 are shown. (a) is from binary counter 4, can) is from phase shifter 8
It will be input manually. In the figure, Ms=3. In the figure, the phase delay caused by the phase shifter 8 is indicated as φ. From this, the frequency at which the addresses of each ROM 51 and 52 change is 1
・For fCL, ROM 5 in Fig. 10 shown in the conventional example
It can be seen that half the operating speed is sufficient.

The contents of ROM#151 and ROM$252 shown in FIG. 1 have completely different contents written therein. Mayu, in Figure 3,
A single pulse response is shown as an example. In Figure 3, the above RO
The data written in M#151 and R2M1752 is the waveform amplitude value at the time indicated by the arrow, and these amplitude values are different data even when the ROM51.52 is at the same address. It is shown that. Also, the third
In the figure, cases where the addresses of the ROMs 51 and 52 are the same are surrounded by dotted lines.

As described above, ROM#151, ROM#252
Data are outputted from the data selector 9, and these data are alternately selected by the data selector 9. The selection time is T,'
M is every. FIG. 4 shows the output data of the ROMs 51 and 52 and the output data of the data selector 9. When the output data of the data selector 9 is applied to the D/A converter 6, a desired stepped filter output waveform is obtained as output analog data. That is, with the configuration shown in FIG. 1, the operating speed of each ROM 51, 52 can be halved, and the capacity of the ROM can be halved. This means that even if the input data rate is equivalently doubled and the impulse response duration is 1 bit longer, the same storage capacity R
This makes it possible to configure a filter using OM.

In FIG. 1, the output of the D/A converter 6 is directly connected to the output port door to obtain a stepped waveform. It is also possible to obtain a smooth output waveform by connecting the area filter 10.

FIG. 5 shows a filter according to another embodiment of the invention. In the figure, the input side of the low-pass filter lO is connected to the output side of the D/A converter 6, and the output side thereof is connected to the output port door.

The operation of the filter shown in FIG. 5 is the same as that shown in FIG. 1 until the output of the D/A:l' inverter 6 is obtained, so a description thereof will be omitted.

Said 4. The spectrum of the step-like waveform obtained from the output of the converter 6 is shown in Figure 6), in addition to the baseband spectrum G (f), there are also baseband spectra for each integer multiple of the frequency Ml·fCL centered around that frequency. G (f
) folded spectra will be lined up infinitely.

In normal carrier wave pulse transmission, elements such as amplifiers and modulators have finite bands, and the transmission path also has finite bands, so harmonic components of the spectrum shown in Figure 6(a) is attenuated and, as a result, only the baseband is treated. However, when signals in various frequency bands are multiplexed as in frequency multiplexing, harmonic spectral components fall into other signal bands and deform the signal spectrum existing there.

Therefore, in such a multiplex transmission system, it is necessary to limit the signal band to only the base band. In such a case, the effect of inserting the low-pass filter 10 shown in FIG. 5 becomes obvious. The effective bandwidth of the low-pass filter 10 in FIG. 5 is such that the baseband spectrum G (f) is completely passed through and G (f
) can be freely selected within a range that provides a value that can be removed.

The spectrum after passing through such a low-pass filter is shown in Figure 6 (
, ). Further, an example of the time domain waveform is shown in FIG. In FIG. 7, (a) is the output waveform of the converter 6, and (b) is the output waveform after passing through the low-pass filter 10.

In addition, in the above-mentioned embodiment, the configuration in which the number of ROMs is two is shown, but it is also possible to further increase the number of ROMs. FIG. 8 shows another embodiment in which there are five ROMs. Further, FIG. 9 shows the phase relationship of the output data of each ROM and the output data of the data selector 9 corresponding to the configuration diagram of FIG. 8. With this configuration, the input signal data rate can be up to three times higher, and the storage capacity of each ROM can be IA.

〔Effect of the invention〕

As described above, according to the present invention, the circuit configuration is such that a plurality of ROMs are arranged and the phase of the signal giving the address of the ROM is shifted by a certain amount, so there is no need for high-speed operation of the ROM. This has the effect of preventing an increase in memory capacity due to an increase in , and providing a filter that operates stably. Also, by inserting a low-pass filter in the output stage),
This has the effect of providing a filter that outputs a smooth waveform.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a filter according to an embodiment of the present invention, FIGS. 2, 3, and 4 are time domain waveform diagrams illustrating an embodiment of the present invention, and FIG. 5 is a diagram of a filter according to an embodiment of the present invention. FIGS. 6 and 7 are spectral characteristics and time domain waveform diagrams for explaining the configuration of FIG. 5, respectively, and FIG. 8 is a circuit diagram of a filter showing an embodiment of another invention. 9 is a time domain waveform diagram explaining the embodiment of FIG. 8, FIG. 10 is a circuit diagram of a conventional filter, and FIG. 11 is a diagram of the circuit diagram of a conventional filter. FIG. 3 is an output time domain waveform diagram of the filter. In the figure, 1 is a data input port, 2 is a shift register, 4 is a binary counter, and 5 and 51 to 53 are ROMs.
(storage means), 6 yes converter, 8 and 81.82
is a phase shifter, 9 is a data selector, and 10 is a low-pass filter. Amplitude (b) Width (c) (a) (b) 6. Contents of correction Procedures for writing correction spontaneously) 6.! , 9・-5 Showa month day

Claims (3)

[Claims] (1) A shift register that temporarily stores the NRZ signal input from the data input port, a binary counter driven by a clock that is an integral multiple of the clock rate of the NRZ signal, and an output of the binary counter and the shift register. a first storage means whose address is the output of the
a plurality of phase shifters that change the phase of the output of the binary counter by a fixed amount; a plurality of second storage means whose addresses are the outputs of the phase shifters and the outputs of the shift register; and the addresses. a data selector that selects the output data of the first and second plurality of storage means read according to the clock rate at a speed that is an integral multiple of the clock rate; and D/A conversion of the output data of the data selector. A filter equipped with a D/A converter. (2) a shift register that temporarily stores the NRZ signal input from the data input port; a binary counter driven by a clock that is an integral multiple of the clock rate of the NRZ signal; and an output of the binary counter and the shift register. a first storage means whose address is the output of the register, a plurality of phase shifters that change the phase of the output of the binary counter by a fixed amount, the output of the plurality of phase shifters, and the shift register. a plurality of second storage means whose addresses are the outputs of the first and second storage means, and output data of the plurality of first and second storage means read according to the addresses at a speed that is an integral multiple of the clock rate. a data selector to
D/A converting the output data of the data selector
The filter according to claim 1, further comprising a converter. (3) a low-pass filter that filters an output signal of a D/A converter that D/A converts the output data of the data selector; filter.