JPS62271518A - Chopper type comparator - Google Patents

Abstract

PURPOSE:To quicken the signal transmission and to reduce power consumption by providing a buffer circuit to a comparator to reduce the input capacitance viewed from a signal source. CONSTITUTION:A signal potential Vs and a reference potential Vr are applied respectively to one terminal of switches 2, 4 of a chopper type inverter and the other terminals are connected in common. A sourse followr buffer circuit comprising MOS transistors (TRs) 5A, 5B is connected to the common connecting point, one terminal of a capacitor 6 is connected to the source of the TR 5A, an inverter amplifier 7 comprising TRs 7A, 7B is connected to the other terminal and a switch 8 is connected in parallel with the amplifier 7. Inverter amplifiers 11, 13 similar to the amplifier 7 are connected to the post-stage of the amplifier 7 via a capacitor 9. Then the input capacitance viewed from the input terminal is decreased by using the circuit 5 so as to use the stray capacitance of the TR 5A only, the signal transmission is quickened and the power consumption of the inverters is reduced.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a chopper type comparator used in an AD converter or the like.

[Summary of the invention]

The present invention relates to a chopper type comparator, and provides a buffer circuit immediately before a capacitor in the input stage to enable high-sensitivity and good comparison.

[Conventional technology]

The chopper type comparator is constructed as shown in FIG. In the figure, the terminal (41) to which the signal potential v9 is supplied
are connected to each other through a switch (42), and a terminal (43) to which reference potential Vr is supplied is connected to each other through a switch (44), and the midpoint of this connection is connected to one end of a capacitor (45). The other end of this capacitor (45) is connected to the input of an inverter amplifier (46), the input and output of this amplifier (46) are connected through a switch (47), and the output of this amplifier (46) is connected to the input of an inverter amplifier (46). )
connected to one end of the The other end of this capacitor (48) is connected to the input of an inverter amplifier (49), and the input and output of this amplifier (49) are connected through a switch (50), and the output of this amplifier (49) is connected to the inverter amplifier (49). An output terminal (52) is led out through the terminal (51).

In this circuit, switches (44) (47) (
50) are controlled to be turned on and off at a high potential, for example, with the same phase of the clock signal 77, and the switch (42) is controlled on and off by a clock signal φS having an opposite phase. This causes switches (44) (47) (5
0) is turned on, the reference potential Vr is supplied to the circuit, and the capacitor (45) (
4B), charging is performed. And then the switch (42)
is turned on and the switches (44, 47, and 50) are turned off, and if the signal potential vs from the terminal (41) is even slightly higher than the reference potential Vr, the output of the amplifier (46) becomes a low potential. , the output of the amplifier (49) becomes a high potential, and a low potential is output to the output terminal (52). Further, when the signal potential VS is even slightly lower than the reference potential Vr, a high potential is output to the output terminal (52).

In this circuit, each inverter amplifier (46)
The specific configurations of (49) and (51) are shown in FIG. In other words, the other end of the capacitor (45) is a P-type MOS) transistor (46P) and an N-type MO
S) Connected to the gate of the transistor (46N), the source of this transistor (46P) is connected to the power supply terminal (53), the source of the transistor (46N) is grounded, and the transistor (46P) (46N) is connected to the gate of the transistor (46N).
) are connected to each other, and the inverter output is taken out from this connection midpoint.

Similarly, the inverter amplifiers (49) and (51) are P-type MOS transistors <49P) (5
1P) and N-type MO3I-transistor (49N)
(51N) is provided.

However, when trying to apply this device to a so-called flash type AD converter, for example, in order to obtain an 8-bit digital signal, the above-mentioned device must be
It is necessary to provide 5 pieces in parallel.

In that case, as mentioned above, the input stage has a capacitor (
45), even if this one capacitance value is small, for example 0.5 to 0.6 pF, when it is multiplied by 255, the input as seen from the signal source side The capacitance value becomes extremely large. For this reason, time is required for charging and discharging the capacitor each time the switch is changed, which reduces the signal transmission speed and becomes an obstacle to increasing the speed of the AD converter.The power consumption for this charging and discharging is also extremely large. There was a risk that it would become a thing.

The reason why the capacitors (45) (48) and amplifiers (46) (49) are provided in the above circuit is to absorb so-called field-through errors.
Theoretically, only the circuit on the left side of the amplifier (46) and switch (47) is required.

[Problem that the invention seeks to solve]

As described above, in the conventional technology, the input capacitance value of the device increases significantly, which causes problems such as a decrease in signal transmission speed and an increase in power consumption.

[Means for solving problems]

The present invention has a signal potential terminal (11 is a first switch (2)
and the reference potential terminals (3) are connected to each other through the second switch (4), this connection point is connected to one end of the capacitor (6) through the buffer circuit (5A) (5B), and the other end of this capacitor The end is connected to the input of the inverter amplifier (7P) (7N), and the third switch (8) is connected between the input and output of this inverter amplifier.
the first and second switches are driven in opposite phases, and the third switch is connected to the second
This is a chopper type comparator that is driven in the same phase as the switch.

[Effect]

According to this, since the input capacitance of the device seen from the signal source side is reduced by providing the buffer circuit, the signal transmission speed becomes faster (and the power consumption can be reduced).

〔Example〕

In FIG. 1, a terminal (11
is connected to one end of the switch (2), a terminal (3) to which reference potential Vr is supplied is connected to one end of the switch (4), and the other ends of this switch (2) +41 are connected to each other. This connection midpoint is the depression type Mo
It is connected to the gate of the S transistor (5^), the drain of this transistor (5A) is connected to the power supply terminal (10), and the source channels are connected to each other.
Furthermore, the source of this transistor (5A) is connected to the drain of a depletion type Mo3) transistor (5B), the gate and source channels of this transistor (5B) are connected to each other, and the midpoint of this connection is grounded. This constitutes a source follower buffer circuit.

Furthermore, the source of the transistor (5A) is connected to the capacitor (6A).
), and the other end of this capacitor (6) is connected to a P-type MoS transistor (7) that constitutes an inverter amplifier.
P) and the gate of an N-type Mo3I-transistor (7N), the source of this transistor (7P) is connected to the power supply terminal (10), the source of the transistor (7N) is grounded, and the transistor (7P) (7N
) are connected to each other, and the inverter output is taken out from this connection midpoint.

The connection midpoint of the drains of the transistors (7P) (7N) and the other end of the capacitor (6) are connected through a switch (8).

Further, the connection midpoint of the drains of the transistors (7P) (7N) is connected to one end of the capacitor (9), and the other end of this capacitor (9) is connected to the connection point of the drains of the transistors (7P) (7N).
P constituting an inverter amplifier connected in the same way as N)
It is connected to the gates of a type MOS transistor (LIP) and an N type MOS transistor (IIN). The drains of this transistor (IIP) (IIN > are connected to each other, and the midpoint of this connection and the transistor (IIP) (
IIN) is connected to the gate of IIN through a switch (12). And this transistor (IIP) (IIN
) P-type MO3) transistor (13P) and N-type Mo3I that constitute the inverter amplifier from the connection midpoint of the drain of
- Output terminal (14) is led out through transistor (1311).

In this circuit, transistors (5A) (5B)
By making the sizes of the transistors (5
This transistor (5B) is connected between the drain and source of B).
A current that makes the gate-source voltage VGS of 0 is passed,
By flowing this current between the drain and source of the transistor (5A), the gate-source voltage VCS of the transistor (5A) is reduced to 0. Therefore, the gain of the buffer circuit consisting of this transistor (5A) (5B) is approximately By setting the flag to 1, the comparator operation of the circuit is performed in the same manner as in the prior art. In this case, by providing a buffer circuit, the signal source (input terminal (11)
The input capacitance seen from (31) is only the so-called overlap capacitance of the transistor (5A), and since this overlamp capacitance is generally about o, oipp, it is necessary to reduce the capacitance seen from the signal source side to about 1150 compared to the conventional one. Can be done.

This is how signals are compared,
According to the above-described device, the input capacitance value seen from the signal source side is significantly reduced. Therefore, the signal transmission speed is increased and power consumption is also reduced.

Furthermore, even if a large number of such devices are provided in parallel, the risk of a decrease in signal transmission speed or an increase in power consumption due to the increase in input capacitance is reduced, and this is particularly suitable when configuring a flash type AD converter.

Further, according to the above-mentioned device, since the buffer circuit is provided at the input end, radiation of noise generated inside the device to the input side is blocked, and in particular clock noise caused by switching of the switch (8) etc. is blocked. It is possible to prevent the possibility of affecting the input side.

Fig. 2 is a general block diagram of the above-mentioned circuit, and in the figure, terminal +1 to which the signal potential Vs is supplied.
1 and a terminal (3) to which reference potential Vr is supplied are connected to each other via a switch (21 (41), and the middle point of this connection is connected to a capacitor (6) through a buffer circuit (5).
At the same time, the other end of this capacitor (61) is connected to an inverter amplifier (7), and a switch (8) is connected between the output of this inverter amplifier (7) and the other end of the capacitor (6). Further, the output of the inverter amplifier (7) is connected to one end of the capacitor (9),
The other end of this capacitor (9) is connected to the inverter amplifier (11
) and this inverter amplifier (11)
A switch (12) is provided between the input and output of the inverter amplifier (11), and an output terminal (14) is led out from the inverter amplifier (11) through an inverter amplifier (13).

In this circuit, by setting the gain of the buffer circuit (5) to approximately 1, a comparison similar to the conventional one is performed, and by providing the buffer circuit (5), the input capacitance is reduced and the signal transmission speed is increased. At the same time, power consumption can be reduced.

Note that the above-mentioned circuit is applicable not only to ordinary MO3I transistors but also to circuits using 50L SIT, GaAs, etc.

(Effects of the Invention) According to the present invention, the provision of the buffer circuit reduces the input capacitance of the device as seen from the signal source side, thereby increasing the signal transmission speed and reducing power consumption. Now you can.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 and 4 are diagrams for explaining the conventional technology. fil (31 is a terminal, (21(4) (El) is a switch, (5A) (5B) is a buffer circuit, (6) is a capacitor, (7P) (7N) is an inverter amplifier.

Claims (1)

[Claims] A signal potential terminal passes through a first switch, and a reference potential terminal is connected to each other through a second switch, this connection point is connected to one end of a capacitor through a buffer circuit, and the other end of this capacitor is connected to one end of a capacitor. It is connected to the input of an inverter amplifier, and the input and output of this inverter amplifier are connected through a third switch, and the first and second switches are driven in opposite phases, and the third switch is A chopper type comparator driven in phase with the second switch.