JPS62269249A - Address conversion index buffer device - Google Patents
Address conversion index buffer deviceInfo
- Publication number
- JPS62269249A JPS62269249A JP61112918A JP11291886A JPS62269249A JP S62269249 A JPS62269249 A JP S62269249A JP 61112918 A JP61112918 A JP 61112918A JP 11291886 A JP11291886 A JP 11291886A JP S62269249 A JPS62269249 A JP S62269249A
- Authority
- JP
- Japan
- Prior art keywords
- attribute information
- page
- address
- locality
- index buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000013507 mapping Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は番地変換装置の番地変換索引緩衝装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address translation index buffer for an address translation device.
従来の技術
第２図は従来の複数系統の論理番地検索部、物理番地蓄
積部からなるセソトアンシエイティブ法によるマツピン
グを使用した番地変換索引緩衝装置の概念図である。被
変換論理番地は第２図（２Ｌ）に示すようにタグ部Ｔ、
インデクス部工、オフセット部０から成っている。前記
被変換論理番地のインデクス部が第２図（１））に示す
ようにアドレスデコーダ１の入力端子１１に与えられデ
コード出力が出力端子１２より論理番地検索部２，３、
物理番地蓄積部４，５に出力される。前記デコード出力
により前記論理番地検索部２．３のそれぞれにおいて１
つの記憶場所が選択され前記記憶場所に格納されている
タグと前記論理番地検索部２，３の入力端子２１．２２
に与えられる被変換物理番地のタグ部との比較がそれぞ
れ独立に行われる。前記タグ両者が一致する系統があれ
ば前記被変換論理番地に対応する物理番地が前記系統に
格納されていることになり前記系統の論理番地検索部２
の出力端２４より一致信号が前記系統物理番地蓄積部４
の入力端４１に出力され、前記系統物理番地蓄積部４の
出力端４４より物理番地が出力される。BACKGROUND OF THE INVENTION FIG. 2 is a conceptual diagram of a conventional address translation index buffer using mapping based on the sesotropic method, which includes a plurality of systems of logical address search units and physical address storage units. As shown in FIG. 2 (2L), the logical address to be converted is a tag part T,
It consists of an index section and an offset section 0. The index part of the logical address to be converted is given to the input terminal 11 of the address decoder 1 as shown in FIG.
It is output to the physical address storage units 4 and 5. 1 in each of the logical address search units 2.3 by the decoded output.
One memory location is selected and the tag stored in the memory location and the input terminals 21 and 22 of the logical address search units 2 and 3
The comparison with the tag part of the physical address to be converted given to is performed independently. If there is a system in which both the tags match, it means that the physical address corresponding to the logical address to be converted is stored in the system, and the logical address search unit 2 of the system
A coincidence signal is output from the output terminal 24 of the system physical address storage section 4.
The physical address is output from the output terminal 44 of the system physical address storage section 4.
また前記比較結果が不一致の場合いずれの系統の物理番
地蓄積部にも前記被変換論理番地が格納されていないこ
とがわかる。これと並行して置換系統裁定回路６は無作
為に１つの系統を選択し出刃端６１．６２を介して置換
系統候補信号を前記系統論理番地検索部２，３、物理番
地蓄積部４．５に出力する。前記一致信号の得られなか
った系統では前記置換系統候補信号を見てその系統が置
換候補となっておれば前記系統論理番地検索部に被変換
論理番地のタグ部を前記系統物理番地蓄積部に置換物理
番地を前記記憶場所に格納する。Further, if the comparison results do not match, it can be seen that the logical address to be converted is not stored in the physical address storage section of any system. In parallel with this, the replacement system arbitration circuit 6 randomly selects one system and sends the replacement system candidate signal via the cutting edges 61 and 62 to the system logical address search units 2 and 3 and the physical address storage units 4 and 5. Output to. In the system for which the matching signal was not obtained, the replacement system candidate signal is checked, and if that system is a replacement candidate, the system logical address search section sends the tag part of the logical address to be converted to the system physical address storage section. A replacement physical address is stored in the memory location.
発明が解決しようとする問題点
しかしながら上記の様な構成では前記番地変換索引緩衝
装置内に変換したいページの論理番地に対応する変換情
報が存在しない場合、無作為に１つの系統が選択され前
記ページの変換情報で置換が行われる。前記系統に他の
系統に較べて吏用頻度の高いページの変換情報が格納さ
れていた場合、使用頻度の低いページの変換情報が前記
番地変換索引緩衝装置内に留ることになシ被変換論理番
地に対する変換有効率を低下させていた。Problems to be Solved by the Invention However, in the above configuration, if there is no conversion information corresponding to the logical address of the page to be converted in the address conversion index buffer, one system is selected at random and the page is Replacement is performed with the conversion information of . If the system stores conversion information for pages that are used more frequently than other systems, the conversion information for pages that are used less frequently will remain in the address conversion index buffer. The conversion effectiveness rate for logical addresses was reduced.
本発明はかかる点に濫みてなされたもので簡易な構成で
各系統間のページ朗用頻度を推定し醍用頻度の高いペー
ジの変換情報を前記番地変換索引緩衝装置内に留まらせ
ておくことにより被変換論理番地に対する変換有効率を
向上させた番地変換索引緩衝装置を提供することを目的
としている。The present invention has been made in view of this problem, and has a simple configuration to estimate the page recitation frequency between each system and to retain conversion information of frequently used pages in the address conversion index buffer. It is an object of the present invention to provide an address conversion index buffer device which improves the conversion efficiency rate for logical addresses to be converted.
問題点を解決するための手段
本発明は上記問題を解決するため、複数系統の論理番地
検索部、物理番地蓄積部からなるセットアソシエイティ
ブ法によるマツピングを使用し前記論理番地検索部の各
登録自答毎にページ属性情軸を有し、各系統毎の前記ペ
ージ属性情報の比較を行う属性情報比較回路と、前記比
較結果を１つの入力とし置換系統候補を選択する置換系
統裁定回路を備え、前記属性情報比較回路により局所性
の低いページの格納されている系統を検出しその系統番
号を置換系統裁定回路に出力し前記置換系統裁定回路は
選択された前記局所性の低いページの格納されている系
統に置換系統候補信号を出力し番地変換索引緩衝装置内
に局所性の高い変換情報を残すものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention uses mapping based on a set associative method consisting of multiple systems of logical address search units and physical address storage units, and each register of the logical address search unit an attribute information comparison circuit that has a page attribute information axis for each answer and compares the page attribute information for each system, and a replacement system arbitration circuit that uses the comparison result as one input and selects a replacement system candidate, The attribute information comparison circuit detects the system in which the page with low locality is stored and outputs its system number to the replacement system arbitration circuit, and the replacement system arbitration circuit detects the system in which the selected page with low locality is stored. A replacement system candidate signal is output to the existing system, and conversion information with high locality is left in the address conversion index buffer.
作用
本発明は前記した構成により属性情報比較回路によυ各
系統のページ属性情報を比較することにより局所性の低
いページを罐用頻度の低いページとしてその系統を選択
し変換情報を置換することにより餌用頻度の高いページ
の変換情報を番地変換索引緩衝装置内に留め高い論理番
地変換有効率が得られる。Effect of the present invention With the above-described configuration, the attribute information comparison circuit compares the page attribute information of each system, selects a page with low locality as a page with low frequency of use, and replaces the conversion information. This allows the conversion information of pages that are frequently used as bait to be retained in the address conversion index buffer, and a high logical address conversion effectiveness rate can be obtained.
実施例 第１図は本発明の一実施例を示す概念図である。Example FIG. 1 is a conceptual diagram showing an embodiment of the present invention.
第１図において１はアドレスデコーダであって被変換論
理番地インデクス部入力端子１１とデコード信号出力端
子１２を有する。２は論理番地検索部で被変換論理番地
タグ部入力端子２１とデコード信号入力端子２２と置換
系統候補信号入力端子２３と一致信号出力端子２４と属
性情報出方端子２５を有する。３は論理番地検索部で被
変換論理番地タグ部入力端子３１とデコード信号入力端
子３２と置換系統候補信号入力端子３３と一致信号出力
端子３４と属性情報出力端子３５を有する。In FIG. 1, reference numeral 1 denotes an address decoder, which has an input terminal 11 for a logical address to be converted, and an output terminal 12 for a decoded signal. Reference numeral 2 denotes a logical address search unit having a logical address tag input terminal 21 to be converted, a decode signal input terminal 22, a replacement system candidate signal input terminal 23, a match signal output terminal 24, and an attribute information output terminal 25. 3 is a logical address search unit having a logical address tag input terminal 31 to be converted, a decode signal input terminal 32, a replacement system candidate signal input terminal 33, a match signal output terminal 34, and an attribute information output terminal 35.
４は物理番地蓄積部で一致信号入力端子４１とデコード
信号入力端子４２と置換系統候補信号入力端子４３と物
理番地出力端子４４と置換物理番地入力端子４６を有す
る。５は物理番地蓄積部で一致信号入力端子５１とデコ
ード信号入力端子５２と置換系統候補信号入力端子５３
と物理番地出力端子５４と置換物理番地入力端子５５を
有する。4 is a physical address storage unit having a coincidence signal input terminal 41, a decode signal input terminal 42, a replacement system candidate signal input terminal 43, a physical address output terminal 44, and a replacement physical address input terminal 46. 5 is a physical address storage unit having a coincidence signal input terminal 51, a decode signal input terminal 52, and a replacement system candidate signal input terminal 53.
, a physical address output terminal 54 , and a replacement physical address input terminal 55 .
６は置換系統裁定回路で置換系統候補信号出力端子６１
．６２と置換系統入力端子６３を有する。6 is a replacement system arbitration circuit and a replacement system candidate signal output terminal 61
．． 62 and a replacement system input terminal 63.
７は属性情報比較回路で置換系統出力端子７１と属性情
報入力端子７２．７３を有する。以上のように構成され
た本実施例の番地変換索引緩衝装置について以下その動
作を説明する。被変換論理番地のインデクス部がアドレ
スデコーダ１の入力端子１１に与えられデコード出力が
出力端子１２より論理番地検索部２，３、物理番地蓄積
部４．６に出力される。前記デコード出力により前記論
理番地検索部２．３のそれぞれにおいて１つの記憶場所
が選択され前記記憶場所に格納されているタグと前記論
理番地検索部２．３の入力端子２１゜２２に与えられる
被変換論理番地のタグ部との比較がそれぞれ独立に行わ
れる。前記タグ両者が一致する系統があれば前記被変換
論理番地に対応する物理番地が前記系統に格納されてい
ることになり前記系統の論理番地検索部よシ一致信号が
前記系統物理番地蓄積部に出力され前記系統物理番地蓄
積部より物理番地が出力される。また前記比較結果が不
一致の場合いずれの系統の物理番地蓄積部にも前記被変
換論理番地が格納されていないことがわかる。これと並
行して前記記憶場所に格納されているそれぞれのページ
属性情報を読み出し属性情報比較回路７に出力し属性情
報比較回路７においてこれの比較を行う。通常データに
は局所性がありこの局所性はそのページの属性によって
傾向が異なり一般に手続部の方がデータ部に対しより高
い局所性を有している。この性質よりデータ部のページ
に対し前記属性情報比較回路は局所性の高いページすな
わち吏用頻度の高いページである手続部のページの番地
変換情報を積極的に番地変換索引緩衝装置内に残すよう
に置換候補となる系統を選択しなければならない。例え
ばページの属性情報として手続部をφ、データ部を１と
定義しておけば属性情報の小さい方が局所性が高く前記
属性情報比較回路アにおいて前記各系統間の属性情報を
比較し局所性の低い方の系統つまり属性情報の大きい方
の系統番号を置換系統出力端子７１に出力する。属性情
報比較結果が等しい場合無作為にある１つの系統を選択
する。置換系統裁定回路は前記系統番号により置換系統
に対し置換系統候補信号を出力する。前記一致信号が得
られなかった系統では前記置換系統候補信号を見てその
系統が置換候補となっておれば前記系統論理番地検索部
に被変換論理番地のタグ部を前記系統物理番地蓄積部に
置換物理番地を前記記憶場所に格納する。これにより吠
用頻度の高いページの変換情報を番地変換索引緩衝装置
内に留まらせておくことができる。7 is an attribute information comparison circuit having a replacement system output terminal 71 and attribute information input terminals 72 and 73. The operation of the address conversion index buffer device of this embodiment configured as described above will be explained below. The index portion of the logical address to be converted is applied to the input terminal 11 of the address decoder 1, and the decoded output is outputted from the output terminal 12 to the logical address search units 2, 3 and the physical address storage unit 4.6. One memory location is selected in each of the logical address search units 2.3 by the decoded output, and the tag stored in the memory location and the tag applied to the input terminals 21 and 22 of the logical address search unit 2.3 are selected. Comparison of each converted logical address with the tag part is performed independently. If there is a system in which both the tags match, it means that the physical address corresponding to the logical address to be converted is stored in the system, and the logical address search unit of the system sends a match signal to the system physical address storage unit. The physical address is output from the system physical address storage section. Further, if the comparison results do not match, it can be seen that the logical address to be converted is not stored in the physical address storage section of any system. In parallel with this, each page attribute information stored in the storage location is read out and output to the attribute information comparison circuit 7, where the attribute information comparison circuit 7 compares the information. Normally, data has locality, and this locality varies depending on the attributes of the page, and generally the procedure division has higher locality than the data division. Due to this property, the attribute information comparison circuit for pages in the data division actively leaves the address conversion information of pages in the procedure division, which are pages with high locality, that is, pages that are frequently used, in the address conversion index buffer. Therefore, we must select a lineage that is a candidate for replacement. For example, if the procedure section is defined as φ and the data section as 1 as attribute information of a page, the smaller the attribute information, the higher the locality. The system with the lower value, that is, the system number with the larger attribute information, is output to the replacement system output terminal 71. If the attribute information comparison results are equal, one system is selected at random. The replacement system arbitration circuit outputs a replacement system candidate signal to the replacement system based on the system number. In the system for which the matching signal is not obtained, the replacement system candidate signal is checked, and if that system is a replacement candidate, the system logical address search section sends the tag part of the logical address to be converted to the system physical address storage section. A replacement physical address is stored in the memory location. This allows the conversion information of frequently used pages to remain in the address conversion index buffer.
発明の効果
以上述べてきたように、本発明によればきわめて簡易な
回路構成で、高い論理番地変換有効率を提供することが
できることから本発明にかかる番地変換索引緩衝装置は
極めて産業上価値の高いものである。Effects of the Invention As described above, according to the present invention, it is possible to provide a high logical address conversion efficiency rate with an extremely simple circuit configuration. Therefore, the address conversion index buffer device according to the present invention has extremely high industrial value. It's expensive.
第１図は本発明の一実施例における番地変換索引緩衝装
置の構成概念図、第２図は従来の番地変換索引緩衝装置
の構成概念図である。
１・・・・・・アドレスデコーダ、２・・・・・・論理
番地検索部、３・・・・・論理番地検索部、４・・・・
−・物理番地蓄積部、５・・・・・・物理番地蓄積部、
６・・・・・・置換系統裁定回路、７・・・・・・属性
情報比較回路。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図FIG. 1 is a conceptual diagram of the configuration of an address conversion index buffer according to an embodiment of the present invention, and FIG. 2 is a conceptual diagram of the configuration of a conventional address conversion index buffer. 1...Address decoder, 2...Logical address search unit, 3...Logical address search unit, 4...
- Physical address storage unit, 5...Physical address storage unit,
6... Replacement system arbitration circuit, 7... Attribute information comparison circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure
Claims (1)
ットアソシエィティブ法によるマッピングを使用し前記
論理番地検索部の各登録内容毎にページ属性情報を有し
、各系統毎の前記ページ属性情報の比較を行う属性情報
比較回路と、前記比較結果を１つの入力とし置換系統候
補を選択する置換系統裁定回路を備えてなる番地変換索
引緩衝装置。Using mapping based on the set associative method consisting of multiple systems of logical address search units and physical address storage units, page attribute information is provided for each registered content of the logical address search unit, and the page attribute information for each system is 1. An address conversion index buffer comprising: an attribute information comparison circuit that performs a comparison; and a replacement system arbitration circuit that receives the comparison result as one input and selects a replacement system candidate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61112918A JPH0766351B2 (en) | 1986-05-16 | 1986-05-16 | Address conversion index buffer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61112918A JPH0766351B2 (en) | 1986-05-16 | 1986-05-16 | Address conversion index buffer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62269249A true JPS62269249A (en) | 1987-11-21 |
| JPH0766351B2 JPH0766351B2 (en) | 1995-07-19 |
Family
ID=14598742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61112918A Expired - Lifetime JPH0766351B2 (en) | 1986-05-16 | 1986-05-16 | Address conversion index buffer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0766351B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07287671A (en) * | 1994-04-20 | 1995-10-31 | Kofu Nippon Denki Kk | Replacement circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53132232A (en) * | 1977-04-25 | 1978-11-17 | Hitachi Ltd | Control system for address conversion buffer memory |
-
1986
- 1986-05-16 JP JP61112918A patent/JPH0766351B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53132232A (en) * | 1977-04-25 | 1978-11-17 | Hitachi Ltd | Control system for address conversion buffer memory |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07287671A (en) * | 1994-04-20 | 1995-10-31 | Kofu Nippon Denki Kk | Replacement circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0766351B2 (en) | 1995-07-19 |
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