JPS62260447A - Multivalued signal identification circuit - Google Patents

Abstract

PURPOSE:To minimize errors in terms of identification timing, which are caused by the frequency fluctuation and a change in temperature, by identifying a multivalued signal with the aid of plural bits more than necessity for identifying the inputted multivalued signal and controlling a voltage controlled oscillator through the use of the product between the inclination of an error signal obtained in such a way and that of a reception base band signal CONSTITUTION:An inclination decision circuit 4 obtains the polarity (m) of the differential coefficient of the reception base band signal in an identification point, that is, an inclining direction. An exclusive OR circuit 5 exclusively ORs the 3rd and fourth bit outputs D3 and D4 of an analog/digital converter 2, supplies it to the clock input C of a flip flop 6. When 'l' is inputted to the clock input C, the flip flop 6 outputs the value of the 3rd bit output D3 to a multiplier 7. It does not depend on the inclination of the reception base band signal, and outputs a code corresponding to the mistaken direction of the identification timing. A smoothing filter 8 integrates the output, and takes it for the control signal of the voltage controlled oscillator 9, whereby the operation can track so that the error of the identification timing can be automatically minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is used for demodulating a multilevel orthogonal amplitude modulation signal. In particular, it relates to phase adjustment of clock synchronization for identifying received data.

[Conventional example]

Recently, from the viewpoint of effective use of radio frequencies, 16.64.
Research is being carried out on multilevel orthogonal amplitude modulation methods such as H.256. In such a multilevel modulation method, timing deviation from the optimum identification point has a large effect on code error characteristics. Regarding this, Saito (Y.

5aito) 4th, r Facility Consideration Op High Level CAM Multi-Carrier
System (Feasibility Con5ider
ation of old GH-1 level QAM) 1u
lti-carrier System) J, IC
C'84, pp. 665-671. Therefore, realizing clock synchronization with small timing deviation is an important issue.

FIG. 7 shows a block diagram of a general conventional clock synchronization circuit.

This clock synchronization circuit performs full-wave rectification on a demodulated signal using a full-wave rectifier circuit 71 to extract a clock component, and suppresses amplitude fluctuation components and noise components of this clock component using a resonance circuit 72, a limiter circuit 73, and a phase-locked loop. do. The phase loop is composed of a multiplier 74, a low pass filter 75 and a voltage controlled oscillator 76. The thus obtained reproduced clock is adjusted to an optimal phase by a phase shifter 77 and output to the identification circuit.

[Problem that the invention seeks to solve]

However, in the conventional clock synchronization circuit described above, the phase of the recovered clock fluctuates due to frequency fluctuations of the voltage controlled oscillator 76 and fluctuations in ambient temperature, and the identification timing may deviate from the optimal phase. Therefore, it is not suitable for use in a multilevel orthogonal amplitude modulation method.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multilevel signal identification circuit that suppresses phase errors in identification timing due to frequency and temperature fluctuations and identifies multilevel orthogonal amplitude modulated signals.

[Failure to solve the problem]

The multi-value signal identification circuit of the present invention includes an analog-to-digital converter for identifying a 2N-value received baseband signal, and adjustment means for optimally adjusting the identification timing of the analog-to-digital converter. , the analog-to-digital converter converts N+M bits of 2 (a
The adjustment means is configured to output a signal train, and the adjustment means includes means for determining a slope direction of the received baseband signal amplitude;
The present invention is characterized in that it includes calculation means for calculating a phase shift based on the tilt direction determined by this means and the output value of the lower M bits of the analog-to-digital converter.

Here, N and M are integers of 1 or more.

[For production]

The multilevel signal identification circuit of the present invention converts a received baseband signal into a digital signal of N+M bits, uses the upper N bits of the output as an identification output, and calculates the slope of this identification output and the amount of error indicated by the lower M bits. The clock phase is adjusted by the calculated value.

When a 2N-value received baseband signal is binarized, an N-bit signal is obtained. Therefore, when a 2N-value signal is identified by N0M bits, an identification output signal is obtained in the upper N bits, and an error signal due to an error in identification timing is obtained in the lower M bits.

That is, if there is an error in the identification timing, a value larger than the expected digital value is output from the analog-to-digital converter. Here, assuming that the identification timing is small to some extent, the lower M bits of the analog-to-digital converter will indicate an error in the identification timing.

If the slope of the received baseband signal is positive, the error will be positive if the identification timing is delayed, and the error will be negative if the identification timing is early. If the slope is negative, the sign of the error is opposite. Therefore, the sign of the product of the error and the polarity of the slope always matches the sign of the identification timing error.

The multilevel signal discrimination circuit of the present invention uses this principle to adjust discrimination quimming.

〔Example〕

FIG. 1 is a block diagram of a multilevel signal identification circuit according to a first embodiment of the present invention. This embodiment is a circuit that identifies N=2, M-2, that is, a 4-value signal, and adjusts the clock phase using a 2-bit error signal.

A four-value received baseband signal is input to the input terminal 1. Input terminal 1 is connected to an analog-to-digital converter 2. The first and second bit outputs D1 and D2 of the analog-to-digital converter 2 are supplied to an output terminal 3 and a slope determination circuit 4. The third bit output D3 of the analog-to-digital converter 2 is supplied to the first input of the exclusive OR circuit 5 and to the data output of the flip-flop 6. The fourth bit output D4 of the analog-to-digital converter 2 is supplied to the second input of the exclusive OR circuit 5. The output of the exclusive OR circuit 5 is the clock C of the flip-flop 6.
supplied to The output of the slope determination circuit 4 and the output Q of the flip-flop 6 are supplied to a multiplier 7. Multiplier 7
The output of is supplied to a voltage controlled oscillator 9 via a smoothing filter 8. Voltage controlled oscillator 9 is connected to analog-to-digital converter 2 and slope determination circuit 4 .

The analog-to-digital converter 2 outputs a 4-bit binary code sequence in response to the 4-value received baseband signal. As a result, the first bit output D1 and the second bit output D
An identification output signal is obtained at 2, and an error signal is obtained at 3rd bit output D3 and 4th bit output D4.

The slope determination circuit 4 determines the polarity m of the differential coefficient of the received baseband signal at the identification point, that is, the direction of the slope.

The exclusive OR circuit 5 calculates the exclusive OR of the third bit output D3 and the fourth bit output D4 of the analog-to-digital converter 2, and supplies this to the clock input C of the flip-flop 6. The flip-flop processor outputs the value of the third bit output D3 to the multiplier 7 when "1" is input to the clock input C.

Therefore, the deviation of the input signal level from the optimum point is ±d
When the deviation is less than /4, the flip-flop 6 outputs the third focus output D3, and when the deviation is larger than this, the flip-flop 6 holds the previous state. here,
"d" represents the minimum signal amount voltage.

The multiplier 7 multiplies the polarity m output from the slope determination circuit 4 by the output Q of the flip-flop processor.

Smoothing filter 8 integrates the output of multiplier 7 and supplies a control signal to voltage controlled oscillator 9 . The voltage controlled oscillator 9 is
The analog-to-digital converter 2 and the slope determination circuit 4 include
A clock indicating the identification timing is supplied.

Table 1 shows the relationship among the outputs of the analog-to-digital converter 2, exclusive OR circuit 5, flip-flop 6, and multiplier 7. In the table, rA/D output", rEXOR
J, rFFJ, and "multiplier" indicate the outputs of the analog-to-digital converter 2, exclusive OR circuit 5, flip-flop 6, and multiplier 7, respectively, and "~" indicates that the previous state is held.

Table 1 FIG. 2 shows a block diagram of the tilt determination circuit 4. As shown in FIG.

The first bit output D1 of the analog-to-digital converter 2 is
A data input of flip-flop 41 and a digital comparator 43 are provided. The second bit output D2 of the analog-to-digital converter 2 is applied to the data input of a flip-flop 42 and to a digital comparator 43. The clock power from the voltage controlled oscillator 9 is fed to the flip-flop 41.
42 clock inputs. flip flop 4
The output of 1.42 is fed to digital comparator 43.

Digital comparator 43 is connected to multiplier 7.

The flip-flop 41 is the analog-to-digital converter 2
The first bit output D1 is sampled and the output DI' is supplied to the digital comparator 43. flip flop 4
2 is the second bit output D of the analog-to-digital converter 2
2 and output D2N to digital comparator 4.
Supply to 3.

The digital comparator 43 receives the values represented by the first bit output D1 and the second bit output D2 and the value D' one clock before, and compares their magnitude. Therefore, the output of the digital comparator 43 is equal to the polarity m of the differential coefficient of the received baseband signal at the discrimination point. Table 2 shows the relationship between these values.

Table 2 Next, it will be explained that the direction of the error in the identification timing in the analog-to-digital converter 2 and the sign of the output of the multiplier 7 match. .

FIGS. 3 and 4 show the relationship between received baseband signals and timing errors. FIG. 3 shows the case where the slope of the received baseband signal is positive, ie, m=1, and FIG. 4 shows the case where the slope is negative, ie, m=-1.

First, a case will be described in which the slope is positive, the identification timing is delayed from the optimal timing, and the phase shift Δt is positive. At this time, the third bit output D3 of the analog-to-digital converter 2 becomes "1".

Here, if the fourth bit output D4 is "1", the deviation of the signal level from the optimum point is large, ±d/4 or more (in this case, the output of the multiplier 7 is the previous value). will be held.

If the fourth bit output D4 is "-1", the flip-flop 6 outputs "1", so the output of the multiplier 7 is "1".
”.

When the slope is positive and the phase shift Δt is negative, the third bit output D3 becomes "-1". At this time, the fourth bit output D
If 4 is "-1", the signal level deviation is ±d/4 or more, and the outputs of the flip-flop 6 and the multiplier 7 are held. If the fourth bit output D4 is "1",
Flip-flop 6 outputs "-1", and multiplier 7 outputs "-1".

When the slope is negative, the third bit output D3 becomes "-1" when the phase shift Δt is positive, and becomes "1" when it is negative. Therefore, similarly to the case where the slope is positive, when the phase shift Δt is positive, the output of the multiplier 7 becomes "1", and when the phase shift Δt is negative, the output of the multiplier 7 becomes "-1". When the phase shift Δt is large, the output of the multiplier 7 is held.

In this way, the multiplier 7 outputs a code corresponding to the error direction of the identification timing, without depending on the slope of the received baseband signal. By integrating this output with the smoothing filter 8 and using it as a control signal for the voltage controlled oscillator 9, it is possible to follow the identification timing so as to automatically reduce the error.

FIG. 5 is a block diagram of a multilevel signal discrimination circuit according to a second embodiment of the present invention. Similarly to the first embodiment, this embodiment is a circuit that identifies N=2, M=2, that is, four plant numbers, and adjusts the clock phase using a 2-bit error signal. This embodiment differs from the first embodiment in the circuit configuration for determining the inclination.

A four-value received baseband signal is input to the input terminal 1. Input terminal 1 is connected to analog-to-digital converters 2 and 2'. The first of analog-to-digital converter 2
, second bit outputs DI, D2 and first and second bit outputs D1, D2 of the analog-to-digital converter 2' are supplied to a digital comparator 43. The third bit output D3 of the analog-to-digital converter 2 is supplied to the first input of the exclusive OR circuit 5 and to the data output of the flip-flop 6. The fourth bit output D4 of the analog-to-digital converter 2 is supplied to the second input of the exclusive OR circuit 5. The output of the exclusive OR circuit 5 is supplied to the clock input C of the flip-flop processor. Digital comparator 4
3 and the output Q of flip-flop 6 are supplied to multiplier 7. The output of multiplier 7 is supplied to voltage controlled oscillator 9 via smoothing filter 8 . The voltage controlled oscillator 9 is connected to the analog-to-digital converter 2 via a 172 frequency divider circuit 10, and includes flip-flops 11 and 1.
/2 frequency divider circuit 12 to analog/digital converter 2
′.

This embodiment uses two analog-to-digital converters 2.2'
are operated using clocks with different phases, and the slope of the received baseband signal is determined by comparing the magnitude of the two obtained values. Since the other configurations are the same as those of the first embodiment, the following description will be omitted.

The 172 frequency divider circuit 10 divides the output signal of the voltage control circuit 9 into 1
The frequency is divided by 72 and the clock is supplied to the analog-to-digital converter 2. The flip-flop 11 is a voltage controlled oscillator 9
The output signal is delayed and a clock is supplied to the analog-to-digital converter 2' via the 172 frequency divider circuit 12.

FIG. 6 shows a time chart. (al is the output signal of the voltage controlled oscillator 9, (b) is the output signal of the 172 frequency divider 10, (C) is the output signal of the flip-flop 11, (dl
show the output signals of the 172 frequency divider circuit 12, respectively.

The analog-to-digital converter 2 takes in the input signal level at the rising point of the output signal of the 172 frequency divider circuit 10.

On the other hand, the analog-to-digital converter 2' has 172
The input signal level is captured at the rising point of the output signal of the 172 frequency divider circuit 12, which is delayed by one period from the output signal of the frequency divider circuit 10. Since the operating timings of the two analog-to-digital converters 2 and 2' are different, the first and second bit outputs D1 and D2 of each are compared by the digital comparator 43 to determine the polarity of the differential coefficient of the received baseband signal. can be found.

In the above embodiments, the case where M=2 and N=2 was explained as an example, but the present invention can be implemented in the same way with other values.

Furthermore, in the above embodiments, the slope of the received baseband signal is determined using the output of the analog-to-digital converter, but the present invention can be implemented in the same manner even if the input signal thereof is used for determination.

〔Effect of the invention〕

As explained above, the multi-value signal identification circuit of the present invention identifies the input multi-value signal with a number of bits greater than necessary to identify the input multi-value signal, and distinguishes the resulting error signal from the input multi-value signal. The slope and product of the received baseband signal are used to control the voltage controlled oscillator.

Therefore, errors in identification timing caused by frequency fluctuations and temperature fluctuations can be suppressed.

Since the present invention can adjust the identification timing with high precision,
The present invention can be used in a multilevel quadrature amplitude modulation method such as the 16.64.2 SQAM method to realize a highly accurate and highly stable demodulator.

[Brief explanation of drawings]

FIG. 1 shows the first embodiment of the present invention! ! FIG. 2 is a block configuration diagram of a signal identification circuit. FIG. 2 is a block diagram of the tilt determination circuit. The third is a diagram showing the relationship between the received baseband signal and timing error. FIG. 4 is a diagram showing the relationship between received baseband signals and timing errors. FIG. 5 is a block diagram of a multilevel signal identification circuit according to a second embodiment of the present invention. Figure 6 is a time chart. FIG. 7 is a block diagram of a conventional clock synchronization circuit. DESCRIPTION OF SYMBOLS 1...Input terminal, 2.2'...Analog-digital converter, 3...Output terminal, 4...Inclination judgment circuit, 4
1... Flip-flop, 42... Flip-flop, 43... Digital comparator, 5... Exclusive OR circuit, 6... Flip-flop, 7... Multiplier,
8... Smoothing filter, 9... Voltage controlled oscillator, 10
...172 frequency divider circuit, 11...flip-flop,
12...172 frequency divider circuit. Patent applicant Naotaka Ide, patent attorney representing Nippon Telegraph and Telephone Corporation. ””'I2. "V 屓 2 Figure I (Toad 1 Yo) 7\'Work M 3 Figure 4 -, ! Noku Negative 4 Romi 2 Example 35 Figure 4tK" f level
Towards demodulation - Figure 36

Claims (1)

[Claims] (1) In a multi-level signal identification circuit comprising an analog-to-digital converter for identifying a received baseband signal of 2^N values, and an adjusting means for optimally adjusting the identification timing of this analog-to-digital converter, The converter is configured to output a binary signal string of N+M (N and M are integers of 1 or more) bits, and the adjustment means includes means for determining the slope direction of the received baseband signal amplitude; A multi-level signal discriminating circuit comprising: arithmetic means for determining a phase shift based on the determined inclination direction and the output value of the lower M bits of the analog-to-digital converter.