JPS62260423A - Bipolar logic circuit - Google Patents

Abstract

PURPOSE:To reduce the output low/high propagation time of a switching time as the titled circuit by designing the circuit that a base electric charge of an output transistor(TR) is sucked in the base as a collector current of the 2nd TR connected to the collector of the 1st TR. CONSTITUTION:When a low-level voltage is applied to an input terminal 3, a diode 12 and a TR 13 are conductive, resulting in that a TR 14 is conductive, a base electric charge of a TR 7 is sucked via diodes 17, 18 together with the base electric charge of a TR 8 and the TR 8 is nonconductive. On the other hand, a TR 5 is conductive and TRs 6, 7 are nonconductive, then TRs 9, 10 are conductive, a current flows from a high-potential power supply 1 via a resistor 30 to an output terminal 4, which goes to a high level. Thus, the timing when the TR 8 is nonconductive approaches the timing when the TR 7 is nonconductive and the circuit having short output low/high propagation time as the switching time is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar logic circuit, and particularly to an output circuit of a bipolar logic circuit.

[Conventional technology]

Figure 2 shows, for example, the '84 Mitsubishi Semiconductor Data Book High Hole.
It is a conventional bipolar logic circuit shown on page 1a2-s of latitude p<hxasrrxa>,
In the figure, Hl is a high potential power supply terminal, (21 is a low potential power supply terminal, (31 is an input terminal, (41 is an output terminal, (
5) The pace is the input terminal (31 has the emitter resistance (to)
The collector connects the low potential to the power supply (11) through the low potential power supply (2
1 is connected to the emitter of the transistor (61, and the collector is connected to the high voltage through the resistor 4). 5BDnpn) transistor connected to potential power supply fi+, (8
) is connected to the emitter of the transistor (7), whose collector is the output terminal f4Hc, and whose emitter is connected to the low potential power supply (21) of the 5BDnpn transistor, (9
) is connected to the collector of the transistor (7) whose collector is connected to the high potential power supply +11 through the resistor -5.
EDnpn) transistor Tr, [101 has a pace connected to the emitter of the transistor (9), a collector connected to the collector of the transistor (91), and an emitter connected to the output terminal (4).
npn) transistor (hereinafter referred to as npnTr) connected to
), CEI is an 8 transistor whose pace and collector are connected to the transistor (8) through resistors cii> and (to), respectively, and whose emitter is connected to the low potential power supply (2).
BDnpn) transistor, 051 has an anode connected to the transistor (7) and a cathode connected to the transistor (51).
Schottky diode (hereinafter referred to as S) connected to the pace of
BD).

Next, the operation of the circuit configured as above will be explained.

First, when a low level signal is applied from the input terminal (31) to the pace of the transistor (6), the transistor 161
becomes conductive, and as a result, the transistors +61 and 171 become non-conductive, and the transistors +61 and 171 become non-conductive, and the transistor (8) becomes non-conductive because the transistors +61 and 171 become conductive transiently and draw out the pace charge of the transistor (8). In addition, the transistors (7) become non-conductive and the transistors +91 and +1
01 becomes conductive, and the potential of the output terminal (41 flows from the high potential power supply 11 through the resistor -, and the output terminal 14) becomes high.

On the other hand, when a high level signal is applied from the input terminal (3) to the pace of the transistor 161, the transistor (6
) becomes non-conductive, resulting in transistor +81,
ill and igl become conductive and suck current from the output terminal (4), so the potential of the output terminal (41) becomes the ROC level.At this time, since the transistor (7) is conductive, the transistors +91 and tlol become non-conductive. It is something that

[Problem that the invention seeks to solve]

Conventional bipolar logic circuits are configured as described above, so when the input is low, transistor (7) becomes non-conductive, then transistor (to) becomes conductive, and transistor (8) becomes non-conductive. (but it's a transistor)
The time it takes for the circuit to change from non-conductive to conductive is slow, and even when it is conductive, the current value is limited by the resistor.Therefore, there are problems in that the switching time as a circuit and the high propagation time are long.

This invention was made to solve the above-mentioned problems.
Is it possible to obtain a bipolar logic circuit that can shorten the propagation time? purpose.

[Means for solving problems]

The bipolar logic circuit according to the present invention has a first transistor whose pace receives an input signal, whose emitter is connected to a high potential power supply, and whose emitter is connected to the collector of this transistor whose emitter is connected to a low potential power supply and which outputs an output signal. transistor and a second transistor connected to the pace of the preceding transistor.
It is equipped with transistors.

[Effect]

In this invention, as the input signal switches from high level to low level, the first transistor becomes conductive, the second transistor becomes conductive, and as a result, the pace charge of the output transistor is extracted. The timing at which the output transistor becomes non-conductive approaches the timing at which the preceding stage transistor of the output becomes non-conductive when the voltage is applied to the input pnp (input pnp) transistor of the circuit, and the output low and high propagation times of the switching time as a circuit are shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

Are the same symbols in the figure the same as in Figure 2? show.

In the figure, (Ill is an SBD whose anode is connected to input terminal 13, t12) i cathode is input terminal 3+
The EIEID% state connected to VC is connected to the cathode of the diode (11) and the anode of the diode (12J), and the emitter is connected to the high potential power supply through the resistor 2I19...
A pnp transistor whose collector is connected to the low potential power supply +21 VC through a resistor, the collector of this transistor (131) is connected to the emitter of this transistor (131), and the emitter is connected to the high potential power supply H1 through a resistor string. !9BDnpn transistor connected to !9BDnpn transistor, +lfG with cathode connected to collector of transistor 7 node connected to pace of transistor (8), 11η anode connected to pace of transistor 5Bp1QSi anode connected to cathode of this diode nη 5BDSαIt− connected to the collector of transistor I
j S whose anode is connected to the emitter of the transistor field
BD% wire is a pn diode connected to the cathode of this diode 01, a11i is a pn diode whose anode is connected to the cathode of this diode 4, and the solid near node is a pn diode whose cathode of this diode 4 is connected to the low potential power supply 12). The diode has an anode connected to the collector of the transistor (13) and a cathode connected to this transistor (13).
An SBD is connected to the pace of I3, and (to) an SBD whose anode is connected to the collector of the transistor I and whose cathode is connected to the input terminal.

Next, the operation of the circuit configured as described above will be explained.

First, when a low level is applied to the input terminal (31), the diode IJ2 and the transistor become conductive, and as a result, the transistor +141 becomes conductive, and the diode 71. The pace charge of the transistor (71) is sucked in through the transistor (8), and the transistor (8) becomes non-conductive.

On the other hand, transistor (5) becomes conductive and transistor 16
1 and 171 become non-conductive, the transistor +
91, tlol becomes conductive, current flows from the high potential power supply +11 to the output terminal (41) through the resistor -, and the output terminal becomes high state. In this way, in the non-embodiment, transistor IJ4 becomes conductive. Since the transistor α41 immediately becomes conductive and extracts the pace charge from the transistor (8), the timing at which the transistor (81) becomes non-conductive is determined by the transistor (8).
7) approaches the timing when it becomes non-conductive.

Next, when a high level signal is applied to the input terminal (3), the diode (11) becomes conductive and the transistor (1)
becomes non-conductive, so that the diode ++91; 12
[1ml, +n becomes conductive, transistor I becomes non-conductive, while transistor (6) becomes non-conductive, transistors (6) to (8) become conductive, and the output terminal (output terminal 41 sucks current). The potential of the transistor 141 is in a low state. At this time, the transistor (7) is conductive, so the transistors !91 and tlol are in a non-conductive state.

〔Effect of the invention〕

As described above, according to the bipolar logic circuit according to the present invention, the pace charge of the output terminal transistor is absorbed as the collector current of the second transistor connected to the collector of the first transistor. The timing at which the output transistor becomes non-conductive approaches the timing at which the pre-output transistor becomes non-conductive,
Compared to conventional circuits, switching time output is reduced,
This has the effect of shortening the high propagation time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a bipolar logic circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional bipolar logic circuit. In the figure, (11 is a high potential power supply terminal, (2) is a low potential power supply terminal, (31 is an input terminal, (4) is an output terminal,
tel, α311 (pnp) transistor, +61,
+71, (81*(91,041iSBDnp,n
) transistor, tlol it n pn transistor% to), ug, oa, sB, 117
), S&, α→, fl, 1241 is S B D
, 121m, 2IJ, E t's p n
Diode, :2S, "jt5, 27+, c
2a, 2! J, ull, and Is' are resistors O. Note that the same reference numerals in the drawings indicate the same or equivalent parts.

Claims (1)

[Claims] a first transistor whose pace is connected to an input terminal of an inverter circuit constituting the transistor-transistor logic and whose emitter is connected to a high potential power supply;
a second transistor whose emitter is connected to the low potential power source to the collector of the first transistor; its anode is connected to the collector of the output transistor of the transistor-transistor logic and its cathode is connected to the collector of the second transistor; a first diode and an anode connected to the gate of a transistor preceding the output transistor of the transistor-transistor logic; a second diode and an anode connected to the cathode of the second diode; a cathode connected to the collector of the second transistor; A bipolar logic circuit, comprising a third diode connected to a third diode.