JPS62259164A - Computer and real time voice recognizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to electronic computers and real-time speech recognizers, and more particularly to computers having interconnected parallel processors.

(Prior Art) Parallel processing and symbolic processing are the main trends toward realizing real-time computation. Real-time applications of multiplication require rapid logical decisions using stored knowledge and processing large amounts of data at high speed.Furthermore, the tight coupling between symbolic and numerical computations , speech and image understanding and recognition, robotics, weapons systems, and industrial facility control.In fact, the widespread use of small computers in offices and homes, and the increasing use of artificial intelligence and robotics The emergence of a field of research has drawn attention to the fact that the amount of computational effort devoted to non-numeric or symbolic computations is increasing, and many of the tools used with computers, such as editors, compilers, and debuggers, are software tools are expanding the use of symbolic processing.Symbolic computation is an addition to numerical and statistical methods for solving problems because qualitative information or a priori knowledge can be made available in the form of databases and procedures. It leads to new methods.

For example, attempts to solve real-world problems that require human-like intelligence in robotics, speech, and vision are challenging to solve real-world problems that require human-like intelligence in robotics, speech, and vision. Because of the amount of a priori information and the high data rate from the sensors, a huge amount of symbolic and numerical computing power is required. In fact, signal processing of sensor data
Occurring in fields such as acoustics, sonar, seismology, voice communications, bioengineering, etc., typical purposes of such processing include estimating characteristic parameters, removing noise, and converting to a more desirable format. be. Traditionally, most signal processors are configured to suit the performance and efficiency of a small number of specific algorithms. Future signal processors will be able to compute high-resolution eigensystem beamforming and optimal Wiener filtering on the same processor, and to efficiently implement new algorithms as they are developed. Further increases in speed and algorithmic flexibility will be required. The ability to handle a wide range of algorithms in military systems allows for a variety of algorithms to be used during missions and to update field facilities with new algorithms. Traditional vector techniques are unable to meet the ever-increasing demands on computer performance, and future designs will need to be able to efficiently exploit wide concurrency. (March 1983, 22-Orléans, USA, EEE Computer Association, "IEEE International Training Session on Computer System Organization", IEE
Macaulay (McAul) of E issue 83 C81879-6
ay ) direction in rVLsI, parallel array or vector machine? J (ParallelArrays o
r Vector Machines, Which
Direction in VLSI? ), as well as L.S. Haynes
, R.L. Lau, D.P. Siewior
ek), and D.W. Mitsuel (D,W,
Mizell)'s ``Computer J''
er H5(1), 9 (1982), and IEE
J.E. Newsletter, 73(5), 852 (1985).
Allen (J, At1en), and A.D. McAulay (A, D) in IEEE Field 5 Conference Bulletin 85 CH2123-8 (1985).
ay)). The contents of these references, along with all other references, are discussed herein.

Very large scale integration in semiconductor devices is also leading towards greater use of parallel processing methods.

Parallel processing requires some kind of interconnection between processing elements, which results in a trade-off between speed and the ability to handle a wide range of algorithms.

For example, composite interconnect networks offer some flexibility at the expense of speed, and higher speeds can be obtained with fixed interconnects for certain algorithms. The problem then is to obtain extremely high speeds by efficiently using a large number of processing elements, and at the same time retain extremely high algorithmic flexibility. Efficiency for parallel processing is the speed gain over using a single processor of the same type divided by the number of processors. The complexity of the processing elements is also related to the degree of parallelism that can be achieved. That is, sophisticated calculations tend to have parts that cannot be columnarized at a coarse level. Overall speed is dominated by parts that cannot be parallelized at a coarse level.

The large number of high speed basic processors then places a significant communication burden on the interconnects between the processors. There is a need for a parallel processor interconnect with easy reconfigurability.

Currently, most experimental systems show that it is difficult to obtain parallel processing for a range of algorithms, even with a moderate number of processors (March 1983). 22-Orléans, USA, I
EEEE Computer Association, "IEEE International Training Session on Computer System Organization", IEEE Publication 83CH
Direction in Macaulay's rVLsI of 1879-6,
Parallel array or vector machine? ”. Number of parallel processors that can be used efficiently (and hence speed)
is limited by communication delays and interconnect complexity in the present prototype and proposed system. The constraints imposed by interconnections on algorithm design are a significant problem because they reduce the opportunity to gain performance with new algorithm designs and increase costs by limiting the scope of application and lifetime of equipment. It is.

Fixed interconnections limit the range of algorithms that can be efficiently executed. For example, the limitations of bus structures in parallel computation using new machines have been considered (
NASA Langley Research Center's NA on Advances and Trends in Structures and Mechanics, October 22, 1984.
Macaulay's ``Finite Elem Computation J for Recently Adjacent Connected Machines'' at the SA Symposium.
entComputationonNearest
Neighbor Connected Machine
nes )).

Systolic configurations such as those being developed at Carnegie Mellon University (rlEEE Computers, 1)
Kung H.T., January 982 issue, pp. 37-46, “Why Systolic?”
Is it architecture? J (Why Systoric
Architectures? )) @This reduces communication time and allows efficient use of multiple processors in parallel. However, since it is a fixed interconnection, the algorithm is highly constrained.

Algorithmic flexibility is obtained by complex reconfigurable interconnect networks (Siegel, F. J., 1984, Lexington Books, ``Interconnect Networks for Massively Parallel Processing''). , Theory and Case Studies J (Interconnection N
etworks for Large 5cale P
Arallel Processing, Theor
yand Ca5e 5tudy )), and a prototype system with eight processors and Banyan switches is in operation at the University of Texas in Austin, USA (``Physics Today'').
Today) Volume 37, No. 5 (May 1984), Brown J. C., Parallel Architectures for Computer Systems J (
p3rallel Architecture for
Computer Systems)) *Banyan is a multi-channel switch configured with 2x2 switch levels. However, this type of reconfigurability causes large delays and high control overhead in most proposed systems, which limits the number of processors and the speed of the system.

Distributing work among multiple processors, although for fault tolerance purposes this is not necessarily always the same mechanical part of the system, eliminates the need for a minimum level of central control. isn't it. The idea of a single program that single-handedly determines the complete operation of a computer is replaced by multiple such programs running simultaneously in different processors. The communication channel to the central controller must be sufficient to prevent this from becoming a bottleneck. And common memory is often used in the process of communicating information from one processor to another. A potential difficulty, memory contention, occurs when two or more processors simultaneously request the same portion of information from a common memory.

Some arbitration is then required, requiring either one processor to be left idle or to request this memory again at a later time. This increases complexity, cost and inefficiency. A simple example that occurs in matrix-matrix multiplication is that a single row of a first matrix is required on all processors for simultaneous multiplication with each column of a second matrix. Memory contention for such well-defined operations requires attention in computer design.

Sophistication is required to partition the problem so that the various processors complete their tasks at the appropriate time and provide information for the next stage. Synchronization forces everything to wait on the slowest link, resulting in inefficiency. Parallel algorithms may involve more steps than the serial algorithm used in -a, although they are more efficient for a particular parallel machine. efficiency, speed for multiple processors,
Overhead reduces the efficiency of the algorithm, measured as the speed of the fastest algorithm for a single processor. It is also necessary to compare the stability and accuracy of parallel algorithms with respect to serial algorithms.

The telecommunications industry uses optical fiber extensively, to avoid turning to electronics and to support switching purposes.
We are developing an optical switching device. To overcome mid-band bin limitations and edge connectivity constraints, optics have traditionally been suggested for communicating with VLSI (IEEE Bulletin, Vol. 72, No. 7 (July 1984), 850-86).
6 True, good man
an J, Beast), Leonberger FJ (Leo
nberger F, J,).

Kung S, Y. and Athale R.A.
optical interconnection for the rVLsI system) NJ (
Optical Interconnections f
AGARD-NATO Avionics Panel Expert Meeting on Digital Optical Circuit Technology (Neff J.A.--September 1984) J (IE Electro-op
tictechniques for VLSI In
terconnect)).

Digital optical computers are expected to eventually become dominant, and designs have been proposed to solve the major problem of finite elements ("Optical Technology J (0
(1985)
McAulay's “Deformable Mirror Nearest Adjacent Optical Computer J (Deforma
bleMirror Nearest Neighbo
r 0ptical Computer ), and
Pending U.S. Patent Application No. 777.66
(See No. 0). This design uses deformable mirrors or other spatial light modulators (Opt.
Eng.), Volume 22, No. 6 (December 1983), pp. 675-681.
pe D, R,) and Hornbeck LJ (H
ornbeck L, J.), “Characteristics of deformable mirror devices for optical information processing”
istics of the Deformable
MirrorDevice for 0ptical
(See Information Processing). Acousto-optical machines for matrix algebra operations are currently being investigated. Although these computers are useful for numerical operations, their algorithmic flexibility is limited by the interconnection system used. These are also not intended for signal processing purposes.

Data flow has been widely studied at MIT, SRI and Japan (Arvind
) and Iannucci R.A.
R, ^,)'s ``Two fundamental problems in multiprocessing J
(Two Fundamental l5sues
inMultiprocessing), and
MIT Report, MIT/LC3/TM-241 (1983
Dataflow Solution J (September 2013)
5 solution), as well as I regarding parallel processing.
Hira of the newsletter of the EEE International Conference (August 1984)
ki K,, 5hin+adaT,, N15hid
"Hardware Design of Sigma-1, a Data Flow Computer for Scientific Computing" by A K.
are Design of the Sigma -
1.a Data-flow Computer for
r 5Ccientific Computations
), as well as Jaganat
han R.) and Ashkrot E.A.
shcroft E.

A,)'s ``Easyflow J' (Easyflow
), as well as IEEE International Conference on Parallel Processing 1 (1
Jaganathan R (Jag) in the newsletter of August 984)
anathanR,) and Ashcroft E.
Ashcroft E, A.'s "Easy Flow: Vibrift Model J for Parallel Processing" (A H
ybrid Model for ParallelP
processing ), as well as I on parallel processing.
EI! EEEE International Conference (August 2014) Newsletter by Omandi A. and Tarapholz.
Klapholtz D., “Data-Driven Computation in Process-Based MIMD Machines” (Da.
ta Driven Computations on
Process Ba5ed MIMD Machine
es), as well as Long Ji Ji (Ro
"Pipelining of Homogeneous Data Flow Programs" by ng G, G,
) lomogeneousDataflow Prog
rams)). Allowing operations to begin as soon as the required input is available is generally seen as a possible means of using parallelism, since it avoids the use of a single program counter, as in von Neumann's machine. .

However, many forms of data flow machines have been proposed, and to date, no system has become dominant in computing. (C9R, Vick) and C.V. Ramamoorazi (C, V.).

Rama+noorthy) Oxley D (Oxley D, ), Sober B (5) in Software Technology Handbook (1984)
auber B.), Corniche M.
Software development for data flow machines J (Sh M, )
t for Data-Flow machines
) s and U.S. Pat. No. 4,197.589). Problems associated with interconnection and matching algorithms to processors are not automatically solved by data flow thinking.

(Problems to be Solved by the Invention) The present invention proposes an extremely fast computer by using a large number of basic processing elements to efficiently obtain maximum parallelism, and at the same time optical spatial light modulation. The goal is to maintain extremely high algorithmic flexibility through a high-speed, large-scale, general-purpose interconnection network in the form of a device.

(Means for Solving the Problems) In the present invention, an optical spatial light modulator acts as a crossbar switch, allowing any processing element to be directly connected to any combination of other processing elements. . By using simple processing elements, it is possible to process parts in parallel that cannot be processed in parallel at a coarse level. In embodiments, the processing elements are adders, multipliers, comparators, etc.

(Operation) According to the present invention, problems of parallel processing and algorithm flexibility at the basic processor level are solved. Optical interconnects have advantages over electronic interconnects by reducing the effects of capacitive loading and increasing insensitivity to mutual interference, and also have the performance of hard-wired systems.

(Embodiments) First, the features of a general optical crossbar interconnection type computer will be briefly explained, and then embodiments of the present invention will be explained in detail.

The system is designed to efficiently execute and enable high-speed computation of a wide range of processing algorithms while automatically taking full advantage of low-level parallelism in interconnected computers. Direct mapping of algorithm graphs is possible.

FIG. 1 schematically shows such a computer 30, which is a combinator with a reconfigurable N
The XM crossbar switch 32 is connected by optical fibers 34 to each of the K elementary processors P+ to Pk. The output of each elementary processor goes to one row of crossbar switches 32, and each column of crossbar switches 32 goes to one input terminal of one elementary processor. That is, N is the total number of output terminals and M is less than or equal to the total number of input terminals (this takes into account independent external input terminals as shown in FIG. 1). For example, in a 1024x1024 crossbar switch, assuming 4 connections (2 inputs and 2 outputs) for each, 512 elementary processors are obtained. This basic processor is
For example, multipliers, adders, (multipliers and adders), comparators, buffer registers, programmable elements, and input/output registers for general-purpose signal processing, or logic gates, comparators, pattern matrices for general-purpose symbol processing. It is a mixture of tea, etc. As a result of a test algorithm for a specific application area, a provisional arrangement is easily created which optimizes the mix and number of elements installed in the crossbar switch. The computer 30 also includes a memory 36, a host computer 38, an input/output device 40, a display 42, a programmable address generator 44, and a controller 4.
6. These devices are peripherals to the main crossbar switch/base processor architecture and can be replaced by other types of computer 30.

Basically, the calculations of the computer 30 are as follows. That is, after each parallel processing step, the elementary processor P1
. . . , Pk simultaneously transmit their results to the crossbar.
Via the switch 32, the elementary processor P or Pk
It is output to the input terminal of the selected other one of them, and serves as an input for the next parallel processing step. crossbar
This passage of data through the switches can be either parallel (in this case each data bit requires an output line of the elementary processor and a -row crossbar switch 32) or serial (in this case parallel to serial). converter and multiple clock cycles are required for passing the data) or a combination.

FIG. 2 shows how a group of these computers, each shown as a processing unit, can be connected to form a system that allows the user to take advantage of high levels of parallel processing. That is, the processing units are connected in parallel, and the basic processors in each processing unit are connected in parallel.

The user decides which algorithm he wishes to implement in mathematical notation or in a high-level language such as Eizo.

The software within the host computer constructs the flow graph and begins to prepare the tables that define the interconnect network, the operations that need to be performed by the base processor, and the timing schedules for these operations. These are mapped into hardware. That is, the network is mapped within the crossbar switch 32 setting, and the operations are mapped within the available basic processors P or P. This mapping is such that timing constraints are met while efficiently utilizing available resources. Libraries of configurations for different algorithms can be kept for future use.

The user only needs to feed the data into the computer,
After some delay, the processed data appears on the output. Each elementary processor performs its operation as soon as it receives the required logical or numerical input and automatically passes its output to the crossbar switch for routing to the next required operation. Continuous streams of signal data need to be processed through the same algorithms for signal processing, so pipeline processing through the basic processor-based device makes the most of the available parallelism. Several parallel streams may be used, thereby freeing up resources (if available).

The above system has the following advantages:

Namely: 1. Easy to use. Sophisticated software and high-bandwidth medium crossbar switches free programmers from having to struggle with low-level parallelization of their code. That is, parallel processing is automatically performed for most algorithms.

2. The crossbar switch's software reconfigurability allows completely new cent algorithms to be optimally executed, thus extending the life of field equipment and allowing the same computer to be quickly used from one algorithm to another. You can switch to .

3. Failure tolerance. The ability to quickly reconfigure the crossbar switch allows for bypassing of failed elements.

4. High performance. Because the algorithm graph can be mapped directly onto the computer, the crossbar switch allows full parallelism to be used at the lowest level for a wide range of algorithms.

5. Accuracy. Accuracy depends on the selection of processing elements.

6. Optical crossbar switch. The silicon deformable mirror device provides rapid electronic reconfigurability and also minimizes communication time for algorithms that require interconnections between the various base processors.

7. Optical fiber link. A 3GHz fiber link provides easy links to other boards since fiber exhibits no capacitive loading effects.

8. Programmed boot flow. The data flow is programmed by a crossbar switch, which
Unlike serial phono-Neumann processors that use program counters, they allow parallel streams of data to flow.

There is no need to retrieve information and instructions from remote memory.

Description of the Bean Processing System FIG. 3 shows the organizational structure for the optical crossbar complete signal processor 100. 512 elementary processors P1 to PSI2 are connected to a 768 with serial fiber optic link 104 of 320 Mbit/s or more.
It is connected to the optical crossbar switch 102 of the X768. The first 256 processors P, through P26.
has two input terminals, one of which is switch 1
02, others come from digitized sensors or directly from main memory 106. There are two output terminals that go directly into the optical crossbar switch 102. The processors Pt to P□ act only as multipliers for the basic algorithm considered in the signal processor of the first embodiment.

The second 256 processors P! Sff or P, 1
! is the two input terminals from switch 102, and
1 connected directly to main memory 106 and to switch 102
It has two output terminals. Processor P2. .

ps+□ acts only as an adder for the considered algorithm. Subdividing the basic processor into two banks is advantageous for the considered algorithm, since data can be passed back and forth between them.

Multiple memory paths generate high bandwidth between main memory 106 and processors P, P2Sk. Optical crossbar switch 102 directs data returning to memory 106 into the appropriate bank of processors for future calculations. This is to reduce the complexity of memory management and addressing, and to maintain speed (F
(See FT section). The system or signal processor 100 also includes a host computer 108, an input/output device 110 between the host computer 108 and the memory 106, a display 112, and a programmable address generator 1.
14, a controller 116, and 256 NAND gates 118 for immediate input.

Data transfer is accomplished by resetting switch 102 within a few microseconds, either by frame buffering or by optical setting. Optical setting is different from electronic setting and has been demonstrated for a long time ("Optical Engineering J (Opt.
, Eng. ) 24(1), 107 (1985)
(See D. R. Pape). Generally, only long vectors are moved sequentially between memory and the program, reducing the difficulty of address calculations for such high speed machines. Implementing an algorithm that loops within switch 102 before returning to memory 106 is desirable to reduce performance requirements and time associated with memory transfers (see FFT section below).

FIG. 4 shows the basic processor structure 120.
It is used for P or ps+□ of the signal processor 100. (Texas Instruments (T)
exas Instruments), VH5IC
Play Processor and Carnegie Mellon University (Car
Development of systolic chips at Negie-Mellon University (Kay Bromley)
(K.

Bromley) Akebono, 5PIE Newsletter 495.130
(1984), “Real-time signal processing (Real-time signal processing)”
"TingeSignalProcessing)"
H.T. Kung (H.T. Kung)
and O Menzilcioglu (0, Menzilc
Note that ioglu) uses a programmable crossbar switch in its processor design. ) Data from the main optical crossbar switch 102 representing the two operands for the operation of the processor 120 enters the left side of FIG.
2 and 122' and serial-to-parallel converted by converters 124 and 124'. An operand may also come from main memory, local base processor memory 127, or a digitized sensor. The output of the calculation on the right side is the parallel-to-serial converter 126
and the optical crossbar provided to the laser driver 128.
Return to switch 102. A second output is provided to the systolic configuration, where the input data is passed through the base processor. The above output is also the main memory 10
In some cases, it may pass through 6. Arithmetic operations are performed by ALU/multiplier 1
25, which includes a programmable 8x8 interconnect 12 that couples the input/output and ALU/multipliers.
3 is included. Thus, for example, interconnect 123
converter 124' to converter 126'
and input to converter 124 without change.
and 124' to the ALU/multiplier 125 for multiplication, and finally, the multiplication product is sent to the output converter 12.
Pass to 6. (This is, in effect, a provision for the first bank of basic processors in the systolic filtering example below.) Figure 3 shows that the top half processors are connected differently than the bottom half processors. This indicates that there is a The normal operation of the processor is under the control of the local program, and the start of a computation or move cycle is determined by the mask synchronization signal.

Multi-gigaflop performance requires the use of commercially available 100 nanosecond multiplier and adder chips.

FIG. 5A shows a diagram for a 4x4 crossbar switch 102. Each intersection has a directional switch that couples the horizontal input line with the vertical output line. Black circles indicate closed switches. One output line receives information from one input line, but one input line can broadcast to several output lines. FIG. 5B shows the spatial light modulator 13
5A, the crossbar switch 102 is diagrammatically shown with a crossbar switch 102 having a crossbar switch 102 with a dot indicating a transparent area consistent with the settings of FIG. 5A. An optical lens system (not shown) is used to spread the light from the input source (LEDI-4) horizontally without spreading the light vertically. The light passing through the spatial light modulator 130 is directed onto the receiving diodes (detectors 1 to 4) by a lens system (not shown) that focuses the light vertically without spreading it horizontally.

FIG. 6 shows a switch 102 with a deformable mirror device (DMD) as a spatial light modulator 130. The DMD does not act as a transparent modulator, but as a variable intensity reflector, so the right side of this modulator is folded back. A beam splitter 132 is used to separate the returning light from the incident light. Schlieren optics 134 are used to block reflections from the areas between the mirror deflection pixels of DMD 130. 5 with modulation capability up to 3 GHz
12 laser diodes 136 (rToday's Physics)
Physics Today) 38 (5),
32 (1985) Y.

(see 5uesatsu) acts as a light source, and 512 P
IN diode 138 acts as a photoreceptor (IEE
Liu W. Gutsman (J, W. Gooda +
an) F.J. Leonberger (F.J.
, Leonberger), Nis Y Kang (S
, Y. Kung) and R.A. Athale, and AGARD Proceedings 362.17 (1985), B.L. Dorp (
B, L, Dove), eds., Digital Optical Circuit Technology J (Digital Optical Circuit Technology J)
Liu A.
Neff (see J, ^, Neff). Optical devices not shown in FIG. 5B are shown in FIG. 6. That is, the cylindrical optical device 140 horizontally spreads the light from the input source 136;
A cylindrical optical device 142 directs light vertically onto the receiving diode 138. Optics 136 and photoreceptor 138 can be integrated directly onto the electronic chip.

Membrane and cantilever deformable mirror device (DMD) (I
EEEii Proceedings ED-22(9), (1975) R.N. Thomas) has been developed. Texas Instruments Membrane D
The results of imaging and spectroscopic analysis performed with MD have been published ("Optical Engineering J 22 (6), 675 (
Reference D. R. Peso and L. J. Hornbeck (1983)). Film light modulators consist of an X-Y array of deformable mirror elements that are addressable by an underlying array of MOS transistors. 7A is a perspective view of four adjacent mirror elements, and FIG. 7B is a schematic representation of the array. a reflective conductive film 170 covers the surface of the array;
It is a mirror. The line addressing organization of the DMD is shown in FIG. 7B. That is, data is provided to a series-to-parallel converter 171, which is connected to the drain line 172 of the MoS transistor. The drain line 172 is charged (the kth line 172 is charged to the potential φ61.), and the decoder 174 connected to the gate 176 selects the mth gate and turns it on.

Next, the mth gate line 17? The floating source 178 of the Mo3 transistor is charged to the potential of the corresponding drain 172 (the mth gate line is φ3).

). The gate is then turned off and mirror 170 is held at a fixed potential of vM. Therefore, ■9-φ1. An electrostatic force proportional to is applied to the (k, m)th mirror element to deflect it downward toward floating source 178. The mechanical response time of the mirror element, and thus the line settling time, is a few μs. mth gate line 17
Once the floating source 178 in 7 is set, the next line's data is then provided into the drain line 172 and the next gate line 177 is selected by the decoder 174. The cantilever device is similar except that above each floating source a small flap is hinged at one corner to form a conductive mirror. As in the film optical modulator, when the transistor is turned on, the floating source is charged and the corresponding flap is bent downwardly at its hinge toward the charged floating source. The deflection of the membrane or flap is a nonlinear function of the applied voltage and approximates the shape shown in Figure 7C. Above a critical "failure voltage" the membrane or flap is unstable against buckling towards the charged capacitor plate. The mirror element size for the membrane and cantilever devices described above is on the order of 30 microns square.

``Probooming'' The user derives an approximate formula to calculate the target function and selects an algorithm to execute this formula.
``Computer Architecture + J for Digital Signal Processing'' by Allen J ()
Computer Architecture for
(See Digital Processing) is configured for this algorithm in such a way as to present maximum parallelism. Represent operations as nodes and connections as edges or arcs. The above directed graph is mapped onto an optical crossbar switch system. That is, the edges are mapped into crossbar settings and the nodes are mapped into available base processors in a manner that satisfies timing constraints while efficiently utilizing available resources. Systolic filtering, FFT to implement folding garbage
.

and the doubling algorithm are then mapped to processor 100. Present the parallel conjugate gradient algorithm graph somewhere (A. D. McAulay, 2nd SIAM Conference on Parallel Processing for Scientific Computing (November 1985) [Optical Crossbar Mutual Conjugate gradient J for connected multiprocessors
(Conjugate Gradients on Op
tical Crossbar Interconne
cted Multiprocessor)). The main objective is to automatically construct and duplicate directed graphs with maximum concurrency for algorithms.
Ackerman (W, B.

Ackerman) “Computer J15(2), 1
5 (1982)), and the next step is to develop software for efficiently mapping this onto a processor. This includes preparing the tables that determine the interconnection network, the operations that need to be performed by the elementary processor, and the timing schedule for these operations.

The user supplies a stream of data to the processor, and the results appear at the output terminal each cycle as the pipeline fills. Each basic processor P or ps
After receiving all necessary logic or numerical inputs, t□ performs its operation on the next synchronization pulse and sends the output to crossbar switch 102? Automatically pass through and route to the next required operation.

Algorithms Systolic filtering, convolution, correlation, and Fourier transform are basic signal processing algorithms. The linear filter is as follows.

Here, a, , (k=1...k) are filter coefficients, bn (n=1...N) are data, and * mark is a convolution operator.

The cross-correlation between vectors a and b can be written as follows.

Comparing equations (1) and (2), it can be seen that the convolution and correlation can be computed on the same processor by reversing the order of one input. Systolic, FFT, and doubling methods for performing such operations on an optical crossbar signal processor will now be described. However, only 16 basic processors are illustrated for clarity.

FIG. 8A shows a directed graph for executing filter equation (1) in systolic mode. The filter coefficients ak are stored within the multiplier processor P, through P. Data is serially entered into processor P, with zeros inserted between data values. The above zero is 2
It allows cyclic operations, where the computation is performed in one cycle and the data is moved to the next processor in another cycle. All processors perform corresponding computations and move operations together when the pipeline is full. Thus, in each transfer cycle, a new value of output c7 comes out at the upper right processor P. For example, term c4. =a, b, +azb2 +
a3bt is generated as follows. That is, the first transfer cycle puts bl into processor P, and all other elementary processors are filled with zeros. The first computation cycle is irrelevant for C4 (ie, the product a,b, computed in processor P, is for term c). A second transfer cycle transfers bl to processor P2 and places O into processor P1. All other transfers (ie, transfers from processor P, to P) are irrelevant. The second calculation cycle is also irrelevant. A third transfer cycle transfers b, into the processor pH, transfers 0 into the processor pH, and bt
into the processor pH. The third calculation cycle produces the product a, b. The fourth transfer cycle moves a, b, from processor P3 to P, and bt from processor Pt to P.
2 and puts 0 into processor P. Fourth
The calculation cycle of brings the product a, b into the processor pH,
A simple sum of O and a3b is then created in the processor pH. A fifth transfer cycle transfers a, b to processor P,
to PI(1, a2b, from processor P2 to P,.

and place it in the processor pH. The fifth calculation cycle calculates the sum a=b, +a2b2 by the processor P. and create a product alb3 in processor P1. A sixth transfer cycle transfers aab++azb2 from processor pto to P, and a,b3 from processor P1 to P. The sixth calculation cycle creates the sum axbt + azb2 + a+b3. This sum is C4 in the processor pH. Then, the seventh movement cycle outputs 04.

FIG. 8B illustrates the implementation of the directed flow graph of FIG. 8A on the computer of FIG. 3. Input is provided to processor P. The top output of processor PI is routed back to the input terminal of processor P2 via a top closed switch (designated A) in the upper left quadrant of crossbar switch 102. The second output from processor P is the input data value b7
, which is passed to the top input terminal of adder P, via a switch setting (designated B) on the upper right quadrant of crossbar switch 102. The other input of the adder P is the crossbar switch 10.
It comes from the adder PIO via a se/ning (denoted by the symbol C) in the lower cloth quarter area of 2. The output comes from processor P. For systolic arrays, when the pipeline is full, an output is available for each computation-transfer clock cycle.

High Flux Fourier Transform (FFT) The FFT is often advantageously used to correlate two equal length vectors, for example in matching input data to a template for recognition. Compute the Fourier transform of the input data and multiply that value by the stored template transform coefficients. The overall calculation takes less time than convolution. That is, convolution of two N-length vectors requires approximately O(N'') multiplication/addition calculations, while convolution by FFT using padding of 2 requires approximately O(2N+4N logz(2N)) operations. FFT is also important when determining spectral information, for example when recognizing ships from propeller motion in noise data.

The Fourier transform of the finite sequence X is another finite sequence X given by the following equation.

FIG. 9A shows the graph for a temporal 8-point decimation FFT, and FIG. 9B shows the bit inversion for the start of this configuration.

FIG. 9C shows a fixed configuration stage used in each iteration by sending the right-hand output back to the input terminal log, N times for an FFT of length N (e.g., The 8-point FFT takes logz8 = 3 iterations, as shown in Figure 9A). formula(
The weight W corresponding to the appropriate index term in 3) is also the 9th
As shown in Figure A, it is necessary to make a displacement in each iteration. These weights are stored in base processor local memory 127 or main memory 106.

Figure 10 shows F on the 24x24 crossbar switch 102.
FT implementation is shown. FFT
Inputs are provided to processors P1 through P, which pass this data to crossbar switch 102. (i.e., raised to the power of 1). The upper left quadrant of the switch converts the bits into the bit-reversed sequence required in FIG. 9B and returns this to the processors Pl-P. First set weight W
is used for the first loop of the FFT stage (Figure 9C). The crossbar switch 102 is then reset to turn off the upper left quadrant and turn on the upper and lower quadrants for a repeating loop. Therefore, the above data is transformed into a fixed configuration FFT.
Adder processors P, through PI3, through the upper cloth quarters of crossbar switch 102, which execute the graph.
pass to. The exit quarter section of the crossbar switch 102 is used to return the data to the processors P, P, for the next loop of the FFT. After the loop of logzH, its output is sent to an adder processor P, or P,
. taken from.

Complex multiplication and complex addition are performed within each loop of FFT.
They are carried out one after another. However, complex multiplications take significantly longer than complex additions. Even if two FFTs are incremented, high efficiency cannot be obtained because of the discrepancy in the computation times for complex multiplication and addition. This discrepancy can be overcome by separating the real and imaginary parts.

Figures 11A and 11B show a 4-point FFT flow graph that separates the real and imaginary parts;
It requires 1 multiplier, 12 adders, and a 36x36 crossbar switch. The calculation proceeds as follows.

That is, the first cycle rearranges the order of the sequence to be converted (FIG. 11A).

The crossbar switch is then reset for repeat loops each having one multiplication cycle and two addition cycles containing similar computation times.

Therefore, three FFTs can be interleaved and computed so that a total of three cycles are computed simultaneously for different transforms. Table 1 shows the crossbar switch settings for this flow.

FIG. 12A shows a graph for correlating many vectors with respect to the template vector b1 in the time domain, ie, equation (2), by recursive doubling. The above vectors can be thought of as rows of matrix A in matrix-vector multiplication. While one vector is being multiplied in processors P, through P, the results of a previous multiplication are being added in processors P, through ptz, and the results of a second preceding multiplication are being added in processor P13. or PIJ, and the result of the third preceding multiplication is added to the processor PI
It is being added within S. Processor P0 is not used, and the value of the output vector for the above matrix-vector multiplication is obtained in each computational transfer clock cycle. FIG. 12B shows a computer implementation of FIG. In this case 16
An X24 switch is suitable. The latency for this implementation is log,N, as opposed to N for systolic array mode. Parallel inputs are required here, and multiple vectors must be correlated to fill the pipeline. Problems arising from taking a Fourier transform are also avoided.

Autoregressive Modeling for Spectrum Autoregressive modeling is chosen because it is widely used in audio, underwater acoustics, sonar, radar, and seismic processing.

Autoregressive modeling (AR) generally includes optimal least squares or Wiener filtering, linear prediction (LP),
and the maximum entropy method (MEM).

The purpose of modeling is to represent the time series by a small number of autoregressive parameters (full ball model), which can reproduce the time series to within least squares accuracy by passing white noise through the model. It is.

Therefore, passing the time series through the inverse filter of the model removes the information for the time series and leaves behind white noise. Therefore, the AR parameters include information for calculating the time series vector, ie, its color. The above AR parameters are also linear predictive coefficients (LPC)
) can also be considered. That is, F with these coefficients
This is because the IR or MR filter predicts the next value in a time series from a plurality of past values. Subtracting the predicted value from the actual value gives white noise, similar to applying an inverse AR filter. The mth order LPGam (k=1...m) makes it possible to predict the value of the time series at time j from past values.

That is, Then, it is calculated to minimize the following value.

Σ= 1xj−Xj l ” ' (5)
Three uses will be briefly described. In geography, the reflected signals from the earth are considered to be random.

The response measured at the surface is a convolution of the source wavelet and a random ground sequence.

The influence of the source wavelet is removed from the sensor data by predictive deconvolution. i.e., removing colored information in the spectrum (I EEE International Conference on Acoustics, Speech and Signal Processing J (March 1985), Macaulay, ``Predictive Deconvolution of Seismic Array Data'') Deco
nvolution of Se15m1c Arra
yData for Inversion).

In the second application, a 200 sample segment of audio is represented by 16 linear prediction coefficients (AR parameters). That is, this multiball is suitable for modeling the spectrum and for recognizing this segment. In this case, the compression of the data from 200 to 16 acts as a feature extraction that greatly speeds up the calculations in subsequent stages.

The third example is the AR parameter all(k=
1...m) and obtaining the energy V.

The assumption that the data is zero or repeating outside the measurement region, made in the FFT, is avoided when calculating spectra from the AR model.

The aforementioned methods such as AR, LP and MEM lead to the next step to determine the AR parameters or LPG. Estimate the autocorrelation function of the following equation for the time series.

τ=0...m(7) AR parameter or linear prediction coefficient ak(
Find k=l...m).

Ra = b (8) where R is the Toeplitz autocorrelation matrix formed from Rxx. This is commonly referred to as Durbin.
in) or on a sequential processor using the Levinson algorithm. However, for parallel machines, Schur
is generally considered to be more convenient (IEEE Proceedings ``Acoustics, Speech and Signal Processing J
ASSP-31 (1983) Nis Kang (S, K
ung) and Y.T.

Hu)'s ``Highly Concurrent Algorithms and Pipelined Architectures for Solving Toeblitz Systems'' J (
A Old Ghly Concurrent Algor
ithmand Pipelined Archit
ecture for SolvingToplit
z Systems ), the l matrix R is decomposed into a product of lower and higher triangular matrices as follows.

By substituting R−U”U (9) into equation (8), it can be solved in two steps. Namely,
Find g from the following formula.

b=U”g (10) and
Find a from the following formula.

g = U a (11) 1st
The autocorrelation coefficient in equation (7) can be calculated using the tree correlations in Figures 2a and 12B. In this case, assuming we have a sufficient number of processors, we set the data into a multiplier and then feed a copy of this data from the top delayed by an amount equal to the maximum desired delay. At each step, the delay is reduced by one and the correlation is performed, thus ensuring that the delayed data stream is accurately aligned with the original data.

As it is calculated, the self-alignment coefficients R,, R,...RN are fed into the elementary processors Q, SO2...QtN in the systolic array as shown in FIG. This array uses Joule's algorithm to calculate the AR parameters or LPG for the time series and invokes a set of base processors in computer 100 that are different from those used for the calculation of the autocorrelation coefficients. (
It goes without saying that rather than feeding the autocorrelation coefficients to the elementary processor as they are computed, the autocorrelation coefficients can be stored after being computed, and the same elementary processor in the systolic array can be used. The crossbar switch 102 may be reset as shown in FIG. ) Compute the upper triangular matrix U, which is then used in the lower systolic array to compute g and a. While calculating g and a, the top two row processors can be started for calculating the AR parameters for the next time series. basic processor ql
, (h...(Izs is interconnected with up to 4 inputs and up to 3 outputs.

It is more complex than that shown in FIG. 3 and requires a larger crossbar switch as shown in FIG.

The computer 100 (or more generally, the computer 30) as a No. 48 processor can provide multi-gigaflop performance, and the cantilevered spatial light modulator results in a large, high-speed crossbar switch. However, the size, speed, and cost of this crossbar switch make conventional semiconductor technology unlikely to be compatible. In fact, the algorithm is reduced to a maximally parallel directed graph, and this graph is mapped to a signal processor. Use programmed boot flow to minimize overhead during execution. 4 illustrates implementations of filtering, convolution, correlation, fast Fourier transform, and matrix-vector multiplication. Because the crossbar switch is fully reconfigurable, fast and efficient implementation of complex algorithms is possible, and new algorithms can be automatically mapped to computer 100 or computer 30.

The optical crossbar-reading parallel elementary processor can also form a symbolic computer or a mixed symbolic numerical computer. For symbolic calculations, the basic processor includes logic gates, comparators, etc. That is, in FIG. 4, ALU/multiplier 125 is replaced or supplemented with logic gates, pattern matching, or other symbolic processing functions. It comprises a second embodiment computer, which will be described in connection with the following applications.

艮１１゛ Expert system A direct form of expert system that can be widely applied is
A system in which information is contained within procedures in the form of "if then" rules. There are many real-time applications where rapid inference is required and for which the processor proposed here is suitable. Applications include audio, vision, industrial equipment, robotics, and weapons systems. In a forward chaining rule-based system, one makes -sets of observations and assumes a probability of accuracy for each. This reasoning agency is
Quickly identify conditions, surroundings, or threats and direct appropriate action. In backward chaining rule-based systems, a goal is assumed and then subdivided into requirements for meeting this goal. These are further subdivided.

It all started with computer languages that worked in this way. Forward and backward chains will be explained later. In either format, parallel processing is required to obtain rapid response. - It is not economical to hardwire a system containing a set of interconnected logic rules and probabilities.

That is, the rules may change or need to be changed for new conditions.

The speed and reconfigurability of the optical crossbar switch proposed here is required. The simple system considered here does not invoke propositional computations and address the more complex first-order predicate computations required in more complex applications.

Figure 14 shows the implementation of i ゛.
Figure 3 shows a directed flow graph for identifying 7 animals based on 20 observed features. This example and its explanation can be found in Winston's ``Artificial Intelligence'' (Addison-Wesley).
(1984). The explanation can be simplified by assuming that each observation is true or false with no assigned probability. The basic processors (marked with symbols P1 to P9°) are:
An AND gate is indicated by a circle, an OR gate is indicated by a circle with a black dot, and an inversion gate is indicated by a circle with rlJ. The input is "true" if the input corresponding to this animal is true.
It is. To illustrate the characteristics of the if-then rule of a rule-compliant system, for example, in processor P, ``If an animal is a mammal and eats meat, then it is a carnivore.''
, the OR gate in processor pz+ indicates, in another way of reasoning, that it is a carnivore. That is, it is inferred that ``If this animal is a mammal, and this animal has pointed teeth, and this animal has forward-facing eyes, then it is a carnivore.''

In the case in question, observations have a probability of accuracy associated with them. Assuming independence, the joint probability of two events is the product of these two probabilities. Therefore,
Processors indicated by hollow circles and processors without black dots are 2.
Multiply by the probability of arrival. These processors will be referred to later as type A.

An output of zero corresponds to a logical value and is obtained if any input probability is zero. The dotted circle processor is what we will later call type B and determines the maximum value of the arrival probability. Other formulas are given in Winston's paper. A type C processor subtracts the probability of arrival from one. These total three types of processors are also:
It has a probability mapping function that changes the output. This function maps calculated input probabilities to output probabilities between 0 and 1.

The flow graph of FIG. 14 can be implemented directly on a systolic system such as the one shown in FIG. 1, in which the first 12 processors have input connections; The last eight processors have output connections. Only 40 processors are required for the simple example shown here. The processor is programmed to work as type A, B or C as shown in Table 2. The observation input is the first 20 processors P
, or P2°. Probabilities are obtained at the output of the last seven processors, the highest of which indicates the identified animal. The confidence factor clearly relates to the magnitude of the probability and the amount by which this exceeds the magnitude of the probability for other animals. Table 2 indicates which of the crossbar switch elements must be activated to provide the interconnections between the rules shown in the flow graph of FIG.

/J-,l Implementation Many applications are better suited to backward chaining than to forward chaining. That is, the user is interested in solving a particular hypothesis or goal. Obtaining data can be difficult, and users do not want to expend effort obtaining unnecessary observation data. The real question to ask the expert system shown in Figure 14 is, "Is this animal data?" This means reading the flow graph of FIG. 14 from right to left. In the processor P34, the animal has a tan color;
And if it has a dark spot on processor P2□, and this animal is a carnivore, it will meet the target. The advantage of backward chaining is that it dictates which features to look at and there is no time wasted on obtaining other off-target data.

Implementation on an optical crossbar-interconnected processor requires backward 4 extraction of trees leading to a hypothetical target (Figure 15). The processors are assigned numbers Q1 to Q as shown. All known data is sent into the processor as real information. It is advisable to set the crossbar switch for multiple trees containing different sets of base processors, assuming that further assumptions are forthcoming. A signal enters processor Q. Reverse direction A
In each circle representing an ND gate (Ql is related to Pco in FIG. 14), the signal is transmitted again in the output direction. In the dotted circle representing a backward OR gate, the above signal is the number of the above OR gate and the above OR gate.
The gate technique is tagged. If all of the outputs are already marked true on either processor, there is no need to proceed further with the trick. Alternatively, the processor may output a question to the user such as "Is the animal a carnivore?" Eventually, the signal is filtered to a base that dictates what information is needed to ascertain whether the animal is data. Output indicators are also tagged so that the machine can interpret the output to provide alternative combinations that the user must be satisfied with to confirm that the animal is data. .

``It is possible to simultaneously perform symbolic processing of voices and logical reasoning, and to combine them via a crossbar switch. This allows the signal processing output to be used directly for reasoning.'' and has the advantage that the inference output can initiate the specific computations needed to complete the inference step.

A practical way to calculate these is to allocate the upper section of the processor to inference and the lower section of the processor to signal processing. The crossbar switch is divided into four corresponding segments, with the upper segment used for signal processing and the lower fabric segment used for symbolic calculation. The other two segments allow communication at any stage between symbolic and numerical calculations. That is, in the third embodiment, a set of basic processors having arithmetic functions (ALU/multiplication at 25 in FIG.
), and another set of basic processors with symbolic functions (replacing the ALU/multiplier 125 in FIG. 4 with symbolic functions such as logic gates).

Of course, a more expansive approach would be to have both arithmetic and symbolic functionality in all basic processors.

Geographical exploration requires faster symbolic and numerical processing to enable real-time processing and interpretation. Cleaning up data and removing source signatures using symbolic processing (A. Macaulay's ``Inversion of Seismic Array Data'' in IEEE International Conference on Acoustics, Speech and Symbolic Recording, May 1985). Predictive Deconvolution J
nvolution of Se15m1cArray
(See Data for Inversion).

Then \Modeling and Inversion (50 “Geography J77-8
7 (1985), “Prestack Inversion J by Planar Layer Point Source Modeling”.
version with Plane Layer
Direct estimation of earth parameters is performed using the following method: The selection of parameters and the derivation of equations to control these calculations require symbolic calculations. A rule-based expert system is required for interpretation and must communicate with the signal processing so that specific assumptions made in backward chaining mode are validated by specific reprocessing of the selected data.

The System Signal/Numerical Speech Recognizer demonstrates the benefits of performing simultaneous numerical and symbolic calculations.

FIG. 16 is a block diagram for speech lexical analysis by the embedded parser. Each block is subdivided into three parts. That is, the upper part contains a description of the functions performed, the middle part is the algorithmic method used, and the lower part is the architectural implementation configured by crossbar switch 102. The difficult problem of speech recognition is greatly simplified to illustrate the principles involved. First, assume that audio data is input and sampled continuously. Each stream of sampled data contains 20
Partition into 20 ms frames with 0 samples. This embodiment operates on a continuous stream of frames, unlike most systems that operate in batch mode on batches of frames. This avoids the complexity associated with batch interface operations.

In FIG. 16, the first two functional blocks 202 and 204 use the AR modeling method described above to generate data for a single frame from 200 samples to 16
linear predictive coefficients (LPGs). A parallel implementation using optical crossbar-interconnected basic processors was provided earlier in FIG. in general,
Further stages are used to refine the values representing speech based on heuristics. In fact, if there are N data samples and M LPG coefficients per frame, the correlation will only be N/M times longer than the next stage. Therefore, in order to use the processor efficiently, an N/M wide tree can be used repeatedly M times.

After reducing the 20 ms frame to 16 LPGs, the crossbar switch is reset for dynamic time warping. The above warping is performed in function block 2 of Fig. 16.
06, it is used to identify or classify incoming words from the members of the dictionary by correlating the LPG for the incoming signal against the dictionary reference LPG template.

As shown in function block 206, the crossbar switch is again reset to configure the computer as a reasoning machine. Simple rules are used within a rule-based system to make decisions regarding the end of one word and the beginning of a new word.

Symbolic parsing in the form of a situational action weight-and-see rule-based system uses the rules of language grammar to predict the possible parts of speech for the next word, and thus must be taken into account. It reduces the number of words in the dictionary and also helps resolve ambiguities in recognition. This is the function block 2 in FIG.
This is done on this computer by resetting the crossbar switch one more time, as shown at 10.

Parallel dynamic time warping and symbolic parsing will now be described along with their implementation using optical crossbar switches. The crossbar switch is reset three times during each frame. The first setting is
Corresponding to computing the LPG and making logical inferences to the rule-compliant parser, the second setting is
The third setting is for determining the cumulative cost function for each reference term during dynamic time toping.
It is used to determine the end of a word and classify it.

As shown in Figure 16, the LPG for frames of incoming data of unknown length must be correlated with each frame for all possible words in the dictionary of LPG templates. Figure 17A shows
−−−−− i −1, i, i+1, −−−−−−−
The input data LPG frame marked with , and the reference word LPC frame in the y direction are shown. Divide the standard template dictionary into subdictionaries according to parts of speech. Words that can occur as more than one part of speech are included in separate subdictionaries.

Using a symbolic parser to predict parts of speech that cannot be followed due to grammar rules, these subdictionaries containing parts of speech that do not match the zero grammar do not need to be correlated;
This saves time in the local distance and dynamic time warp stages.

A typical local distance measurement value is as follows.

and where L is the number of linear prediction coefficients and i is L P
Ci, is the input frame number with -------iL, and r is the reference template number with LPCr, -------rL.

The local distance diar is computed simultaneously along the wavefront shown in Figure 17A as each new input frame arrives. The point (i-r) in FIG. 17A is the corresponding d i, r
represents. In order to perform recognition, the degree of correlation between the incoming frame and the reference frame must be obtained. Expansion or contraction by a factor of 2 is allowed in each input frame to account for variations in speaker speed relative to the reference. This is done by computing an accumulated distance cost function along the wavefront as new input frames arrive. The cost function accumulates running sums of local distances.

FIG. 17B shows that the running total is selected from three possibilities considering shrinkage, stretch, or neither.

This is expressed by the following formula.

si, IP = dt, r”1ln(St-1+ r
-z +d,, P-1'Si-In r-1'5i-
2. r-1+6-11,) The cumulative cost function at the top of the column in Figure 17A is used to determine whether the word is blank and whether a match is obtained. Also, the word in the dictionary with the best match is identified.

FIG. 18 illustrates a method for calculating local distance and dynamic time warping using optical crossbar interconnected parallel processors. The 16 linear prediction coefficients for the next input frame are -16 sets of 10 basic processors P, , P, -------p, . (along the top of Fig. 18) for the lines L+, Lz - - L
It is loaded in parallel on ls-LI& (retired section in Figure 18) and remains there until all reference words have been computed. The reference words are 10 frames for short words (0,2 seconds), 20 frames for long words, or 30 frames (0,6 seconds) for very long words.
is stored as. As a result, 10 frames of short words are connected to input lines R1, R2 --- as shown in FIG.
-1-R+sq, R+h. , and long words are split into two or three parts.

For simplicity, only reference words with a length of 10 frames are considered. 10 sets of 16 LPGs for the above reference words (
A linear predictive coefficient) is connected to the IQH's basic processors P1-P via high-speed memory lines. and further the trees T+, Tz of other basic processors
--T+s is subtraction and addition of equation (12) or equation (1
3) Multiplication and addition are performed. The reference frame is oscillated relative to the word to allow accumulation across all frames. That is, the 16 LPGs for the jth frame of a word are
1 for the (j-1)th frame of the word before entering
6 LPGs are processors PI&j-1s or Poj
, which allows the local distance between the input frame and the (j-1)th frame of the word (plus the accumulation of earlier frame local distances from said input frame) to be
For the accumulation of the local distance between the input frame and the jth frame of the word in adders A, B, and C, it can be used as part of a dynamic time warp computation.

The outputs of trees T1 through TIO represent the sequence of time-varying local distances in FIG. 17A.

Following this, in a pipeline, are local distance values for all reference words. This pattern is then repeated for the next input frame. A dynamic time warping program must be applied to correlate with each reference word separately, so that in subsequent descriptions the delay must be sufficient to match the time to the next input frame and the same reference word. No. For simplicity of explanation, assume that only one reference word is used and that the tree's swinging pipeline output is the sequence of FIG. 17 for a single reference word. The cumulative cost function for the three paths in FIG. 17B is calculated in the flow graph via equation (14). Path 2 is calculated by adding the local distance to the accumulated result in the previous time frame with one less reference frame. Path 1 is obtained by adding the accumulated value for path 2 calculated in the previous time frame to the current local distance. Compute path 3 by adding the accumulated path for the previous frame to the delayed current local distance. To enable comparison of the three paths above, delays are added in paths 1 and 2. The accumulated cost at the far right represents the accumulated cost at the top of the column in FIG. 17A and is used to determine word endings and word identification. As mentioned above, for each input frame, a set of values for every reference word or part of a reference word flows out sequentially at the right end.

FIG. 19 shows a method for detecting the end of a word by logical reasoning. The stream from FIG. 18 representing the accumulated cost for correlation for one input frame against frames for all references is sent into the top of the processor. The result for a 0 segment word is as shown for word 1. will be added to. The cost function goes through a set of logical operations to determine whether the word ends at this point.

The feasibility rule is shown in Figure 19, and the energy is already
is below the threshold for a short time, the accumulated cost is below the threshold, the cost is less than the cost at the neighboring points, and more than the number of frames at the end of the preceding word After that, it has already passed. All tests that do not match the word result in a zero output. Comparisons between words are then made. If a word passes a minimum number of tests compared to other words, this word is filtered to the output along with its value and identification tag. A non-zero tag indicates the end of a word, and this tag specifies this word. All cumulative cost functions in the dynamic time warp computation are set to zero, and after the end of one word is detected, we start searching for a new word. The recognized word and possible parts of its speech are sent to the parser.

With over 10,000 words having many similar words, it is difficult to obtain good performance without utilizing grammar rules to help discriminate between ambiguities. Using a situational action parser like the one mentioned above, phrases can be assembled and recognized as new words,
Therefore, it is possible to predict unacceptable parts of speech in subsequent words. This makes it possible to reduce the number of dictionary words with which inputs have to be correlated during dynamic time toping. A large number of terms can then be accommodated or time is freed up for other calculations. The above parser must operate fast to be useful. Parsing is accomplished by toggling a crossbar switch to activate pattern matching elements within the base processor. The parser considered here is the weight-and-see parser (P. Winston's "
Artificial Intelligence” 2nd edition (Addison Wesley, 1984)
), this parser consists of a set of rules and actions to take when a rule is activated.

Approximately 500 rules can be executed on a system such as the one shown in FIG.

I will explain this using a set of 13 rules described in Winston's book.

FIG. 20 shows the analysis of a sentence and the generation of an operand analysis tree. As described in Winston Winston's book, trees are generated from sentences using -set rules. Still other rules are needed to predict unacceptable parts of speech. Furthermore, for words that can have two or more parts of speech, all parts of speech must be considered. If more than one part of speech gives satisfaction, it has a double trace, or
Alternatively, it may be necessary to remember the state of the processor for backtracking in case operand parsing fails later.

Table 3 shows the parsing order. Typically three buffers are required, but for this example only two are needed.
There are only two buffers, B+ and B2. The three stack nodes are shown as Kg and Kg. The buffer and stack nodes described above are multiple registers, and the contents of all registers are typically moved together. Words enter from the left and rules are operated according to the contents of the buffer and the topmost stack node KI. The action taken as a result of the rule being activated is on the stack, for items in buffer B.

and right-shift the word in the buffer to fill the available space in buffer B1,
The second action removes the subtree, for example the verb phrase (V
P) is to create a new node within one in the stack to start. A node in the stack is moved aside to make room for the new node.

The final action used in this example is stack K.

Move the node from buffer B to buffer B, and shift the nodes in the stack to the left to fill the stack.

Table 3 shows the parsing of sentences in a 12-step order according to Winston. At the beginning, suppose a phrase (S) in the stack KI, and then set the part of speech (Figure 20) for this sentence, starting from the first word in the sentence,
Enter into buffers B1 and B2 from the left. Since 1 on the stack contains a sentence node, and there is a noun phrase (NP) in buffer B, the sentence rule on the right side works.

The action taken is to move NP onto the stack, and create a task for it to S. At the same time, the incoming word is shifted to the right to refill buffer B. As shown on the right, we activate the other sentence rules in step 2, which moves the stack down from 1 to 2, and places a new verb phrase node on the stack,
Set up inside. At this stage, the NP subtree of operand analysis is complete and the vPPP subtree is starting (Figure 20). Steps 4 and 5 combine verbs and nouns with the above subtrees.

Step 6 is to add the already generated subtree to the stack.
and start the prepositional phrase subtree while keeping it within 2. Steps 7 and 8 establish the PP subtree. The rules in step 9 enable concatenation of PPs under VP, and steps lO and 12 concatenate VPs under statement S to provide a complete operand parse tree.

FIG. 21 shows a flow graph that can be mapped to an optical crossbar-interconnected basic processor computer similar to that in FIG. 3 for the examples of Table 3 and FIG.

13 rules S+ to S4, vp, to VP6, P
P, through PP3 have input terminals from the buffer register and the upper stack register. At each clock cycle, every rule attempts to match its stored pattern with the pattern at its input terminal. In this example, two matches are required to activate any rule, except for rule VP4, which requires three matches.

It is also assumed that the rules are not ordered. Ordered rules can be accommodated by rearranging the interconnects, as in FIG. 14. Eight of the above rules, when activated, act on an output in the dismount section, which causes the buffers, including transfer buffer B1, to begin task generation for the bottom of the registers in the stack. Rules S3 and V P 4, when activated, shift the stack register to the right and cause a new phrase node to occur and be placed on the stack. Rules VP and PP
When S is activated, it shifts the stack register containing the stack into buffer B.

Activation of rule S4 indicates completion of parsing and reading of the tree.

Various modifications can be made to the computer of the invention while retaining the characteristic of optical dynamic reconfigurability of the parallel basic processor interconnections. For example, the number and type of processors can be varied by mixing types of processors, and it is not necessary to use all of the processors to obtain dynamic changes in algorithms that require different numbers of processors. It is also possible to hardwire some subset of the elementary processors to reduce the number of elementary processors interconnected by the crossbar switch, and in this way
The time required to reset the switch can be reduced. Of course, the basic processors can be configured in a pipelined manner with crossbar switches, and the reconfigurability of the crossbar switches allows time-sharing for different algorithms on the same computer. In addition, the spatial light modulator is an LCD
It may be a transmission type such as , or it may be a play of a smaller modulator. Modulators based on quantum well devices appear to provide nanosecond switching times (RP-I-N diode structures such as T. Wood et al. High-speed optical modulation J (High -5peed 0p
tical Modulation with GaA
s/GaA I AsQuantuai Well i
na p-1-n Diode 5structure
)reference).

For example, the fast Fourier transform of the embodiment by separating into real and imaginary parts in order to make the calculation more efficient is
This can be modified by using the well-known method of decimating time or frequency by the number of points in the non-base region.

Similarly, the symbolic-numeric phonetic recognizer of the embodiments can be extensively modified while preserving the characteristics of the numerical and symbolic computations for each input frame, such as the correlation of each frame with a dictionary of frames and end-of-word inference rules. Can be done. Instead of LPG, other characterizations of the samples making up the frame may be used, and the dynamic time warp may be removed or made more extensive such that the stretch factor can be increased or decreased. , different end-of-word rules may also be utilized, and different parsers for the subdictionaries or no such parsers may be invoked to limit the correlation search.

EFFECTS OF THE INVENTION JT configurable monopoly hardwiring provides a faster system for executing a particular algorithm, but does not provide adequate flexibility for executing a variety of algorithms. The bus is
For most algorithms that use more than about 10 high-performance processors, saturation is likely (R.J. Hayduk and Noor A. Li). NA
"Research on structure and mechanics J" published by SA, 2335.15 (1984)
The closest neighbor connections between processors are cost effective for the algorithm. For example, NASA's 2-D processor array, MPP, is effective for edge enhancement. What is being built at Carnegie-Mellon College (K. Bromley)
)[, Bulletin 5PIE495.137 (1984)
Real Time Signal Processing J
Processing )
Kuekes (P, J, Kuekes) and M, S, 5chlausker
) such as systolic arrays (see H.T. Kung's ``Computer J'').
) l 5 (1), 37 (1982)),
ESL, Hughes (International Conference on Acoustics Speech and Signal Processing 85CH2i1B-8,3,1
392 (1984), J.G. Natsch (
J, G, Na5h) and C-petrozolin (C, P
etrozolin)), and N03C (edited by Kay Bromley, Bulletin 5PIE431.2 (1983))
J.M. Spacer in "Real-time Signal Processing"■
(J, M, 5peiser) and H.A. White House (H, J.

Whitehouse) is effective for convolution, correlation, and other easy-to-pipelin operations;
It is expected that it will dominate conventional signal processing in the near future. However, algorithms that require more complex connections perform less well and are also difficult to map onto such processors, especially for automated systems. Example computers can be reconfigured to give the appearance and performance of a hard-wired system, a systolic array, or a more complex network.

Generic Networks of Any Size and Speed (Lexington Books)
H.J. Sigel (1984)
Interconne Networks, Theory and Case Studies for Massively Parallel Processing J.
ctionnetwork for large 5c
parallel processing.

theory and case 5 studies)
) are too expensive using conventional semiconductor technology.

Therefore, today's systems have multiple stages requiring several switches between input and output terminals or between incomplete crossbar switches. BBN Butterfly Machine (rSRC Technical Report J (SRC Technical Report) by D, Y, Cheng, University of California Berkeley
N1059 (1984)) has multiple stages of 4x4 crossbar switches interconnected in a fully shuffled network and is located at TRAC (J.C.Br.
own )'s ``Physics Today J (PhysicsT)
37 (5), (1984)) uses a 2×2 switch of Banyan's configuration. Multiple stages increase latency and control complexity.

Passing messages further increases overhead, resulting in further sacrifices in speed and flexibility. Intel (I
) 1Psc is Nismic Cube (Co
sa+ic Cube)
．． 5eLtz) rACM communication J (Coau++u
cation of the ACM)2B(1
), 22 (1985)) and has 2'=64 nodes with distributed memory at the apex of a six-dimensional hypercube interconnection system. The processor is connected to 6 out of 64 other processors, which provides more algorithmic flexibility and control complexity than a systolic array, but less flexibility than a fully reconfigurable network. . The example signal processor is fully reconfigurable and uses pre-programmed optical switches to provide high speed, lower latency and simpler control than multi-stage reconfigurable systems.

The monopolized programmable booter flow reduces the overhead time spent in memory address calculations, instruction decoding, and memory and instruction fetching. Dataflow provides a mechanism for executing a directed graph for an algorithm on any suitable reconfigurable machine ("Computer J
(Computer) 13 (11), 48 (198
0) J.B. Dennis
) r Computing Overview J (ComputingSurv
eys) 14 (1), (1982)
Earl Treley Pen (D, R, 7releaven
), Earl Brownbridge (R, Brownbri)
dge), and R.B. Hopkins (R,P,
Hopkins), as well as C.R. Vick and C.V. Ramamoorthy wA.
Software Technology Handbook J
of Software Engineering
) (1984) in Dee Offsley (D, 0x
ley), Bee Sober (B, 5auber)
, M. Cornish)
.

The ohelator operates as soon as it has all the necessary inputs. Flexibility and the ability to perform recursive functions have a higher priority than speed in most dataflow projects, which tend to be directed toward general computation or artificial intelligence rather than signal processing; , dynamic allocation of processors, and transmission of packets containing information about future operations, routing, and data. Examples of current prototype machines include the MIT machine (Arvind
d) and R.A. Iannussi (R.A.).

rMIT Report J (MIT
Report) MI T/L CS/TM-241
(1983)), Manchester Dataflow Machine (J.R.Gurd)
C,C,Kirkham
) and i.Watson (1, Watson) rACM
Communication of th
e ACM) 28(1), 34 (1985)),
Japanese Sigma 1 machine (R.M. Keller)
M, Keller) Pigeon 84CH2045-3, I
In International Conference on Parallel Processing, EEE Bulletin 524 (1984), l1iraki, T., 5his.
ada, K., N15hida), and Texas.
Instruments Machine (IEEE Conference Proceedings 19 (19
79) M. Cornissi's (M, Cornisi) 3rd Conference on Digital Avionic Systems
There is ish )).

The example computer uses a virtually programmed boot flow. The data path and operation order in each elementary processor is precomputed to reduce the need to send overhead bits. Each elementary processor with all necessary inputs performs prespecified operations on data from input terminals or internal memory determined by local codes and synchronization pulses, the purpose of which is to perform a predetermined simple The goal is to obtain maximum throughput and minimum latency through control and data flow strategies.

Single-occupancy optical interconnects overcome mid-band pin limitations and edge connection constraints, with the advantage of reduced capacitive loading effects and greater insensitivity to mutual interference compared to electronic interconnects. To overcome this problem and to connect multiple processors, optics have been previously suggested for communicating with VLSI.

The telecommunications industry is developing optical switching devices to avoid converting to electro-optics and to support the purpose of switching when using optical fibers. Developments in optical spatial light modulators suggest that crossbar switches will become available at costs, speeds, and sizes that are unlikely to be matched by conventional semiconductor technology. It is expected that digital optical computers will eventually become viable, and a design for solving the proximate problems is proposed in co-pending U.S. Patent Application No. 777.660. listed in the number. Such a computer is different from that of the embodiment,
Flexibility is limited due to the interconnection system used and does not compromise real-time processing.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing a general optical crossbar-connected parallel processor type computer, Fig. 2 is a block diagram showing a high-level parallel architecture, and Fig. 3 is an optical crossbar-connected parallel signal of the first embodiment. FIG. 4 is a block diagram showing the basic processor of the first embodiment, and FIGS. 5A and 5B are optical crossbar diagrams.
Diagrams for explaining the operation of the switch; FIG. 6 is a schematic diagram showing a possible optical arrangement for an optical crossbar switch in the form of a deformable mirror device; FIGS. FIGS. 8A and 8B are perspective views and diagrams to explain the operation; FIGS. 8A and 8B are diagrams showing the flow and crossbar switch settings for the filtering algorithm; FIGS. 9A to 9C; FIGS. 11
Figures A and 11B are diagrams showing the flow and crossbar switch settings for fast Fourier transform;
Figures A and 12B are diagrams showing the flow and crossbar switch settings for the doubling algorithm for correlation and matrix-vector multiplication; Figure 13 illustrates the parallel computation of linear prediction coefficients by Joule's algorithm; Figures 14 and 15 are diagrams showing forward and backward chain rule conformance graphs, Figure 16 is a block diagram for explaining speech recognition by embedded system flow versa, and Figure 17A is a diagram showing forward and backward chain rule compliance graphs. Figure 17B is a diagram for explaining the principle of dynamic time warp, Figure 18 is a diagram showing the flow graph for the continuous dynamic time warp algorithm, and Figure 19 is a diagram showing the end-of-word determination and Figure 20 is a diagram showing the flow graph for recognition, Figure 20 is a diagram showing the operand analysis tree, and Figure 21 is a diagram showing the situation action weight.
FIG. 3 is a diagram illustrating a flow graph for the and sea parser. 102... Optical crossbar switch, 104... Fiber optical link, 110... Input/output device, 116... Controller, 134... Schlieren optical device. Ft'g, 7゜Channel stop Ft"1.7b Upper sound I3 boundary (Z8t cumulative 1 member □ biased input data (Method) ■Indication of the case 1985 Patent Application No. 283012
Item 3: Relationship with the person making the amendment Applicant 4: Agent

Claims (1)

[Claims] 1. (a) a plurality of parallel processors; (b)
) a resettable optical crossbar switch, said switch switchably interconnecting said processors in pairs such that an output from a first processor is directed to an input terminal of a second processor; and (c) a controller for synchronizing the processors and controlling the settings of the optical crossbar switch; and (d) an input/output device connected to the plurality of processors. 2. (a) The computer according to claim 1, wherein the processor performs only basic calculations. 3. (a) The computer according to claim 1, wherein the crossbar switch is dynamically resettable. 4. The computer according to claim 1, wherein (a) the optical crossbar switch is a deformable mirror device with schlieren optics. 5. (a) The switch is illuminated by a light emitting diode or laser diode activated by a processor, and the unobstructed light reflected by the switch is detected by a photodiode driving the processor. Computers mentioned in section. 6. The computer of claim 1, wherein: (a) the interconnect includes a fiber optic link. 7. The computer of claim 1, wherein: (a) the plurality of processors comprises a first plurality of lower order numeric processors and a second plurality of lower order symbolic processors. 8. A computer capable of dynamically resetting hardware between parallel and pipelined architectures, comprising: (a) a plurality of processors; and (b) a resettable optical crossbar switch, the switch comprising: The processors are switchably interconnected in pairs such that the output from the first processor is directed to the input/output terminals of the second processor, such that the setting of the switch allows the processors to be connected in parallel, pipelined or otherwise. A computer characterized in that it can be configured as a mixture. 9. A real-time speech recognizer for large words: (a) a plurality of subdictionaries according to the part of speech of the words; (b) a word recognizer with a word-end detector for speech input data; (c) ) a rule-compliant parser, the parser comprising: (i) a rule-compliant parser;
resolve the ambiguity for the above recognizer, and (
ii) A real-time speech recognizer, characterized in that it selects a subdictionary to the word recognizer to apply to the input data subsequent to the end of the detected word. 10. The real-time audio recognizer of claim 9, wherein (a) the audio input data is processed as a continuous stream of frames.