JPS62256536A - Power line carrier system - Google Patents

Abstract

PURPOSE:To attain sure data transmission/reception even when a plural number of transmission data are sent at the same time by retarding the transmisson of data from itself when the superimposing time of a superimposing bit signal is shorter than the superimposing time of the superimposed bit signal. CONSTITUTION:Equipments 2-1, 2-2,-2-n such as a computer, a printer, a memory device, a load controller and a load control terminal equipment are connected to the power line 1 of AC 100V. The equipments 2-1-2-n have a function that the superimposing time of each bit constituting a transmission data differs from each code represented by the said bit, the data is superimposed on a power waveform, the bit signal superimposed on the power waveform is detected and the data transmission from its own equipment is retarded when the superimposing time of the bit signal superimposed by the equipment itself is shorter than the superimposing time of the bit signal superimposed actually on the power waveform. Thus, even when plural data are set simultaneously, the data transmission/reception is attained surely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Industrial Field of Application) The present invention relates to a power line transport system in which transmission data is superimposed on a power waveform of a power line and transmitted and received between devices.

(Prior art) Such a power line transport system connects various devices such as computers and printers to power lines, and when transmitting and receiving data between each device, transmission data consisting of multiple bits is transmitted along the power lines. This is done by superimposing it on the power waveform.

Therefore, when transmitting data from a device, it is determined from the power waveform whether data is being sent/received between other devices, and if data is being sent/received between other devices, a waiting time is set and the wait time is set. The transmission operation is started again after a certain amount of time has elapsed.

However, when data is transmitted from multiple devices at the same time, these transmitted data are simultaneously superimposed on the power waveform, resulting in each transmitted data being destroyed. Even if the transmitted data was destroyed in this way, the data could not be transmitted from the device again, and the system could not transmit or receive sufficient data. Further, even if the transmitted data is destroyed by external noise, retransmission is not performed, and as in the case where a plurality of transmitted data are transmitted at the same time, sufficient data transmission and reception cannot be performed. Furthermore, while other devices are continuously transmitting data, even if there is urgent data to be transmitted, the user has to wait until the other device finishes transmitting data.

(Problems to be Solved by the Invention) As described above, in the conventional system, when a plurality of transmission data are transmitted simultaneously, the transmission data may be destroyed, and transmission data cannot be transmitted preferentially.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is an object of the present invention to provide a power line transport system that can reliably transmit and receive data even when multiple pieces of data are transmitted simultaneously, and that can preferentially transmit desired data. .

[Structure of the Invention] (Means for Solving the Problems) The present invention superimposes transmission data consisting of multiple bits on a power waveform on a power line, and transmits and receives data between devices connected to the power line. In a power line transport system that performs This is a power line transport system that attempts to achieve the above object by having a function of delaying transmission data from itself if the superimposition time of the bit signal is shorter than the superimposition time of the bit signal superimposed on the power waveform.

In addition to the above-mentioned functions, the present invention also provides the device with a second function of adding a priority bit signal, which takes longer to be superimposed on the power waveform as the transmission priority becomes higher, to the earliest position of the transmitted data and superimposing it on the power waveform. This is a power line transport system that attempts to achieve the above objectives.

(Function) By providing such a means, each bit constituting the transmission data is superimposed on the power waveform with different superimposition times depending on its code, and the bits actually superimposed on the power waveform are detected, If the superimposition time of the superimposed bits is shorter than the actual bit superimposition time, the transmission of the transmission data is delayed.

In addition, when transmitting data with priority, a priority bit with a superimposition time according to the priority is added to the first position of the transmit data, and each bit constituting the transmit data is Detect bits that are superimposed on the waveform and actually superimposed on the power waveform, and if the superimposition time of the superimposed bits is shorter than the actual bit superimposition time, data transmission is delayed (Example) Below , an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a power line conveyance system, in which a power line 1 with an AC voltage of 100 V is connected to various devices 2-1.2 such as a computer, a printer, a storage device, a load control controller, and a load control terminal. -2,...2-
n is connected.

These devices 2-1 to 2-n have a function of superimposing transmission data having a field configuration as shown in FIG. 2 onto the power waveform of the power line 1 and transmitting and receiving data between each device 2-1 to 2-n. are doing. Note that the transmission data consists of a 1-bit start bit, a 4-bit control code, 8-bit data, and a 4-bit control code.
It consists of a checksum of bits. The control code indicates the data destination devices 2-1 to 2-n and the content of the data, and also indicates whether or not an ACK (acknowledgement character, consisting of 4 bits) is required to be returned from the destination device. There is. The specific configuration of these devices 2-1 to 2-n is as shown in FIG. 3, in which a coupling circuit 3 such as a transformer is connected to a power line 1, and a transmitting circuit 4 and a receiving circuit 5 are connected to this coupling circuit 3. It is used to send and receive data. Further, a power supply circuit 6 is connected to the power line 1, and a power synchronization circuit 7 is provided which obtains a synchronization signal synchronized with the power supply frequency from a rectified waveform etc. obtained by the power supply circuit 6. A control circuit 8 having a function of controlling data transmission and reception
is provided, and data transmission and reception is performed by this control circuit 8 according to a data transmission and reception flowchart shown in FIG. In other words, each device 2-1 to 2-n
As shown in FIG. 5, the superposition time of each bit constituting the transmission data is indicated by each code (for example, a start bit).

rOJ, 'rlJ) are separately superimposed on the power waveform W, and together with this, the bit signal superimposed on the power waveform W is detected, and the superposition time of the self-superimposed bit signal is actually superimposed on the power waveform W. If the superimposition time of the bit signal is shorter than the superimposition time of the bit signal, the iFa delays data transmission from itself.
power waveform W1 by adding a priority bit signal, which takes longer time to be superimposed on power waveform W as the transmission priority becomes higher, to the first position of the transmission data, that is, before the start bit.
; and a superimposed second function. Note that the start flag, bit "0" and bit "1" are high frequency signals that are sufficiently higher than the power supply frequency (for example, AM modulation).
The superimposition time is T1 for the start flag, T2 longer than the time T1 for the bit rOJ, and T3 longer than the time T2 for the bit "1".

Next, we will discuss the operation of the system configured as described above in the fourth section.
This will be explained according to the transmission/reception flowchart shown in the figure.

To explain the operation of the device 2-1, in step s1, the power waveform of the power line 1 is received by the control circuit 8 through the coupling circuit 3 and the receiving circuit 5, and the control circuit 8 determines whether transmission data is superimposed on the power waveform. do. If it is determined that the transmitted data is superimposed, the process moves to step s2, the transmitted data is received, and it is determined in step S3 whether the checksums match. Then, if the checksums match, send an ACK to the device 2 that sent the data.
-2 to 2- It returns ACK to n and executes other processes such as lamp lighting and load control, and if the checksums do not match, it returns NAK (Negative Acknowledgment Character).

Now, since the transmission data is not superimposed on the power waveform, step s
If the transmission data is to be sent based on the judgment in step 7, the next step s
In step S8, it is determined whether there is a waiting time and the process moves to the next step S9. In this step S9, the transmission data to be transmitted from now on is urgent, that is, other devices 2-2 to 2-n.
It is determined whether there is a need to transmit the transmission data with priority over the transmission data transmitted from the . By the way, this transmission data is superimposed on the power waveform through the transmission circuit 4 and the coupling circuit 3 according to the field configuration shown in FIG. Specifically, as shown in FIG. 5, each bit of the transmission data is superimposed one by one after a predetermined time Ta from each zero-crossing point every half period of the power waveform. Now, the transmission data superimposed in this way is transmitted to the receiving circuit 5 at the same time as this superimposition.
At step sll, each bit of the superimposed transmission data and the actually superimposed transmission data are compared at any time to determine whether they match.

Now, if the data transmitted from the device 2-1 is the transmission data Da shown in FIG. 6, and data Db is transmitted from the device 2-2 at the same time as this transmission data Da, each bit of these data Since the code of the third bit of the control code ("1", "O") is different, the code actually superimposed on the power waveform has the bit "0" erased and becomes a signal of bit rlJ. This is because, as shown in FIG. 5, the superposition time of bit "1" is longer than the superposition time of bit rOJ. As a result, the device 2-2 stops transmitting the transmission data Db based on the determination in step sll, and sets a waiting time determined from a random number or the like. Therefore, the data that is actually transmitted superimposed on the power waveform is Da", which has the same configuration as Da, and the transmission of this transmission data Da is given priority over the transmission data Db. Then, the device 2-1 transmits the transmission data Da". When the transmission is completed, in step s14, the device receives an ACK returned from the designated destination devices 2-3 to 2-n, and if the ACK is normal, executes other processing. If not, step s9
and transmits the transmission data Da again. On the other hand, device 2
-2 executes the transmission operation of the transmission data Db again after the waiting time has elapsed.

Next, a case where transmission data is urgently transmitted will be explained. In this case, the priority of data transmission is determined in two stages in step S9, and in the case of an upper stage that requires very urgent transmission, a signal with a priority bit "1" is added to the first position of the transmission data in step s18. , and in the case of the lower stage, the signal of the priority bit rOJ is added to the first position of the transmission data in step s19. Therefore, equipment 2-
1, in step 10, transmission data Dc as shown in FIG. 7 is superimposed on the power waveform and transmitted (Dc- in FIG. 7). By the way, when the transmission data Dd is transmitted from the device 2-2 at the same time as the transmission data DC, the transmission data Dc is prioritized due to the difference in the superimposition time between the priority bit "1" signal and the start flag. The device 2-2 stops transmitting the transmission data Dd. Also, when the signal of the priority bit rOJ is added to the first position of the transmission data and transmitted from the device 2-2, the device 2-2
Data transmission from is stopped.

In this way, in the above embodiment, the bits are superimposed on the power waveform with different superimposition times depending on their codes, and the bit signal actually superimposed on the power waveform is detected at any time, and the superposition time of the superimposed bits is determined. Since data transmission is delayed if it is shorter than the actual bit superimposition time, even if data is transmitted from multiple devices 2-1 to 2-n at the same time, the superimposition is performed using different bit codes first. The transmission data that takes longer time can be sent preferentially.
Furthermore, the device that has stopped transmitting data at this time can transmit data again after the waiting time has elapsed. Therefore, each device 2-1 to 2-
Even if data is transmitted from n at the same time, the transmitted data is not destroyed and data transmission and reception can be continued without any trouble. Furthermore, even if the transmitted data is destroyed by external noise, the data transmission can be continued until the transmitted data is reliably transmitted by returning an ACK.

In addition, when transmitting data with priority, a priority bit rlJ rOJ of the superimposition time according to the priority is added to the first position of the transmit data, so urgent transmit data can be transmitted preferentially. , and can be sent depending on the degree of urgency. In other words, even if one field of transmission data is being transmitted continuously, the data can be transmitted preferentially by transmitting the priority bit "1" or "0" in synchronization with the start flag transmission from another device.

Note that the present invention is not limited to the above-mentioned embodiment, and may be modified without departing from the spirit thereof. For example, create rXJ as a priority bit, and create this priority bit r
When XJ is superimposed on the power waveform, the configuration of the device that forcibly stops data transmission allows the transmission data to which this priority bit rXJ is added to be transmitted with the highest priority. Also,
The priority bit may be a modulation method such as not only high frequency signal AM modulation but also FM modulation.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a power line transport system that can reliably transmit and receive data even when a plurality of data are transmitted simultaneously, and can transmit desired transmission data preferentially.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the power line transport system according to the present invention, FIG. 2 is a field block diagram of transmission data transmitted and received in the system of the present invention, and FIG. 3 is a diagram showing specific equipment in the system of the present invention. FIG. 4 is a data transmission and reception flowchart of the system of the present invention, FIG. 5 is a diagram for explaining the superimposition effect of transmitted data, and FIGS. 6 and 7 are diagrams for explaining the data transmission and reception operation of the system of the present invention. This is a diagram for 1...Power line, 2-1~2-n...Equipment, 3...
・Coupling circuit, 4... Transmission circuit, 5... Receiving circuit, 6
...Power supply circuit, 7...Power synchronization circuit, 8...Control circuit. Applicant's agent Patent attorney Takehiko Suzue 2-1 2-2 2-3 2-n
Figure 1 Figure 2 2-1-2-n Figure 3 Figure 5

Claims (2)

[Claims] (1) In a power line carrier system that transmits and receives data between each device connected to the power line by superimposing transmission data consisting of multiple bits on a power waveform carried on the power line, the device superimposes the bits. The time is superimposed on the power waveform in a different manner for each code indicated by the bit, and the bit signal superimposed on the power waveform is detected, and the superimposition time of the self-superimposed bit signal is superimposed on the power waveform. 1. A power line transport system having a function of delaying data transmission from itself if the time is shorter than the superimposition time of a bit signal. (2) In a power line carrier system that transmits and receives data between each device connected to the power line by superimposing transmission data consisting of multiple bits on a power waveform carried on the power line, the device superimposes the bits. The time is superimposed on the power waveform in a different manner for each code indicated by the bit, and the bit signal superimposed on the power waveform is detected, and the superimposition time of the self-superimposed bit signal is superimposed on the power waveform. If the superimposition time of the bit signal being
and a second function of adding a priority bit signal whose superimposition time on the power waveform becomes longer as the transmission priority becomes higher to the earliest position of the transmission data and superimposing it on the power waveform. power line transport system.