JPS62256438A - Etching end-point control pattern - Google Patents

Abstract

PURPOSE:To facilitate observing the situation of etching process directly by a method wherein a predetermined pattern of a multilayer film and a cell pattern which is provided on the same surface as the multilayered film pattern close to it are made of conductive resist and the etching termination of the upper layer is detected by the resistance variation between the electrode terminals of the cell. CONSTITUTION:In order to form patterns 2 and 6 of the source and the drain of a transistor, a cell 8 shown by a dot line is used. Although the cell 8 is removed in the final stage, in the dry etching process, the dry etching is regulated by picking up the resistance variation obtained between electrode terminals 9 and 10 of both the ends of the cell 8. In other words, a predetermined voltage is applied to the leads drawn out from the electrode terminals 9 and 10 of the cell 8 by a constant voltage source and the current variation which follows the progress of etching is measured by an ammeter. The end point of etching can be judged with high accuracy by the resistance variation of the cell induced by the progress (time lapse) of etching process.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to pattern formation of semiconductor thin films by photolithography, and particularly relates to an etching end point control pattern for detecting and determining the etching end point.
1' 1 Yes.

[Conventional technology]

As a conventional etching end point detection method, JP-A-53-34
As described in Japanese Patent Laid-open No. 641, changes over time in the amplitude of atomic emission lines in the atomic emission spectrum caused by plasma generation can be monitored, and changes over time in the pressure of etching gas can be monitored as described in Japanese Patent Application Laid-open No. 60-2232. Examples of ways to do this include monitoring. In these plasma etchings, the starting temperature.

There is usually considerable variation in the etching sequence for various reasons such as changes in plasma conditions and etched areas. This is accomplished by ensuring that the etching ends at the correct time (i.e., end point) for optimal etching. That is, the layer to be etched is removed, but it is difficult to finish the etching without excessively etching the pattern in H and etching the underlying layer to a negligible extent. It is.

For example, when n0 amorphous silicon is formed on polysilicon, only the n0 amorphous silicon is selectively etched.

[Problem that the invention seeks to solve]

The above conventional technology chemically and physically detects the behavior and development of the gas generated when the sample surface is etched by dry etching, but does not directly capture the etching status of the sample itself, but is an indirect detection method. be. Therefore, the above phenomenon does not appear noticeably due to etching,
This was a problem in situations where the selection ratio was small and separation was difficult.

An object of the present invention is to enable direct observation of the etching process.

[Means for solving problems]

The above purpose is to form a predetermined pattern of a multilayer film that requires etching on an insulating substrate and a cell pattern provided on the same surface near the pattern using conductive resist, and then set the etching end point of the upper layer by dry etching to the cell electrode. Etching of a predetermined pattern is achieved by detecting a change in the resistance value of the terminal.

[Effect]

In the operation of the cell according to the present invention, the electrode pads of the cell are formed using a resist that has a photolithographic function and whose film itself is conductive.

Due to the external leads, the resistance of the cell changes as the first N is etched. As a cell structure commensurate with the resistance value of the object to be etched in the first layer.

By adjusting the cell length and electrode pad spacing, the etching process can be directly observed electrically, making it possible to determine the end point of etching with high precision.

〔Example〕

Embodiments of the present invention will be described below with reference to FIG.

The solid line in the figure shows the surface pattern of the matrix formed on the insulating substrate. Wiring electrode patterns 4 and 5 taken out from the source 2 and gate 3 of the transistor 1
The lines intersect continuously both vertically and horizontally, and are insulated from each other. Further, the drain electrode portion 6 of the transistor l is connected to the transparent conductive film pattern 7. In this embodiment, it is necessary to form the patterns 2 and 6 of the source and drain portions of the transistor 1 with high accuracy, so the cell 8 shown in the dotted line portion is used. In the final stage, the cell 8 is removed, but in dry etching, it is used for etching adjustment to catch the change in resistance value obtained from the electrode terminals 9 and 10 at both ends of the cell 8.

Next, the manufacturing process of the transistor 1 will be explained with reference to FIG. 1 regarding the AA' cross section in FIG. 2. A polysilicon island 12 is formed on the quartz plate 11 (1), a gate insulating film 13 is formed on the entire surface thereof (2), and then a polysilicon 14 and an amorphous silicon 15 thin film are successively formed. Next, by photolithography, n0 amorphous silicon 15 and polysilicon 4 were formed to form the source and drain parts 2 and 6 of the transistor 1.
FIG. 3 is a comparison diagram of the dry etch rates of n + amorphous silicon (b) and polysilicon (a) using CF4 gas. Since the etching selectivity ratio between the two is small (up to 1.4), in order to perform clear etching, it is necessary to perform etching with excellent detection sensitivity. That is, in FIG. 1(4), if the n+ amorphous silicon 15 is not just etched, the underlying polysilicon 14 will be etched and the transistor characteristics will be deteriorated. Therefore, a cell 8 is provided near the transistor 1 pattern and used for just-etch determination.

In the present invention, it is necessary that the resist 16 used in this step has a patterning ability for photolithography, and that the film itself is electrically conductive. That is, in dry etching, this resistor film 16 becomes the terminal portion 9, 10 of the cell 8. This terminal part is connected to electrode terminals 9 and 10.
The dry etching is controlled by connecting it to a resistance measuring system as shown in FIG. 4. For the purpose of explanation, only the cell part (the part surrounded by the dotted line) in Figure 1 (4) is taken out and drawn, and an example in which it is applied to the commonly used parallel plate type dry etching will be described. 6 High frequency application electrodes are placed in the reaction chamber 17. 18 and a ground electrode 19.
After the reaction chamber 17 is evacuated by the vacuum pump 20, etching gas of CF4 is introduced through the flow meter 21 to form a plasma discharge region 22 and perform etching. Numbers 23, 24, 25, and 26 in the figure are a matching circuit, a high frequency oscillator, a vacuum gauge, and a valve. A constant voltage power supply 27 applies a predetermined voltage to the leads taken out from the terminal portions 9 and 10 of the cell 8, and an ammeter 28 measures changes in current as etching progresses.

As shown in FIG. 5, the resistance value of the cell changes as the etching progresses (time passes), making it possible to accurately determine the end point of the etching. Therefore, by understanding the etching state of cells placed adjacent to the transistor pattern, it is possible to control etching with high precision6. However, if the etching state cannot be directly observed in the plasma, the plasma is stopped but the etching is not carried out in the atmosphere. It is also possible to go back and check the resistance value of the cell 8. In addition, it is convenient to sense the end point of etching by emitting a signal such as a buzzer. The cell shape used in this method is determined in accordance with the resistivity of the etching material, the etching selectivity with respect to the underlying material, and the processed pattern of the transistor. As specific examples of cell shapes, in addition to FIG. 2 (shown by dotted lines), shapes such as those shown in FIGS. 6, 7, and 8 can be considered, and the cell length and electrode width can be controlled. After the end point determination is completed and the etching of the amorphous silicon is completed, the area around the transistor 29 is etched by photolithography again.
0Amorphous silicon, polysilicon etching cut. In this process, the etching selectivity with respect to the underlying gate insulating film 13 is sufficiently large and there is no problem, as shown in FIG.
As shown in 5), the cell 8 used in the previous step (4) can also be completely removed by etching. Therefore, in process (4), after using the cell 8 for determining the end point of dry etching, the interlayer insulating film 30 is formed, and the source 2%
A contact window is opened in the drain part 6, and the AQ electrode 31,
form 32. Furthermore, even if a cell is used for etching adjustment as described above in 6 in which a transparent conductive film 7 is formed in the display area, it will not cause any problems in the display such as a reduction in the aperture ratio when it is finally removed.

Next, an example in another process will be described with reference to FIG. This is the manufacturing process for the AA' cross section of the transistor 1 in FIG. 2, similar to FIG. 1 of the embodiment. As shown in processes (1), (2), and (3), polysilicon 12°n + amorphous silicon 15. M
The O film 33 is sequentially formed, and a transistor 1 pattern is formed by photolithography using the conductive resist 16. In this case, if overetched, MO
Since the etching speed of the film 33 and the amorphous silicon are fast and they are etched separately, side etching occurs. This side etching causes variations in transistor pattern formation, making it impossible to obtain characteristics with good reproducibility. In this way, even in the etching of a two-layer film, the above-mentioned 1.6, 7.
8 [Cell 8 having the shape described in 1 is used in the same manner as in the previous example. Further, the photoresist has a pattern processing ability for photolithography, and the conductive resist film 16, which itself is electrically conductive, is used, and the etching cut adjustment is performed based on the resistance change by the cell 8. After etching the n1 amorphous silicon and Mo film by the etching end point determination according to the present invention, regarding the transistor peripheral area 29,
First, polysilicon is etched (4), then a glabellar insulating film 30 is formed, windows are opened for the source/drain parts 2 and 6, and AQf! Transparent conductor fi! is formed on the 0 display area where single pole pads 31 and 32 are formed and the gate electrode 34 is also formed. l! ! iI
7 is formed and connected to the drain part 6. In this case too,
As in the previous embodiment, highly accurate etching can be performed using the cell for determining the end point of etching.

By carefully arranging the cell of the present invention on the substrate, the etching distribution of the entire matrix can be determined.

For example, even if the substrate 11 has a large screen as shown in FIG.
In Figure 0, which shows the etching of the entire area, the x-marked area is the transistor element 1.0-marked area is the cell 8, and the mouth-marked area is the terminal portions 9 and 10 of the cell 8.

〔Effect of the invention〕

According to the present invention, it is possible to accurately determine the etching end point even for a film with a small selectivity in multilayer film etching. Furthermore, it is possible to grasp the progress of etching over the entire area of the substrate. Furthermore, used cells can be removed in the next process. Even when the present invention is applied, there is no problem of reducing the porosity of the display portion of the matrix.

[Brief explanation of drawings]

FIGS. 1 (1) to (6) are explanatory diagrams of embodiments of the etching end point control pattern of the present invention, FIG. 2 is a detailed explanatory diagram of FIG. 1, and FIG. 3 is a supplementary explanatory diagram of FIG. Figure 4 is the first
Figure 5 is a supplementary diagram of Figure 1. Figures 6, 7, and 8 are diagrams of the cell shape of the element in Figure 1, and Figure 9 ( 1) to (6) are explanatory diagrams of other embodiments of the etching end point pattern of the present invention,
FIG. 1O is a cell layout diagram of the device of FIG. 1. 2... Source part, 7... Transparent conductive film, End... Cell, 9. .

Claims (1)

[Claims] 1. When a low-resistance semiconductor thin film is formed on a high-resistance semiconductor thin film on an insulating substrate surface and only the low-resistance thin film is cut by etching to leave an island-like pattern, the low-resistance region is placed near the desired pattern. An etching end point control pattern characterized by forming an inspection area consisting of two opposing island-like patterns such that residual immersion can be detected by measuring electrical resistance.