JPS62251838A - Virtual computer system - Google Patents

Abstract

PURPOSE:To determine the specification of a virtual computer identifier independently of the capacity of an I/O device by arranging plural identifiers and a registration table for the upper and lower addresses of storage areas corresponding to the identifiers in the I/O device. CONSTITUTION:An instruction 400 is inputted to an instruction execution control part 150, decoded by an instruction code and interpreted as a virtual computer identifier (VMID) registering instruction. An instruction execution part 150 sends the specified VMID, the contents of a general register and the upper and lower limit addresses to an upper/lower limit entry control part 420 in the I/O device. If an entry has a blank, the control part 430 registers the transmitted VMID and the upper and lower limit addresses alpha, beta in a registration table 440. In this case, a hardware corresponding to the VMID determines the VMID (HVMID) to be discriminated and registers the determined VMID in the same entry.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a virtual computer system, and in particular, in determining a virtual machine identifier, the control program VMCP of the virtual computer system is executed independently of the actual hardware. The present invention relates to a virtual computer system that is effective when creating a virtual computer identifier.

[Conventional technology]

The virtual J1 computer system is as shown in FIG.

Below the real computer system 100, there are virtual computers VMI, VM2゜...VM having architectures similar to this one.
n is defined. 1 on each virtual machine, each operating system O3, os2. ...OS
, 1 run in parallel, and each user program runs under it. Each virtual machine.

Real computer system! 00 and similar instruction set, memory,
It is the control program VMM on the real computer system 100 that realizes them by simulation and schedules the VM group.

By the way, in such a conventional virtual computer system, 1
For example, as shown in Japanese Unexamined Patent Publication No. 55-4232G, the main memory of a real computer system 100 is provided as the main memory of a virtual machine from the CPU to the channel side (that is, the I10 processor side). The information identifying the area is being sent.

In addition, as shown in FIG. 8, each virtual machine VM11 V
Mz + ”・On VMt1, respectively.

SL+○S2. ...○Sn operates. Each VM is
A real computer with an architecture similar to that of a real computer]
This provides each OS with exactly the same environment as when running on 00. In a computer system having virtual memory, prefix conversion exists for converting a real address into an absolute address. This is the document IBM/
Principles of operation of system 370
of ○perat, ion) GΔ22-700
In this specification, since prefix conversion is not directly related, it will be ignored and real addresses and absolute addresses will be used without distinction. In order to improve the performance of the virtual machine, TL[l (Tran
slaeion Look-aside Buffa
r) A quick reference table for address conversion is prepared, in which virtual addresses and corresponding real addresses are registered. By searching the registered contents of this TLB, if it is registered, the address can be converted just by reading it, so that the conversion process can be performed in 51 machine cycles or less.

Note that in a real computer system, the start address (ST○) of the address translation table, the correspondence between virtual addresses and real addresses, etc. are registered in the TLB.

There is no need for a VM ID (virtual machine identifier) registration field.

However, in a virtual computer system, the same S
Since T○ may exist, if the VMID is not in the TLB,
The TLB must be invalidated every time the VM switch is switched. This hinders effective use of the TLB. For this reason, near 5Ek, as the scope of use of virtual computer systems expands, T1. VM within +3
Computer systems with IDs have appeared (for example,
JP-A-55-113182 and JP-A-53-101
No. 234 (described in each publication). Some of these computers have virtual machine identification T-(
VMID), and others have VMIDs directly registered in T[,,B. And these all have TLI3 entries,
This is to make the TLB valid only for the relevant area or the relevant VM, and to prevent invalidation of the TLB due to switching between areas or between VMs. Furthermore, the TL within a region or within a VM
This is also to realize partial invalidation of I3.

[Problem that the invention seeks to solve]

First, the main memory of the actual computer system + JAli! We will discuss the problems when transmitting information that identifies the area. (a) The capacity of a table (consisting of a register group or memory) in which area identifiers are registered is determined depending on the hardware, and is often hardware model dependent. However, the number of areas is determined by the software environment, such as the number of activated VMs and the maximum number of areas when the virtual computer system is generated. Therefore, J'L should be determined independently of the hardware capacity, but how to deal with the number of areas exceeding the hardware capacity, and how to take a program structure that does not depend on the hardware capacity. It is unclear how this should be done.

(b) When the channel accesses the main memory bag,
Access is performed using an area relative address and an area identifier, but in this method, 1, for example, 32
Assuming that 4096 bytes of data are transferred in byte units, for every 32 bytes, 409G/32 = 128 selections of area identifiers, addition of the lower limit (starting point) address of the area, and comparison with the upper limit (final) address are performed. It is necessary to perform checks, and these can easily become a bottleneck in performance. (C) Virtual calculation 1! ! ! Identification and area identification do not necessarily match. For example, one virtual computer may be used by merging two consecutive areas.

Next, problems when registering an area identifier or VMID in the TLB will be described.

The capacity of the storage field for the area identifier or VMID in the TLB (in bits, for example) depends on the hardware, and it is difficult for the program to be aware of the number k in the program. This violates hardware independence (that is, the same computer family, such as the M series computer or the 18M System 370 series, can operate without modification on any model).

This is because the number of bits mentioned above varies depending on the model. Regarding TLB, for example, the VMID identified by the program is 16 bits (therefore, 0 to 6 bits).
5,535), when the number of vMID bits in the TLB is 4 bits (therefore, 0 to 15 when decoding, or 4 when not decoding), the program:
Even if a different VMID is specified, the VMID in the TLB will have the same value, so it is necessary to invalidate the old VMID entry in TL[3. Therefore, if this is to be implemented by a software program, the number of bits k must be recognized. Furthermore, the VMID specified by the software program
Which of the following pins is sent to the VMID in the TLB? ,
Whether the former VMID is recorded or how the former VMID is converted to the VMID in the TLB is a hardware implementation issue, but the above disabling can be done using a software program. If you try to do so, the program will have to be aware of these methods, which will further violate the program's hardware independence. The above two conventional examples also do not provide equivalent solutions to these problems.

The purpose of the present invention is to improve these conventional problems and to change the VMID 1u setting of the control program of the virtual computer system to I1.
0 can be determined independently of the hardware capacity of the processor side, and when providing the VMID in TLI3, TLI3
Regardless of the capacity of VM
The object of the present invention is to provide a virtual computer system that can determine the ID bins 1 to 1 and determine the software structure independently of the hardware configuration 17.

[Means for resolving issues]

In order to achieve the above object, a virtual computer system of the present invention includes a control program that runs multiple operating systems simultaneously.
A registration table is provided in the I10 processor in which one or more identifiers and upper and lower limit addresses defining areas in the main memory corresponding to the identifiers are registered, and the CPU
By notifying the I10 processor of the virtual machine identifier identified by the control program and the upper and lower limit addresses that define the contiguous area of the main storage of the virtual machine, the I10 processor receives the received identifier and upper and lower limits. The address is registered in the above registration table, and when the weighing table is full, a message to that effect is sent to the C from the I10 processor.
The feature is that the PU is notified.

In addition, a table is provided for storing a means for converting a virtual machine identifier identified by the control program into an identifier identified by the hardware of the real computer and a corresponding result after the conversion. When registering the correspondence results in the conversion table, if the table is full, select one of the correspondences, invalidate it (or multiple if it is convenient to limit it to one), and create a new correspondence. There is also a feature in activating the .

[For production]

In the first embodiment of the present invention, means for registering a VM ID (virtual machine identifier) in the I10 processor;
The I10 processor's virtual total The VMID specified by the computer system control progera t1 is I10.
When a surplus is issued to be registered in the registration table in the processor and the instruction is executed, when the registration table is full, the 110 processor notifies the CPU using the condition code of the instruction execution result that registration is impossible. t. When the I10 processor receives an input/output device activation command from the CPU and executes the corresponding channel program.

In the I10 processor, select the VMID in the above registration table, read the upper and lower limit addresses of that area, and add the lower limit (starting point) address of the corresponding area to the address of the CCW group that is the channel program and its data address, While checking the upper limit address, the CC
Execute W group.

Furthermore, in the second embodiment, a VMID effective for improving the performance of a virtual computer system is realized by hardware and software while maintaining the hardware independence of software.

(Example〕 Hereinafter, embodiments of the present invention will be described in detail with reference to one drawing.

FIG. 2 is a diagram showing a method of allocating a main storage device of a virtual machine. In the main storage device 200 of the real computer system 100 in FIG. 8, as shown in FIG. 2, there is an area 1.
Area 2. . . . Define areas n and assign them to VM1.
VM2. ...It is identified as the main storage device for VMn. Area 1. Area 2. ...The lower limit address (that is, the starting address) and the upper limit address (that is, the final address) of area n are (αl, βl) and (α2
It is expressed as ゜β2), ... (αn, β11). These addresses are system real addresses, with the first address of the main storage device 200 being ○. As aforementioned,
Honmei a! The book does not distinguish between real addresses and absolute addresses. Further, although a real address is generally converted to an absolute address by prefilative conversion, in order to simplify the explanation, in this specification, prefilative conversion will also be ignored.

The prefix conversion is when the prefix value is γ page (one page is 4096 bytes).

For real address X page.

This conversion method corresponds to the absolute address 0 page when X=γ, to the absolute address γ page when x=Q, and to the absolute address X itself when X≠O and x≠γ.

However, the handling of addresses in ■/○ processors is as follows, except when interrupt information is stored in a prefix.
CCW addresses and CCW data addresses are often treated as absolute addresses. Therefore, in this specification as well, this method is used to handle the address as a data transfer address in the I10 processor, and in the following explanation, real addresses and absolute addresses will be used without distinction.

FIG. 3 is a diagram showing the memory hierarchy of a virtual machine that has the area shown in FIG. 2 (lower limit address α, upper limit address β) as a main storage device. In FIG. 3, 300 is the main storage device of this virtual machine, which occupies the area (lower limit α, upper limit By adding a constant α to the relative address), it can be converted to a system real address. 310 is a virtual space in which the OS on this virtual machine configures and manages its own virtual memory. The channel program prepared by the OS on this virtual machine, ie, ccwg320, is the main memory ff! of this virtual machine. 300 and its CCW
It is assumed that all addresses and data addresses in the CCW are handled as real addresses within the area. The configurations of FIGS. 2 and 3 described above are exactly the same as the conventional technology. The area definition in FIG. 2 and the memory hierarchy in FIG. 3 are all defined and managed by the virtual machine system control program VMM and the OS on the virtual machine.

FIG. 1 is a block diagram of the main parts of a virtual computer system showing an embodiment of the present invention. In FIG.

200 is the main storage of the actual computer system, 110 is the central processing unit, 120 is the I10 processor (■op), 47
0 is an input/output control device (IOC), 400 is a VMrD registration command, and 800 is an f10 activation command.

700 is a subchannel control block area, 150 is a CP
The U-instruction all instruction execution control unit 30 is an upper and lower limit entry control unit;
440 is an IOP (7) VM ID registration table, 450 is a CCW execution control unit, and 460 is a subchannel register group. As shown in FIG. 4, the instruction 400 executed by the CPUI 10 includes a code portion, a general register number 132.
consists of displacement D2, and upon execution, general register B2
The sum of the content (B2) and the value of displacement D2, ([32)+D2
contains the VMID, as shown at 420 in FIG.

This VMrD is arbitrarily determined by the control program VMM of the virtual computer system, and is determined independently of the hardware capacity of the I10 processor. moreover,
Area numbers shown in Figure 2 VMI, VM2゜...VM
Both n and n are values that can be determined independently. The operand of the instruction is the contents 41 of general register 1 (QRI).
Use 0. As shown in the instruction operand 410 in FIG. 4, the general-purpose register (ERI) includes the lower limit address α and upper limit address β of the upper storage unit of the virtual machine. Biso1 value must be 0.

In FIG. 1, this instruction 400 is executed by CPUll0 as follows. That is, the instruction 400 is sent to the instruction execution control unit 15 of CPUll0 via data 1soo.
It is taken into 0. The instruction execution control unit +50 decodes this using the instruction code and interprets it as a VM r ou record instruction from the CPUll0 to the I10 processor 120. The operation of the instruction execution control unit 150 is completely the same as the conventional one.

In addition, the instruction execution control unit 150 via the line 510
The specified VMID and the contents and upper and lower limit addresses of the general-purpose register GRI are sent to the upper and lower limit entry control unit 430 of the I10 processor 120. The control unit 430 controls the transmitted V
An attempt is made to register MID and upper and lower limit addresses α and β in the registration table 440. The registration table 440 may be a register or a local strange of the I10 processor. At this time, if there is an empty entry in the registration table 440, enter the VMID and upper and lower limit addresses α and β transmitted there.
Record. In this case, a VMID (hereinafter referred to as 1-IVM) that can be identified by the hardware corresponding to the VMTD is determined and registered in the same entry.

+1VMID may be 1, for example, the entry number of the registration table 440, but in any case, the range of its value is determined by the hardware capacity, which is the size of the registration table 440. The HVMID value is a value that is invisible to rough 1 to wear, but not to software.

There is no need to pay attention to the size of the registration table 440. Thus, after registering the information in the registration table 440, the entry control unit 430 of the I10 processor 120 sends the information to the instruction control unit 150 of the CPUI 10 via the line 510. A condition code of 0 is returned to indicate normal completion.

Furthermore, when the registration table 440 is full, registration is not possible, so the entry control unit 430 returns 1 condition code 1 to the instruction control unit 150 of CPUll0 via m510. In addition, if the function of the registration table 440 itself is not originally provided, or if VMI is
If the Dfi recording functions 430 and 440 are not present, no execution of this instruction is performed, and only the resulting condition code is set to 3. Furthermore, when registering in the registration table 440, if there is a VMID that is the same as the VMID specified by the virtual machine system control program, the upper/lower limit entry control unit 430 specifies it as a new one and writes all the contents in one file. shall be replaced. As a result, iteration table 41
It is possible to update the contents of 10. Further, the entry control unit 430 associates different I-IVMIDs with different VMTDs. As a result, the I10 processor 120 can thereafter identify virtual machines using the IVM ID (which has a small number of bits).

The VM ID registration instruction 400 can also have operands 420' and 410' shown in FIG.

FIG. 5 shows a registration deletion command. In this case, these operands are sent to the upper/lower limit entry control unit 430 of the ■/○ processor 120, as in the case of FIG. If it is determined that the value of pin 1-0 is 1, the specified VMID's en 1-ri will be turned on. , record 440
If it exists, it will delete that entry. This allows, for example, when a virtual machine is stopped and disappears (e.g., fl og o
ff L/tatoki) etc., the corresponding 7MID entries in the I10 processor 120 can be deleted.

Next, when actually starting an input/output operation for an input/output device, the activation command (800 shown in FIG. 1) is
Issued by PUll0. The operand of this instruction is the seventh
As shown in the figure, the address of a control block (an area on the memory 200) 810 containing the start address of the CCW group, the VMID specified by the virtual machine system control program, etc. is specified by ([32) +D2, and the general purpose The register GR1 (820 in FIG. 7) contains the subchannel number corresponding to the input/output device. As in the prior art, subchannel numbers have a one-to-one correspondence with input/output devices.

Next, the operation of this input/output device activation instruction 800 will be explained. When the error instruction 800 is issued, the VMID and the upper and lower limits are set normally for the corresponding VMID by the above-mentioned instruction 400 (see FIG. 4).
Assume that it has already been registered on the side. I/O device startup instruction 800
is the instruction execution control unit 1 of CPUll0 through the line 500.
50. The instruction execution control unit 150 detects the corresponding subchannel control block UCW from the subchannel number in the operand (general-purpose register GRI) of this instruction. The UCW group is a hardware system area (hereinafter referred to as "hardware system area") of the main storage device 200 in FIG.

11 SA, ) exists in a certain area 700.

ItsA is located in the main memory bag [200, but exists in a location that cannot be directly referenced from software. A control block UCW corresponding to each subchannel exists in this area. One UCW extracted from this is shown below.
This is UCW710 in FIG.

When the instruction execution control unit 150 detects the corresponding UCW, it writes there the contents of the operand 81O (see FIG. 7) and the CC
Write the W address, VMID, etc.

The instruction execution unit 150 further sends the VMID to the upper and lower limit entry control unit 430 via the line 510. The entry control unit 430 determines whether or not the transmitted VM list is registered in the registration table 440, and if it is registered, reads the corresponding 11 VMID and performs subchannel control via the line 530. Enter -H into block UCW (6th
(see figure). If the corresponding VMID is not registered in the registration table 440, the 2nd condition code 3 is reported to the instruction execution control unit 150 of the CPUll0 via the line 510, and the execution is terminated. If the UCW exists in the registration table 440, the UCW is further registered in the input/output activation request queue and sent to the line 520.
The I/O activation signal is sent to the CCW execution control unit 450 in the I10 processor 120 via the I10 processor 120. As a result, the execution of the input/output activation instruction 800 normally ends with condition code O, and the CPU 110 moves on to execution of the next instruction. Note that the input/output request queue described above is the same as that of the conventional technology, and therefore description and illustration thereof will be omitted. r10 processor 12
The CCV execution control unit 450 in CCV0 schedules input/output activation requests for each subchannel, and executes CCW that defines input/output operations for each subchannel sequentially and in parallel.The method is as follows. It is carried out as follows. That is, C.C.
The W execution control unit 450 accesses the subchannel control block UCW (see FIG. 6) in the input/output activation request queue via the line 530, and accesses the HVM ID in the subchannel control block UCW (see FIG. 6).
and CCW address, and writes the above HVM ID and 00w address to the corresponding subchannel of subchannel register group 460 via line 580. From then on,
The CCW execution control unit 450 receives IIVMID and C0w from the corresponding subchannel register 460 via a line 55o.
Reads the address, sends the HVMID to the upper and lower limit entry control unit 430 via line 570, and sends it to the registration table 44.
Upper and lower limits α and β from the corresponding entry of 0 via 1540
As a result, from now on, the lower limit address α is added to the 00w address and the CCW data address, and the specified CCW is executed for the corresponding subchannel while checking whether the upper limit address β is not exceeded. In this way, the address converted Ccw is sequentially sent to the input/output control bag [(I 0C) 47 via a560.
0, where it is interpreted and executed. In addition, I.O.C.
The subsequent operations are the same as those in the conventional case, so the explanation will be omitted.

Note that instead of VM ID (virtual machine identifier).

Even if the identifier of the area (the area serving as the main storage device of the virtual machine shown in FIG. 2) is replaced, the result is exactly the same. In this case, the area identifier identified by the virtual computer system control program and the area identifier identified by the hardware may be considered.

In this embodiment, the virtual machine system control program uses, for example, a 2-byte value (0, ~,
65, 535) can be freely specified, there is no need to be aware of the size of the VM IDQ list of the I10 processor, and it is only necessary to create a block diagram using the condition code of the dedicated VM r ou record instruction. Furthermore, since constant addition of the 00w address is performed within the I10 processor, only one constant addition (that is, the lower limit address) is required to convert the CCW address and data address to the real address of the system, and the VMID registration table It is possible to perform the search only once for each CCW execution for a subchannel.

In the conventional method, the I10 processor sends the address within the area of the main memory of the virtual machine and its area identifier to the CPU.
The CPU side performs area selection and constant addition, but this requires the above area selection and constant addition for each unit of data transfer between the CPU and the I10 processor, which causes performance problems. It can easily become a bottleneck. In this example, I
10 for the execution of Ilo on the subchannels since the above transformation is performed within the processor.

All it takes is multiple area selections and constant additions.

In this way, in this embodiment, V within the I10 processor
By registering the MID and adding a constant between the CCW address and its data address, the CCW address prepared by the OS on the virtual machine is converted to the real address of the system.
can be directly executed by the I10 processor.

Next, a method of realizing a virtual machine identifier while maintaining software hardware independence, which is a second embodiment, will be described.

Designation of virtual d1 computer system control program, VM ID (software VM ID) or area identifier to be managed, and VM that can be internally identified by hardware.
There is a difference in capacity between ID (hardware VM ID) and area identifier. In this embodiment, a method for solving this problem without depending on hardware implementation is realized.

Next, to give an overview, first, the software VMI
A conversion function f from D to hardware VM ID is defined as follows. (a) The value range of software VMID is 0≦VMID≦A, and the value range of hardware VMID is
O≦VMID≦B.

(b) h1=f(sl) gl =/7 toeware v
Let it be MID. If different S2 (≠l1l) correspond to the same hl, that is.

hz=f(sl)"ht's tosa-(lit t ht) set is invalidated, (
Alehl). (e
) With the function (b) above, only the equality and difference of software VMID values can be detected from the virtual machine system control program! ! ! It is sufficient to be aware of the hardware VMID, and there is no need to be aware of the hardware VMID. By realizing the function f having the above functions in hardware,
The virtual computer system control program only needs to be aware of the VMID that it manages;
It is possible to have a program structure independent of D.

FIG. 9 is a diagram showing the memory hierarchy of a virtual computer. In FIG. Continuously occupies the memory device 200 from address 0 to address α. The address X of the main storage device 210 of this virtual computer corresponds directly to the address X of the main storage device 200 of the real computer 100. 2
20 is a virtual memory of this virtual machine, which is generated when an OS having virtual memory is operated on this virtual machine, and is managed by this OS.

FIG. 10 shows the memory WtM of the virtual machine with V=Resi.
FIG. 310 is a main storage device of the virtual machine with V=Ra5i, which continuously occupies addresses α to β of the main storage 200 of the real computer 100. The address X of the main memory 310 of this virtual computer corresponds to the address X+α of the main memory 20'0 of the real computer 100. 320 is a virtual memory of this virtual machine, which is created when the OS on this virtual machine generates virtual memory, and is managed by the OS.

FIG. 11 is a diagram showing the memory hierarchy of a v=v virtual machine. 410 is the main storage device of the virtual computer where v=v, and each page is stored in the main storage device 2 of the real computer 100.
00 is on an assigned page. 420 is a virtual storage device of this virtual machine, which is the same as the virtual storage 220 in FIG. 9 and the virtual storage 320 in FIG. 10.

FIG. 12 is a diagram showing the main memories of a plurality of v=ROsi virtual machines. In FIG. 12, 310-1 is V=
In the main memory of the R virtual computer, the address αr of the main memory 200
Continuous area from (=O) to β1 (fJji area number 1)
to occupy. Further, 310-2 occupies a continuous area (area number 2) from addresses α2 to β2 in the main memory 200. Further, the same applies to 310-3.

FIG. 13 is a block diagram of main parts of a virtual computer system showing a second embodiment of the present invention. In Figure 13, 6
00 is the software VMID (hereinafter referred to as "software VMID") specified by the virtual machine system control program.

SVMID), and 620 is a register containing SVMID.
VMID and corresponding hardware VMID (hereinafter referred to as I-
This is a group of registers in which the IVMID (called IVMID) is stacked. 610 is a control unit of the VMID stack 620, which detects an overflow of the stack 620 and the like. 63
0 is a register containing the start address (STO) of the address translation table, 640 is a register containing HVMID, 6
50 is a register containing a logical address (LA), 660 is a TLB entry control unit, 670 is a TLB, and 680 is a dynamic address translation mechanism (D) that searches an address translation table.
AT).

Next, the operation shown in FIG. 13 will be described. When the virtual machine system control program dispatches (starts) a virtual machine, it specifies the SVMrD and uses a dispatch-dedicated command. During the command processing, the control unit 61O of the VMID-stack 620 performs the following: perform an action. That is, the SVMID is registered in the stack 620, and the corresponding HVMTD is determined and stored in the register 640 via the 8G 21. Furthermore, the control unit 610
In the stack 620, the SVMID is no longer full;
If it is detected that the registration is not possible, the entry in the stack 620 is invalidated, and the SVMID in the current register 600 is newly registered there. At this time, enter the HVMID of the invalidated old entry on line 6.
11 to the TLB entry control unit 660 to request invalidation of the corresponding TLI3 entry. The TLB entry control unit 660 stores the TLB6 including the specified HVMID.
Invalidate all 70 entries. As a result, the relationship between the new SVMID and I(VMID in the stack) becomes valid, and the new SVMID is activated while the virtual machine is running.

It will be registered in the TLB 670 as the I (VMID) of the virtual machine. The above operation at the time of virtual machine dispatch is a newly added process in this embodiment, and by this, the virtual machine system control program Only the SVMID needs to be recognized, and there is no need to manage the HVMID generation method or whether or not they overlap, and the hardware independence of the virtual computer system control program is maintained.

TLB670 operation while virtual computer is running, DAT680
operation, comparison circuit 690.700 a, 710, An
The operation of the cl gate 720 is all the same as before, but
This will be explained. That is, it is determined whether the logical address (LA) in the logical address register 650 is registered in the TLB 670, and if it is registered,
The corresponding physical address (PA) is read and stored in register 730. The address is real computer 1
It is sent to the main memory bag @750 of 00 and is referenced. To determine whether a logical address (LA) is registered in the TLB 670, a comparison circuit 69 compares the current address translation table start address ST○ 630 and STO in the TLB.
0, the results match, and the current HVMID640
and I-f VMID in TLI3 e 70 are compared by a comparison circuit 700a, and the results match, and the corresponding part of the current logical address and the logical address (LA) in the TLB are compared by a comparison circuit 710. , when the results match,
The output from the AND gate 720 becomes LL L ++, and it is determined that (LA) is registered in the TLB 670. If it is not registered in the TLB 670, the address is translated by the DAT 680 that searches the address translation table, and the resulting real address (P
A) is written to the corresponding field of the TLB 670 via the line 681. The corresponding entry of the TLB 670 takes out a certain part of the logical address LA and sends it via the line 651 to the TLI3 entry control unit 6GO. 660 calculates the value, and then the corresponding entry (
That is, determine the column). These operations are no different from the conventional ones.

In FIG. 13, two features of this embodiment are a VMID stack 620 and a control circuit 610. Therefore, this part will be explained in more detail.

FIG. 14 is an n-thin block diagram of the fj513 diagram (7) VMIDX tap'). The SVMIDs are stacked by the control unit 610 in the left field 620-L of the stack 620 in the order in which they are output, starting from the bottom entry. The entries in field 620-L are numbered o and l in order from the bottom entry.

2,..., register it in the field on the right, and register it as HVMID via line 621 to register 6.
Register at 40. The number of stages of this stack 620 is T L
B 670 NIOKERU HVM ID (7) If the number of bits is r (r≧1), the maximum is 2r stages. Generally, the number of bits r of I-IVMID is the number of bits r of SVMID.
~ less than a number.

When the stack control table m6t o detects an overflow (fullness) of the stack 620, it performs the following operation. That is, among the five stacks 620, the oldest registered entry is found and replaced with the SVMID (new SVMID) to be registered next.

At this time, if the old SVMTD and new SVMID are the same l-
Since it has I V M I D, HVM
The ID is sent to the TLB entry control unit 660 via 1tAC;11, and the TLB 67 with the specified HVM ID is sent.
Erase all entries of 0.

FIG. 16 is a diagram showing a method for finding the oldest entry in the stack of FIG. 13. In Figure 16, TL
I-IVMID (71) in B670 shows a case where the number of bits is 2, that is, a case where only 1-IVMID=0.1, 2°3 can be distinguished.On the other hand, SVMID
is more than this number, for example 16 bits, then 0, 1, 2 . ...You may be allowed up to 65,535. 620-1 in FIG.
0 represents a full state. 620-L, 620-
There are R, 620-F fields, of which 620-
The field of F is not shown in FIG. 14, but this has been omitted only to simplify the diagram. Now,
At 620-1 in Figure 16, the bottom entry (SVMID
Since 620-F (Q and HVMI Do) are the oldest entries, the value of the field 620-F is 1. The dotted arrow on the left represents the direction of the stack of SVMIDs. In this state, when trying to register a new SVMID4, the control circuit 610 looks at the field 620-F, finds an entry of 1, and sets it as a replacement target. In this way! The changed state is 62
0-2, and the oldest entry of 620-1 is (SVMI
D4. HVMIDO). At this time, as described above, the IVMIDO is sent to the TLB entry control unit 660 via 1J1611, and all entries in the TLB 670 including it are invalidated. Further, at 620-2, the value l of 620-F is shifted one entry up to represent the position of the oldest entry in the state of 620-2. 620-3.6
The same applies to 20-4. In this way, when disbatching a new virtual machine, ■MID stack 62
0 is updated and if a duplication occurs in the TLB 670, processing to invalidate the old entry is performed.

Other ways to generate correspondence between SVMID and HVMID,
This will be explained with reference to FIG. FIG. 15 shows a method of registering the lower (7) r via 1- of the SVM IDs as the HVM ID. is the bit width of HVMID in TLB 670. In other words, 5 stack control unit 610' outputs the lower r r of SVMrD in the order of output.
Register the bit via line 601 into the right field 620-R' of stack 620' and at the same time
The left side of the remaining three VMIDs is registered via line 602 to the same entry position on the left field 620-L' side of stack 620'. Thereafter, the value of the r bit is set in the register 640 as I-I V M I D. At this time, if the value of the lower r bits of the SVMID is the same, it is checked whether or not it already exists in the stack 620-R', and if it exists, the I-I V
Since the MID will be duplicated, the HVMID is sent to the TLB control unit 660 and the TLB with the I(V MID is
Invalidate all entries of LB670 and stack 620
-R' (7) Above HVM ID SVMI at position D (7)
The remaining left side of D other than the r bit is registered on the 620-L' side. Note that when the VMID stack 620 becomes full, there is a simple method of invalidating all the contents of TL[3670, but from a performance point of view it is inferior to the above method, so we will simplify it. Not preferable except in certain cases.

Furthermore, the correspondence between one or more SVMIDs and HVMIDs (f7) only needs to be performed once when dispatching a virtual machine, but when dispatching the same virtual machine as the previous one, since the SVMID is the same as the previous one, the previous HVMI
D can be used as is, and all stack black operations can be omitted.

In the above explanation, we have all talked about VMID, but if we are considering only the V=R computer and the V=Re5i computer as virtual computers, as shown in Figure 12, the main storage and memory of each computer Continuously used areas are numbered #1. #2. #3. It is also possible to add ... as an area identifier and use this instead of the VMID. In this case as well, if the number of areas defined by the virtual machine system control program is large, the TLB
In some cases, the number of bits in the region field (corresponding to the TLB 670 (7) HVMID field) is small, and conversion between the two is required in exactly the same way as in the case of VMID. By replacing HVMID with a hardware area identifier and SVMID with a software area identifier, the same argument and method can be achieved. However, this method requires V=R virtual computer (in the case of FIG. 9) and v
=Regi virtual computer (in the case of FIG. 10) can only be targeted, and as shown in FIG. 11, =v virtual computer cannot be targeted.

In this embodiment, when providing the VMID in the TLB, only from a software standpoint, regardless of the capacity of the TLB,
The number of bits in the VMID can be determined, independent of hardware capacity and implementation size.
You can decide on the clothing structure. Further, the correspondence between the software VMID and the hardware VMID only needs to be established once when starting up the virtual machine, and there is no overhead in terms of performance.

〔Effect of the invention〕

As explained above, according to the present invention, a virtual machine system control program can determine whether or not it has actually been registered in the ■/○ processor using only the VMID specified by itself and the condition code of the instruction to register it to the r/○ processor. It is not necessary to pay attention to the capacity of the registration table in the processor. Also, VMIDt! in TLI'3! : When setting, the V
Since the number of bits of the MID can be determined, it is possible to determine the software structure independently of the hardware implementation.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of a virtual computer system showing an embodiment of the present invention, Fig. 2 is an explanatory diagram of the main storage area of the virtual machine, Fig. 3 is an explanatory diagram of the memory hierarchy of the virtual machine, Figs. Figure 5 is a VMID (virtual machine identifier) registration command format diagram, Figure 6 is an explanatory diagram of the subchannel control block, Figure 7 is a format diagram of the I10 activation command for the subchannel, and Figure 8 is an outline of the virtual machine system. Explanatory diagram, Figure 9 is a memory configuration diagram of a virtual machine with V=R, Part 1
Figure 0 is a memory configuration diagram of a 'V'' Re5i virtual machine, Figure 11 is a memory configuration diagram of a v=v virtual machine, and Figure 12 is a memory configuration diagram of a virtual machine with V-, R, or V = Resi. Main storage area explanatory drawing
5 is an example diagram of the VMID stack in FIG. 13, and FIG. 16 is an explanatory diagram of exchanging old and new entries in the VMID stack. 100: Real computer, 11.
0: Central processing bag y1 (CPtJ), 120: I10
Processor (OP), 150: Instruction execution control unit in CPU, 200 = Main storage of real computer, 300 = Main storage of virtual computer, 210: Main storage of virtual computer of V=R, 220: V= Virtual storage device of R virtual machine, 310: V = main storage device of Re5i virtual machine, 320: V = virtual storage device of ReSi virtual machine, 400: Virtual machine identifier (VM ID)
Registration instruction, 410: Main storage of virtual machine with V=V,
420: Virtual storage device of virtual machine with V=V, 430:
Upper/lower limit entry control section, 440: within 10P (7) lvf
ID registration table, 450: CCW execution control unit, 460:
Subchannel register group, 470: input/output control device i!
! (IOC), Goo: SVMIDL/Jista, 610
:VMID,2. Tack control low path, 620: VMID
X tack, 630 register containing near address translation table start address, 640: [IV MID register, 650: logical address register, 660: TLB entry control unit, 670: TLB, 980: dynamic address translation device [ (D A T), 690.700a, 710: Comparison circuit, 700: Subchannel control block, 720:
AND circuit, 730.740: Real address register, 7
50: j memory control device, 800: I/○ startup command. Figure 2 0. ] Fig. δ Cow Fig. 5 ALE command (registration) Fig. 5 Fig. 5 ALE command (delete) Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 11 Fig. 12 Fig. 13 Fig. 4 - Fig. 15 Fig. 16 Figure

Claims (1)

[Claims] 1. In a virtual computer system equipped with a control program that runs multiple operating systems simultaneously,
A registration table is provided in the I/O processor in which one or more identifiers and upper and lower limit addresses that define the area of the main storage device corresponding to the identifiers are registered, and a , by notifying the virtual machine identifier identified by the control program and the upper and lower limit addresses that define the contiguous area of the main storage of the virtual machine, the I/O processor stores the received identifier and upper and lower limit addresses in the registration table. When the registration table is full, the I/O processor sends a message to that effect to the CPU.
A virtual computer system characterized by notifying. 2. The virtual machine system according to claim 1, wherein a lower limit address and the size of the main memory of the virtual machine are used instead of the upper and lower limit addresses. 3. When the above registration table is full, the I/O from the CPU
Claim 1, wherein the I/O processor deletes the specified virtual machine identifier entry in the registration table by instructing the O processor to delete the entry. The virtual computer system described. 4. When registering the virtual machine identifier specified by the control program in the registration table, convert the identifier into an identifier that is identified by the hardware, and when the I/O processor starts the input/output device, the I/O processor identifies the upper and lower limit addresses that define the virtual machine and its main storage area using the identifier identified by the hardware,
When executing the CCW group for the input/output device issued by the OS on the virtual machine, the main storage address of the real computer is obtained by adding the lower limit address of the area to the address of the CCW and its data address. A virtual computer system according to claim 1, characterized in that: 5. After obtaining the main memory address of the actual computer by adding the above lower limit address to the relevant part, check whether it exceeds the upper limit address of the pair, and if it does, send I/O to the CPU side. 5. The virtual computer system according to claim 4, wherein an abnormal termination interrupt is generated. 6. The virtual computer system according to claim 4, wherein the lower limit address and the main memory size of the virtual machine are used instead of the upper and lower limit addresses. 7. When executing the CCW, it is checked whether the address of the CCW and its data address exceed the main memory size of the VM, and if the size does not exceed the size, a lower limit address is added. The virtual computer system described in Section 1. 8. The virtual machine according to claim 1, 3, or 4, wherein the virtual machine identifier is used in place of an area identifier as a main storage device of the virtual machine. system. 9. In a virtual computer system equipped with a control program that runs multiple operating systems simultaneously,
When the control program starts the virtual machine by providing a means for converting the virtual machine identifier identified by the control program into a virtual machine identifier identified by the hardware of the real computer and a correspondence table that holds the correspondence result after the conversion. , when registering the correspondence results in the conversion table, if the correspondence table is full, select one or more of the already registered correspondences and invalidate the correspondence;
A virtual computer system characterized by enabling new correspondence. 10. A patent claim characterized in that, after converting the area identifier identified by the control program into the area identifier identified by the hardware of the actual computer, the converted correspondence result is registered in the identifier correspondence registration table. 9. The virtual computer system according to item 9.