JPS6224969Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a detection circuit used in a receiver for measuring the strength of an electric field in which the strength of the electric field to be measured changes over a wide range, such as in mobile radio communications. More specifically, the detection input of an appropriate level is extracted from the output of the intermediate frequency amplification section according to the input signal strength of such a receiver, and the detected voltage obtained by envelope detection is used to generate the electric field. This relates to a detection circuit used in electric field detectors that detect (intensity).

In conventional electric field detectors, an appropriate level of output is obtained from the receiver's intermediate frequency amplification section through capacitor coupling, etc., and envelope detection is performed using a voltage doubler rectifier or half-wave rectifier using semiconductor diodes. . However, in this circuit, if the input voltage of the detector does not exceed the forward voltage (V _f ) of the diode (forward voltage is the positive voltage at which the detection current begins to flow, and is also called the threshold voltage or offset voltage), the detection output will be It is zero and does not work. Therefore, the detection voltage range is narrow. Furthermore, since the wave detector becomes a load on the input side amplifier, there is a drawback that the gain of the amplifier is also reduced by the input impedance of the wave detector. Furthermore, the detected output voltage is generally input to a voltage comparison circuit (comparator) and compared with a standard voltage (variable) to determine the level.
(V), the voltage input to the comparator after detection needs to be a considerably large value, and the disadvantage is that the detection range becomes increasingly narrow.

In the circuit of the present invention, an appropriate positive bias voltage is applied to the detection diode in advance to cancel out the forward voltage (V _f ) to widen the detection range, and at the same time, an appropriate voltage is applied to the detector output in advance in addition to the detection output. The feature is that the operation of the comparator is facilitated in this case, and will be explained in detail below.

FIGS. 1 and 2 are detection circuit diagrams that are the basis of the present invention, and FIG. 3 is a diagram showing an example of the configuration of a detection circuit implementing the present invention. (The components below the comparator are omitted from the diagram). In these figures, 1 is an intermediate frequency amplification section in the receiver or receiving section, 2 is a buffer amplifier (emitter follower) using a collector grounding circuit, 3, 3a, 3b are detectors (diodes), and 4
5 is a smoothing circuit, and 5 is an output terminal to the comparator. An appropriate output (generally the final stage or a stage close to this) of the intermediate frequency amplification section 1 is applied to the collector grounded circuit 2 which is the input of the detector. As is well known, the input impedance of the common collector circuit is large and the output impedance is low.
When the voltage is applied to a parallel circuit of a resistor R and a capacitor C of an appropriate size through a parallel circuit of a resistor R and a capacitor C, the voltage across R and C becomes the detected output. The detection output is used, for example, to determine the electric field level by inputting it into a comparator and comparing it with a reference voltage, but the bias voltage required for the comparator is determined by the fixed bias resistor R ₁ of the collector grounding circuit 2. is shown in Figure 1. Further, FIG. 2 shows a circuit that obtains a bias voltage using the DC voltage of an intermediate frequency amplification section.

The present invention further expands the detection range based on these circuits, and a specific example of the circuit is shown in FIG. That is, for example, two sets of detection circuits as shown in FIG. To synthesize the output of 3b, a high resistance R ₁ is connected in series with each diode D ₁ and D ₂ , and a common load is a resistance R ₂ and a capacitor C _2.
Commonly connected to parallel circuits. The voltage across this parallel circuit becomes the detected output and is supplied to the comparator. It goes without saying that these circuit elements R ₁ , R ₂ , C ₁ , C _{2 ,} etc. are selected to have optimal values for the detection characteristics.

Next, the effects of the circuit of the present invention will be explained in comparison with conventional circuits. FIG. 4 is a diagram of an example of a conventional detection circuit used to widen the detection range (referred to as detection dynamics range), and FIG. 5 is a diagram of a detection circuit according to the present invention. From these figures, the detection (output) voltage V _p in the case of the conventional method for the first stage is V _p = R ₂ /R ₁ + R ₂ (V _i1 - V _f )...(1) Invented method (Fig. 5) ), the detected voltage is V _p =R ₂ /R ₁ +R ₂ (V ₁ +V _i1 −V _f )...(2) where V _i1 and V _i2 are the output voltages of each stage of the intermediate frequency amplification section , V _f is the forward voltage of the detector diode, and V ₁ is the fixed bias voltage of the diode by the common collector circuit.

Now, as mentioned above, since R ₁ is selected to be much larger than R ₂ , the detector side viewed from the detection output (V _p ) side is considered to be a constant current source, so the composite detection output voltage when two stages are connected. is the sum of the output voltages of each stage. Therefore, in the case of Fig. 4, equation (1) becomes V _p = R ₂ /R ₁ + R ₂ {(V _i1 - V _f ) + (V _i2 - V _f )}...(3), and the present invention's formula In the case of Fig. 5, from equation (2), it is expressed as V _p = R ₂ /R ₁ +R ₂ {(V ₁ +V _i1 −V _f ) +(V ₁ +V _i2 −V _f )} ...(4) . (The fixed bias voltage V ₂ of the diode D ₂ is assumed to be V ₂ = V ₁ for convenience.) Figure 6 is a characteristic comparison diagram of the inventive detector circuit and the conventional detector circuit, and Figure 6 A shows the output. When the gain of the amplifier is the same, B ₁ shows the detection characteristics according to equation (1), and A ₁ shows the input and output characteristics according to equation (2). Also, Figure 6B is a characteristic comparison diagram of the two-stage detection circuit, where A ₁ and B ₁ are as in Figure A, and A ₂ and B ₂ are as shown in Figure A.
Since the characteristics are obtained by adding the detection characteristics of the previous stage to A ₁ and B ₁ , the combined characteristics of B ₁ and B ₂ are shown in equation (3), and the combined characteristics of A ₁ and A ₂ are shown in equation (4). There is.

Next, the operation of the detection circuit and the effect of the circuit of the present invention will be explained in more detail using these characteristics.

First, if you compare Figure 5 according to the present invention with the conventional Figure 4, it will be clear that in the present invention, (a) instead of extracting a part of the output of the intermediate frequency amplifier and directly rectifying it with a diode, Since the output is taken out using an emitter follower (collector grounded) circuit with high impedance and low output impedance, the load effect on the amplifier is small.
When the input voltage of the emitter follower is at a high level, the input voltage of the emitter follower reaches a higher level than that of the conventional type, and detection is possible from the low level output of the amplifier until it reaches the saturated output. On the other hand, in the conventional diode load circuit as shown in FIG. 4, R and C of the smoothing circuit cannot be ignored, and the maximum detection output voltage becomes low due to the load effect. However, since the output impedance of the emitter follower is low, there is no change due to R and C of the smoothing circuit.

(b) By passing a fixed bias DC current through the detection diodes _D1 , _D2 , etc., it is possible to detect AC voltages that are lower than the forward voltage of the diodes, thereby expanding the dynamic range of the detector. In the conventional circuit, as shown in FIG. 6, the portion up to the input V _f is not detected, so the dynamic range is narrow.

(c) Signal processing of the detector output is facilitated by applying an appropriate bias voltage to the signal output of the emitter follower circuit.

There are effects such as Next, the operation of the circuit will be explained.

First, when the detector has one stage as shown in Fig. 2, the detection characteristics of the conventional diode detection circuit and the circuit of the present invention are shown as B in Fig. 6A, assuming that the gain of the amplifier that takes out the detector input is the same. ₁ and A ₁ characteristics. This characteristic represents the characteristic between the input voltage V _i and the detected output voltage V _p , where A ₁ is the characteristic of the circuit of the present invention,
B ₁ is a characteristic of a conventional diode detection circuit.
In the B ₁ characteristic, the output V _p is zero until the input voltage exceeds the forward voltage V _f , whereas in the A ₁ characteristic, the bias voltage cancels V _f and the detected output is increased from the minute input to before its saturated output. It can be generated linearly. Although V _f is about 0.6V, it has a large effect on ICs and transistor circuits with low power supply voltages. In figure A, DR _A and DR _B represent the output dynamic range, and V _is the saturation level, respectively. In general, DR _A > DR _B.

Next, as shown in Figures 4 and 5, there are multiple stages (here, 2 stages).
The following describes the detection circuit in the following stage. In the circuit shown in Figure 5, the output of each stage detector is operated as a current source by the resistor R ₁ (R ₁ ≫ R ₂ ), which has low impedance and is connected in series with the diodes D ₁ and D ₂ as described above. Ru. Therefore, the current flowing through the common load _R2 is the sum of the detected currents corresponding to the output voltages from each stage, and the detected output 5 is the sum of the detected voltages from each stage. Therefore, the detection output reaches the saturation voltage first in the final stage detector, and its characteristics are as shown in _A1 in FIG. 6A. In addition, the detection output from the pre-stage amplifier begins to generate slightly before the final stage reaches its saturation voltage V _is , but while the pre-stage is generating a detected voltage proportional to the input voltage, the output from the post-stage detector remains constant. It can only output voltage of . Therefore, the composite characteristics of the two-stage detector are A ₁ and A ₂ in Figure 6B.
becomes the composite straight line. Note that B ₁ and B ₂ in Fig. 6B are the detection characteristics obtained by adding the latter stage and the previous stage in the case of conventional diodes only (Fig. 4), but the composite characteristic is the sum of the outputs of each stage detection circuit. This is the case assuming that.

In order to make the composite detection characteristics A ₁ and A ₂ or B ₁ and B ₂ a continuous straight line, it is necessary to make some adjustments to the gain of the amplifier in each stage or the detection input voltage by actual measurement. At this time, in the conventional circuit, compared to the circuit of the present invention, it is necessary to lower the gain and perform synthesis, as is clear from the characteristics shown in Figure 6B, and the dynamic range DR _B2 of the detection input voltage is even greater than that of the circuit of the present invention. It gets narrower. Even if we allow some discontinuities in the composite characteristics as shown in Figure 6B, B ₁ and
The detector output of B ₂ is reduced by at least V ₀₁ corresponding to the forward voltage V _f per stage, and the input dynamic range is narrowed by 2 V _f in the two-stage combination. In a multi-stage composite detection circuit as in this example, the output dynamic range can be made considerably larger than that of a conventional diode detection circuit as long as the number of stages is large and the composite detection output increases.

As mentioned above, the detection circuit of the present invention has the remarkable feature of wide detection range, but in addition, the input impedance is high because the collector is grounded, so it has almost no effect on the load impedance of the intermediate frequency amplifier, and the comparator input It has advantages such as not requiring a separate bias, and has been used in electric field detectors and the like with excellent effects.

[Brief explanation of the drawing]

Figures 1 and 2 are circuit diagrams that are the basis of the present invention, Figures 3 and 5 are configuration examples of a detection circuit according to the present invention, and Figure 4 is a conventional detection circuit configuration for expanding the detection range. 6 are characteristic comparison diagrams of the detection circuit of the present invention and a conventional circuit. Figure A is a comparison diagram of characteristics per stage, and Figure B is a comparison diagram of characteristics of a two-stage detection circuit. 1... Intermediate frequency amplification section, 2... Collector grounding circuit, 3, 3a, 3b... Detection diode, 4...
Smoothing circuit, 5... Output terminal to comparator.

Claims (1)

[Scope of utility model registration request] A portion of the output from each successive stage with different output levels of the receiver intermediate frequency amplification section is taken out and used as the base side input, and a bias voltage is generated between the emitter and ground to zero the forward voltage of the detection diode. A common load for multiple stages consisting of a parallel circuit of a resistor R ₂ and a capacitor C ₂ with one end grounded, and a common collector transistor for each stage (emitter follower) to which a bias resistor is connected. A detection diode connected between the emitter-to-ground resistance and the common load, and a resistance several times larger than the load resistance _R2 .
1. A detection circuit comprising a series circuit of _R1 , the detection circuit being configured such that the outputs of the detection diodes in each stage are added and combined to the common load.