JPS62245485A - Multilevel image logical arithmetic circuit - Google Patents

Abstract

PURPOSE:To use one 3X3 logic circuit and one multiplexer and to simplify a multilevel image logical arithmetic circuit by providing a means which sorts density based on a threshold value, codes it into a binary value, and sends out patterns corresponding to 3X3 windows. CONSTITUTION:Eight-bit data indicating density of each dot is stored from a terminal A. Then, (8X9)-bit data sent out of a line buffer 1 is inputted to a pseudo binary-coding circuit which extracts binary data by using parameters of an upper-limit and a lower-limit threshold value and sorting results based on those threshold values are sent out as 3X3 window patterns to a 3X3 logic circuit 5. Those results are compared by the 3X3 logic circuit 5 with data in a ROM and it is decided whether the comparison result or original data from the line buffer 1 is sent out. A multiplexer 3 switches a circuit based on the decision result to send out the comparison result of the ROM or original data to a terminal B.

Description

[Detailed Description of the Invention] [Summary] When performing an N×N logical operation on multivalued image data that expresses the density using M bits, the density within a given threshold is detected and binarized, and the N×N Pseudo 2 sent as N window pattern
The value converting circuit simplifies the N×N logic operation circuit and enables pipeline processing to perform N×N logic operations at high speed to extract isodensity lines, edges, and the like.

(Industrial Field of Application) The present invention relates to a simple multi-value image logic operation circuit that performs N×N logic operations on input multi-value image data at high speed through pipeline processing to extract isodensity lines, edges, etc.

For example, in an image captured by a television camera, the density of one point is detected at, for example, 256 gradations, and is input to an image processing device as 8-bit digital data. When extracting isodensity lines, edges, etc. from this multivalued image data,
It is generally known to perform 3x3 logical operations using 3x3 dots as windows from adjacent dots constituting a pixel, but it is desirable that this circuit configuration be simple and high-speed.

[Conventional technology]

FIG. 7 is a block diagram showing an example of a conventional multivalued image logic operation circuit.

For example, 8-bit data representing density enters the line buffer 1 for each dot from terminal A, and the 8-bit data for each dot is stored as matrix data constituting a 3.times.3 dot window. The 8x9 bit data sent from line buffer 1 is sent to 3x3 logic circuit 2.2',
1.times.9 dots are entered in each of -- and --, and compared with the data in the ROM.

The result compared with this ROM is multiplexer 3.3°
, -, respectively, and sends the ROM comparison result, or
The original data sent from the line buffer 1 is sent out to the terminal B by switching the multiplexer 3.3°, - based on the determination of the 3×3 logic circuit 2.2', -.

[Problem that the invention seeks to solve]

As mentioned above, conventionally, the number of 3.times.3 logic circuits and multiplexers is required in accordance with the number of bits to be processed in parallel for each dot constituting a pixel, and for 8 bits, 8 of each are required.

Therefore, there is a problem that the multivalued image logical operation circuit is complicated and expensive.

In view of these problems, the present invention provides means for selecting and binarizing the density from the threshold value and transmitting a pattern corresponding to a 3x3 window, and combining a 3x3 logic circuit and a multiplexer into one. This is what I did.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

For example, 8-bit data enters the line buffer 1 for each dot from terminal A, and 8-bit data representing the density of each dot is stored as matrix data constituting a 3.times.3 dot window.

The 8x9 bit data sent from the line buffer 1 enters a pseudo-binarization circuit 4 that extracts binary data based on the upper and lower threshold parameters, and the results selected using the thresholds are 3x As the window pattern of 3, 3×3
The signal is sent to the logic circuit 5.

This result is compared with the data in the ROM in the 3×3 logic circuit 5, and it is determined whether the comparison result should be sent out or the original data sent out from the line buffer 1 should be sent out. The multiplexer 3 is configured to send the ROM comparison result or original data to the terminal B by switching circuits based on this determination result.

[Effect]

With the above configuration, when performing a 3×3 logical operation on multivalued image data, the artificial binarization circuit uses the upper and lower limits to be binarized as parameters, that is, the threshold value, to convert the multivalued image data into Select and convert to binary data, 3×3
By using the window pattern, the ROM can easily extract contour lines, edges, etc., and label data representing the directional component of density can also be obtained from the ROM.

〔Example〕

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of the pseudo-binarization circuit 4 of FIG. 1. In explaining the operation of Fig. 2, line buffer 1
A detailed block diagram of the 3×3 logic circuit 5 is shown in FIG. 3, and FIG. 4 shows a detailed block diagram of the 3×3 logic circuit 5.

In FIG. 3, a pixel imaged by, for example, a television camera enters from terminal A, and from 8-bit data representing the density of the first dot of the -th row on the scanning line, 8-bit data of the next dot is sent to the latch circuit. 6.7, the line buffer 8, the launch circuit 9.10, the line buffer 11, the latch circuit 12, the latch circuit 13, and so on. Then, the 8 bits of the next dot are latched into the latch circuit 12.

When the 8 bits of the third dot are stored in the line buffer 11 and sent to the terminal g, the 8 bits of the latch circuits 12 and 13 are also simultaneously sent to the terminals i, respectively.

At this time, the 8 bits of the first dot in the second row on the scanning line are latched by the launch circuit 10 in the same manner as described above, the 8 bits of the next dot are latched by the latch circuit 9, and the 8 bits of the third dot are latched by the latch circuit 9.
The bits are stored in the line buffer 8 and are simultaneously connected to the terminal d.
The 8 bits of latch circuits 9 and 10 are also sent to terminals e and f, respectively.

Similarly, at this time, the 8 bits of the first dot in the third row on the scanning line are latched by the latch circuit 7, the 8 bits of the next dot are latched by the latch circuit 6, and the 8 bits of the third dot are latched simultaneously. It is sent to terminal a, and the latch circuit 6.
The 8 bits of 7 are also sent to terminals A and C, respectively.

When the 8 bits of the 4th dot in the 1st to 3rd rows enter from terminal A, the 8 bits of the first dot in the 1st to 3rd rows are pushed out and disappear, and the 8 bits of the 4th dot in the 1st to 3rd rows are pushed out and disappear. 3×
3 matrix data are formed.

In this way, the 3×3 matrix data is sent to the pseudo-binarization circuit 4 shown in FIG. 2, and at the same time, the data at the terminal e is sent to the multiplexer 3 shown in FIG.

In the pseudo-binarization circuit 4 shown in FIG. 2, a threshold value indicating an upper limit value is set in a register 14, and a threshold value indicating a lower limit value is set in a register 15, for example, in order to obtain an isodensity line.

The output of terminal a of line buffer l is input from terminal a,
The 8-bit data is passed through the comparator 16 to the upper threshold and the comparator 1
7 is compared with the lower threshold, and if it is within the upper and lower thresholds,
The AND circuit 22 sends "l" to the terminal a', and sends "O" if the threshold value is not met. Enter terminals c, d 8
Bit data is also compared in the same way, and terminals b', c',
Sends “1” or “0” to “d”.

The output of terminal e of line buffer 1 is input from terminal e,
The 8-bit data is passed to the comparator 18 and the upper threshold value, and the comparator 1
9 is compared with the lower threshold, and if it is within the upper and lower thresholds,
The AND circuit 23 sends "l" to the terminal e', and sends "O" if the threshold value is not met. 8 entering terminals r, g, h
The bit data is also compared in the same way, and the terminals f', g',
Send "1" or "0" to h'.

The output of terminal i of line buffer l is input from terminal i,
The 8-bit data is passed to the comparator 20 and the upper threshold value, and the comparator 2
1 is compared with the lower threshold, and if it is within the upper and lower thresholds,
The AND circuit 24 sends out a ``1'' to the terminal i', and sends out a 0 if the threshold value is not met.

The 3×3 logic circuit 5 shown in FIG. 4 is constituted by a ROM 25. Labels are stored in advance in the ROM 25 at addresses corresponding to 3×3 windows, and 9-bit inputs input from terminals a'' to i'' are stored in the ROM 25 in advance. The data is compared with a 3×3 window pattern determined by whether each terminal is "1" or "O", and the result is sent to the multiplexer 3 as 8-bit data.

If you want to send out the comparison result of ROM 25 at the same time, send a switching signal to multiplexer 3 and send the comparison result of ROM 25 to terminal B. If you want to send out the original data, do not send out the switching signal to multiplexer 3, and send out the comparison result of ROM 25 to terminal B. 3
sends the data at terminal e to terminal B.

FIG. 5 is a diagram illustrating isodensity line extraction.

When the density is represented by 256 gradations, if the upper limit density is U and the lower limit density is L as shown in Fig. 5(a), then the threshold value U and the density curve are L is given. Therefore, within the range of these threshold values U and L, "l" is transmitted as explained in FIG. 2, and the 3×3 shown in FIG.
The logic circuit 5 can easily extract the equal concentration band as shown by the diagonal lines in FIG. 5(e).

FIG. 6 is a diagram illustrating an example of edge extraction.

If the density is expressed in 256 gradations, then the lower limit of the density to be detected as an edge is L, as shown in Fig. 6 (al), the upper limit is 255. Therefore, Fig. 6 (1)) Threshold values U and L are given to the density curve as shown in FIG.

As shown in FIG. 6(d), the 3×3 logic circuit 5 shown in FIG. 1 sends out the label code top, right, bottom, and left representing the directional components using patterns ■ to ■ corresponding to the 3×3 window. do. By displaying this label code along the edge as shown in FIG. 6(C), subsequent processing becomes easier.

(Effects of the Invention) As explained above, the present invention facilitates the extraction of isodensity lines, edges, etc. by the way threshold values are given, and 3x3 logical operations can be performed easily, allowing for fast and simple multivalued image logical operations. We can provide the circuit.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention, Figure 3 is a detailed block diagram of a line buffer, and Figure 4 is a detailed block diagram of a 3x3 logic circuit. , FIG. 5 is a diagram illustrating an example of isodensity line extraction, FIG. 6 is a diagram illustrating an example of edge extraction, and FIG. 7 is a block diagram illustrating an example of a conventional multivalued image logic operation circuit. In the figure, ■ is a line buffer, 2.5 is a 3x3 logic circuit, 3 is a multiplexer, 4 is a pseudo-binarization circuit, 6.7, 9
．． 10.12.13 is a latch circuit, 8.11 is a line buffer, 14.15 is a register, 16 to 21 are comparators,
22 to 24 are AND circuits, and 25 is a ROM. U4〉Ba°TsufyaOwafEJA°mouth・72Figure 1-3
Figure 4 Figure 7t (C) (b) LP-Power [9 Tadasu 4 Mountain day A Ita・1 to Sanskrit-〇月Jro Figure 5
Fig.

Claims (1)

[Claims] In a multi-valued image logical operation circuit that performs N×N logical operations on multi-valued image data representing density in M bits, the density within a given threshold value is detected and binarized. ×
A pseudo-binarization means (4) is provided which sends out an N window pattern, and an N×N logical operation is performed based on the N×N window pattern sent out by the pseudo-binarization means (4). Multivalued image logic operation circuit.