JPS6224498A - Memory read system - Google Patents

Abstract

PURPOSE:To prevent erroneous read due to an electric noise without reducing the bit density by reading information from the same cell plural times continuously and comparing these information to determine output information. CONSTITUTION:Information read to a node N1 is taken into a latch circuit 1 by a control clock phi1 and is latched. Information is read again from the same cell, and read information is latched in a latch circuit 2 by a control clock phi2, and information read from the same cell is latched in a latch circuit 3 by a control clock phi3 similarly. Three pieces of latched information are subjected to majority decision by a majority decision circuit 4, and the result is read out to the external through an output buffer 5. The majority decision circuit 4 consists of 3 AND circuits A1-A3 and one OR circuit OR and outputs the same information as information inputted to the majority of the first - third input terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory read method that enables read operations with high reliability in read-only memories (ROM memories) and the like.

[Conventional technology]

When performing a read operation in a conventional ROM, information stored in a designated cell is extracted onto a bit line,
It was read out to the outside via a multiplexer, amplifier, and output sofa. A read operation of a ROM memory is a non-destructive operation, and the read operation does not destroy the information stored in the cells. Also, the stored information is stored in RAM.
Unlike memory, it will not be lost due to factors such as noise current.

Therefore, the information stored in the cell itself will not be lost, but if the amplifier or latch circuit malfunctions due to various electrical noises during the read operation, there is a risk that incorrect information will be read (hereinafter referred to as , erroneous reading). In particular, when the information stored in cells is multivalued to increase density, the amplitude of the signal input to the amplifier becomes smaller, making it more likely to malfunction.

As one method for preventing such malfunctions, a multiple cell 1-bit method is known. In this method, the same information is stored in a plurality of cells, and when reading out the information from each cell, a majority vote is taken to determine the output. Therefore, erroneous reading will not occur unless the information from the majority of cells is incorrect.

Therefore, although this method is effective in preventing erroneous reading, it has the problem that the bit density (storage capacity/chip size) is greatly reduced because a plurality of cells must be allocated to one bit.

Another known method is to add information for error detection and correction to stored information. In this case as well, when attempting to detect and correct errors in a large amount of read information, the amount of necessary error detection and correction information increases, resulting in a significant reduction in bit density. Furthermore, since a process of adding information for error detection and correction is added when designing the ROM, there is a drawback that the design of the ROM becomes more complicated.

[Problem that the invention seeks to solve]

Therefore, in the present invention, the problem to be solved is to prevent erroneous reading caused by electrical noise during memory reading without reducing the bit density or complicating the memory design. . It is therefore an object of the invention to provide a memory reading scheme that makes the above possible.

[Means and operations for solving the problem] In order to achieve the above object, the present invention automatically reads information from the same cell multiple times consecutively within the memory and compares the results. The output information is determined, and this is a feature.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As seen in the figure, the readout method according to the present invention includes three latch circuits 1 to 3, 4 majority circuits, 4 control clocks φ1 to φ4, and an output buffer sofa (if the control terminal is at a high level, the input signal is amplified). (5) is used to connect the input terminals of latch circuits 1 to 3 to each other to form a node N1, and also to connect the input terminals of latch circuits 1 to 3 to form node N1. Connect control clocks φ1 to φ3 to each control terminal of 3, respectively,
The output terminals of the RAS and CH circuits 1 to 3 are connected to the first terminal of the majority circuit 4.
- connect to the third input terminal, connect the output terminal of the majority circuit 4 to the input terminal of the output vanofer 5, and connect the control clock φ4 to the control terminal of the output vanofer 5.

The majority circuit 4 includes three AND circuits A as shown in the figure.
1 to A3 and one OR circuit OR, and outputs the same information as the information input to the majority (2 in this example) of its first to third input terminals.

FIG. 2 is an operation timing diagram of each part signal in the circuit shown in FIG. 1.

The circuit operation will be explained with reference to FIGS. 1 and 2.

The read operation starts when an external clock such as a chip enable clock rises in the case of a synchronous type, or by internally detecting a change in the address signal in the case of an asynchronous type.

First, the basic clock φ0 generated inside the chip (this clock corresponds to the chip select clock used in conventional ROM, and is not shown in Figure 1) rises to activate the circuit, and the specified The information of the cell (not shown) is read out to the node N1 via a bit line, multiplexer, and amplifier (not shown).

This information is taken in and latched by the latch circuit 1 by setting the control clock φ1 to a high level. Next, the basic clock φ0 falls for a moment and then rises again, and the read operation from the same cell is performed again.
Read information is latched into latch circuit 2 by control clock φ2.

Furthermore, the same read operation is repeated once again, and the information read from the same cell is latched into the latch circuit 3 by the control clock φ3.

Next, the majority circuit 4 takes a majority vote on the three latched information, and reads the result to the outside via the output buffer 5. Note that in the output buffer 5, the control clock φ4 is at a low level and the output terminal is kept in a high impedance state from the start of the read operation until a majority vote is taken for the continuously read information. This control clock φ4 is the control clock φ1. This can be easily generated by using an R-S flip-flop circuit that inputs φ3.

In the read method of this embodiment, the same cell is repeatedly read three times, and output information is determined by taking a majority vote of the obtained results. For this reason, it is extremely effective in preventing erroneous reading caused by temporary noise such as soft errors, and since it is 1 bit/1 cell, the bit density can be significantly reduced as in the multi-cell 1-bit method. Nor. In this embodiment, the number of reads is set to three, but if the number of reads is increased, the access time will be longer (although the reliability can be increased accordingly).

Further, in this embodiment, the number of times of reading is set to an odd number of three times, but if there is a certain tendency to read information incorrectly, the number of times of reading may be an even number.

For example, most misreads occur when information “0” is replaced by information “1”.
'', if the same number of rOJ and rlJ is obtained as a result of majority voting, it may be configured such that ``0'' is determined as the read information. In this way, advantages such as being able to shorten the read time can be obtained without substantially losing the high reliability obtained by using this embodiment.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

The embodiment shown in the figure includes two latch circuits 1゜2, an OR circuit OR1, an exclusive NOR circuit (XNOR), an inverter NOT, an output sofa 5.2 transistors Ql,
Q2, control clock φATD, φATDB (φA
complementary signal of TD), φ5. Using φ6, input terminal of latch circuit 1, input terminal of output sofa 5, inverter NO.
The input terminal of T and the source of transistor Q1 are interconnected to form a node N1, the output terminal of inverter NOT is connected to the sources of transistor Q2, and the drain of transistor Q1 and the drain of transistor Q2 are connected to latch circuit 2.
The control clock φATD is connected to the gate of the transistor Q1, the control clock φATDB is input to the first input terminal of the OR circuit ORI and the gate of the transistor Q2, and the control clock φATDB is input to the control terminal of the latch circuit 1. Input the control clock φ5, input the control clock φ6 to the second input terminal of the OR circuit OR, connect the output terminal of the OR circuit 'OR to the control terminal of the latch circuit 2, and connect the output terminal of the latch circuit 1゜2. are respectively connected to the two input terminals of the exclusive NOR circuit XNOR, and the output terminal of the exclusive NOR circuit XNOR circuit and the control terminal of the output buffer 5 are connected to the node N.
It is set at 2.

FIG. 4 is a timing diagram of various signals in the circuit shown in FIG. 3.

The circuit operation will be explained with reference to FIGS. 3 and 4.

The read operation starts when a change in the address signal is detected inside a chip (not shown) and the control clock φATD changes from high level to low level. When the control clock φATD goes low, the basic clock φO goes high, the internal circuit is activated, and the information of the designated cell is read out to the node N1 via a bit line, multiplexer, and amplifier (not shown). . This information is latched into the latch circuit 1 by the control clock φ5.

Also, at this time, since the control clock φATDB is at a high level, the transistor Q2 becomes conductive, and the control clock φAT
Since D is at a low level, transistor Q1 is cut off. Therefore, a signal complementary to that in latch circuit 1 is written into latch circuit 2 via inverter NOT and latched. Therefore, the node N2 (the output terminal of the exclusive NOR circuit XNOR) becomes a low level, and the output terminal of the output buffer 5 becomes a high impedance state.

Next, the basic clock φ0 falls for a while and then rises again, so that information is successively output from the same cell again, and this information is latched into the latch circuit 2 by the control clock φ6. The information latched in latch circuit 1 last time and the information latched in latch circuit 2 this time are connected to exclusive NOR circuit XNOR.
If they are equal, the node N2 becomes high level, and the cell information is read out via the output buffer 5. Furthermore, if the information latched in these latch circuits 1 and 2 are not equal, the node N2 remains at a low level,
The output terminal of output buffer 5 is kept in a high impedance state.

Then, reading from the same cell is performed once again, and the result is latched in the latch circuit 1 by the control clock φ5, and compared with the information latched in the latch circuit 2 from the previous time by the exclusive NOR circuit XNOR.

In this manner, reading from the same cell is repeated until the information in the latch circuits 1 and 2 match, and at the time they match, the cell information is read out to the outside via the output buffer 5. In FIG. 4, the information read out first and the information read out the second time are different, the information read out the second time and the information read out the third time are the same, and the information output S from the output buffer 5 is different.
This example shows the output case.

In this manner, in this embodiment, information is read to the outside only when the information read from the same cell is the same twice in a row.

Therefore, it is extremely effective in preventing malfunctions caused by temporary noise such as soft errors.
Since it is one cell, there is no need to reduce the bit density as in the case of multiple cells with one bit.

The basic clock φ0 used in this embodiment is used as a basic clock to repeat the read operation internally, and after confirming that the information latched in the latch circuits 1 and 2 is equal, It is fixed at a low level until a read operation is started. In order to generate the basic clock φ0 having such operation timing, a circuit as shown in FIG. 5, for example, may be used.

In this circuit, a NAND circuit NAND, two inverters N
0TE, N0T2.2 transistors Q3. Q4, the delay circuit 6, the control clock φATD, and the node voltage VN2 of the node N2 in FIG.
A control clock φATD and a node voltage VN2 are connected to the two input terminals of the NAND circuit NAND, and the output terminal of the NAND circuit NAND is connected to the gate of the transistor Q3 and the input terminal of the first inverter N0T1. is connected to the gate of the transistor Q4, the source of the transistor Q3 is connected to the output terminal of the second inverter N0T2, the drain of the transistor Q3 is connected to one terminal of the delay circuit 6, and the drain of the transistor Q4 is connected to the output terminal of the second inverter N0T2. The input terminal of the second inverter N0T2 and the other terminal of the delay circuit 6 are interconnected to form an output terminal.

The operating principle will be described. From the start of the read operation until the information latched in the latch circuits 1 and 2 match,
As one of the control clock φATD and the node voltage VN2 is at a low level as shown in FIG. 4, the transistor Q3 becomes conductive, and the transistor Q3, the delay circuit 6,
A loop is formed by the second inverter N0T2. Due to this loop, the output terminal outputs a low level at a constant cycle.

A clock φO that repeats high level is obtained.

Furthermore, after the information latched in the latch circuits 1 and 2 match and the information is read out, the control clock φAT
Since the node voltages D and VN2 both become high level, the transistor Q3 is cut off and this loop is severed, and the transistor Q4 becomes conductive, so that the basic clock φO is fixed at the low level.

〔Effect of the invention〕

As can be seen from the above explanation, if the readout method according to the present invention is used, it is possible to eliminate misreading caused by temporary noise such as soft errors without reducing the dot density by simply adding a small-scale circuit to the ROM memory. This has the advantage that readout can be prevented and extremely reliable readout operations can be performed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram showing another embodiment of the present invention; FIG. 4 is a waveform diagram showing the operation timing of each part signal in the circuit of FIG. 3; FIG. 5 is a circuit diagram showing an example of a basic clock generating circuit used in the embodiment shown in FIG. 3. Explanation of symbols 1 to 3...Latch circuit, 4...Majority circuit, 5...
・Output sofa, 6...Delay circuit agent Patent attorney Akio Namiki Agent Patent attorney Kiyoshi Matsuzakioln δ≠ −(It--8-3 ÷ 6 years September)

Claims (1)

[Claims] 1) When reading information stored in a cell in a read-only memory, N latch circuits (N is an odd number) and one majority logic circuit are used to read out the information stored in the cell. Information is read out N times from the same cell continuously, and the nth (N≧n≧
The reading result of 1) is taken into the n-th latch circuit and latched, and the output information is determined by taking a majority vote of the information latched in the N latch circuits by the majority logic circuit. memory read method. 2) When reading out information stored in a cell in a read-only memory, I latch circuits and one comparator circuit are used to read out information from the same cell in succession I times within the memory. The read result of the th (I≧i≧1) is
The comparator circuit compares all the information latched in the I latch circuits, and when they all match, the information is read out to the outside, and when they do not match, the information is Repeat the read operation for the jth (j = i + I × k, and I≧i≧1, and = 1, 2
,...) is fetched and latched by the i-th latch circuit, and the comparator circuit confirms that all the information latched in the I latch circuits matches. A memory read method characterized by reading out externally.