JPS62241423A - High-speed clamping circuit - Google Patents

High-speed clamping circuit

Info

Publication number
JPS62241423A
JPS62241423A JP61084119A JP8411986A JPS62241423A JP S62241423 A JPS62241423 A JP S62241423A JP 61084119 A JP61084119 A JP 61084119A JP 8411986 A JP8411986 A JP 8411986A JP S62241423 A JPS62241423 A JP S62241423A
Authority
JP
Japan
Prior art keywords
voltage
circuit
current
clamper
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61084119A
Other languages
Japanese (ja)
Inventor
Junjiro Kitano
北野 純二郎
Toshio Hayashi
林 敏夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP61084119A priority Critical patent/JPS62241423A/en
Publication of JPS62241423A publication Critical patent/JPS62241423A/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
  • Interface Circuits In Exchanges (AREA)

Abstract

PURPOSE:To shorten a signal break time based upon the coupling time constant between a high-voltage system circuit and a low-voltage system circuit by constituting the output circuit of the high-voltage system circuit by using a two-way output voltage buffer which has current-source and current-sink ability and providing a two-way voltage clamper to the input of the low-voltage system circuit. CONSTITUTION:Both detection currents obtained by detecting voltages on the B-line and A-line sides of the high-voltage system circuit connected to a telephone set 1 are summed up at the output point of a current mirror 4 and a voltage proportional to the two wire voltages is detected across a resistance R3 and inputted to the two-way output buffer 6 which has the current-source and current-sink ability. The two-way clamper 7 is connected to the input circuit of the low-voltage system circuit composed of an input resistance Rs, a resistance R4, and an operational amplifier 5. In this constitution, the charging/discharging time of coupling capacity Cs is ended within the time of the time constant determined by the coupling capacitor Cs, the output resistance of the buffer 6, and the on resistance of the clamper 7 against large-amplitude transient variation in DC level at the time of the hook operation of the telephone set, and consequently both said resistances are set much smaller than the resistance Rs to shorten the time of a break of a signal due to the conduction of the clamper 7.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は電話交換機の加入者回路などの高電圧系回路と
低電圧系回路間の信号インタフェース回路に係)、特に
結合時定数によって生じる過電圧入力の電圧クランプに
好適な高速クランプ回路に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a signal interface circuit between a high-voltage circuit and a low-voltage circuit, such as a subscriber circuit of a telephone exchange, and in particular, to a signal interface circuit for overvoltage input caused by a coupling time constant. This invention relates to a high-speed clamp circuit suitable for voltage clamping.

〔発明の背景〕[Background of the invention]

従来の電話交換機の加入者回路などでは、電話機に通話
電流を供給するために加入者線路に接続される直流給電
回路部分には高電圧電源(V、、 =−aaV )が使
用される一方、信号処理を行う回路部分には低電圧電源
(’CC’III =±5F)が使用されておシ、この
高電圧系回路と低電圧系回路間は容量結合されるのが一
般的である。しかしかかる高電圧系回路の信号成分を容
量結合を介して低電圧系回路に伝達する信号伝達系にお
いて、この結合容量による時定数が大きいと高電圧系回
路の直流レベルの過―変動により一時的に低電圧系回路
の入力が飽和して信号が中断する問題点があう是。
In subscriber circuits of conventional telephone exchanges, a high voltage power supply (V, = -aaV) is used in the DC power supply circuit section that is connected to the subscriber line to supply talking current to telephones. A low voltage power supply ('CC'III = ±5F) is used in the circuit portion that performs signal processing, and the high voltage circuit and the low voltage circuit are generally capacitively coupled. However, in a signal transmission system that transmits signal components from a high-voltage circuit to a low-voltage circuit via capacitive coupling, if the time constant due to this coupling capacitance is large, temporary fluctuations may occur in the DC level of the high-voltage circuit. This is due to the problem that the input of the low voltage circuit is saturated and the signal is interrupted.

なおこの種の電話交換機の加入者回路の信号伝達系の従
来例としては、たとえば昭和58年度電子通信学会総合
全国大会予稿集、 Nu 547に記載の「給電特性可
変形BSH回路LSIの設計」などが挙げられる。
Conventional examples of the signal transmission system of the subscriber circuit of this type of telephone exchange include, for example, "Design of a BSH circuit LSI with variable power supply characteristics" described in Nu 547, Proceedings of the 1981 National Conference of the Institute of Electronics and Communication Engineers, etc. can be mentioned.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上記した従来技術の問題点を解決し、高
電圧系回路と低電圧系回路間の結合時定数による信号中
断時間の短縮をはかる高速クランプ回路を提供するにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed clamp circuit that solves the problems of the prior art described above and reduces the signal interruption time due to the coupling time constant between a high voltage circuit and a low voltage circuit.

〔発明の概要〕[Summary of the invention]

本発明は、高電圧系回路の出力と低電圧系回路の入力を
結合する容量の充放電時間の高速化をはかれば信号中断
時間の短縮がはかれる点に着目して、高電圧系回路の出
力回路を電流ソースと電流シンク能力のある双方向出力
電圧バッファよ多構成し、低電圧系回路の入力に双方向
電圧クランパーを設けることにより、双方向電圧クラン
パーの動作する結合容量の充放電期間における過渡的な
結合時定数を下げて充放電の高速化をはか)、もって信
号中断時間の短縮化をはかるようにした高速クランプ回
路である。
The present invention focuses on the fact that the signal interruption time can be shortened by speeding up the charging and discharging time of the capacitor that connects the output of the high voltage circuit and the input of the low voltage circuit. By configuring the output circuit with multiple bidirectional output voltage buffers with current source and current sink capabilities, and by providing a bidirectional voltage clamper at the input of the low voltage circuit, the charging and discharging period of the coupling capacitor operated by the bidirectional voltage clamper can be reduced. This is a high-speed clamp circuit that aims to reduce the transient coupling time constant of 100 kHz to speed up charging and discharging), thereby shortening the signal interruption time.

〔発明の実施例〕[Embodiments of the invention]

以下に本発明の実施例を第1図ないし第6図により説明
する。
Embodiments of the present invention will be described below with reference to FIGS. 1 to 6.

ア 第1図は本発明による高速クラン−回路の第1の実施例
を示す加入者回路の2線−4線変換部の回路図である。
FIG. 1 is a circuit diagram of a 2-wire to 4-wire conversion section of a subscriber circuit showing a first embodiment of a high-speed crank circuit according to the present invention.

第1図において、1は電話機、2,5.4はカレントミ
ラーA #’1 mAm 。
In FIG. 1, 1 is a telephone, 2, 5.4 is a current mirror A #'1 mAm.

5はオペアンプ、6は双方向出力電圧バッファ。5 is an operational amplifier, and 6 is a bidirectional output voltage buffer.

7は双方向電圧クランパーである。B、Aは各B 、 
A@@の接続点、R1#R1j Ra s Raは抵抗
、Dl # Dl s Dl # Diはダイオード、
Qt、Qtは出カドC。
7 is a bidirectional voltage clamper. B and A are each B,
Connection point of A@@, R1#R1j Ra s Ra is a resistor, Dl # Dl s Dl # Di is a diode,
Qt, Qt is output C.

ランジスタ、へは結合容量、R8は入力抵抗%’BB(
−asV )は高電圧電源、Vcc(5V )、’El
l(−sJ/)は低電圧電源である。第2図(α) 、
 (a)は第1図の各カレントミラー2と5.4の等価
回路図である。第2図(a) 、 (A) において、
QB s (’4 eQw−Qaはトランジスタである
。第2図(a)はPnPトランジスタQs、Qaからな
るP%p形(電流ソーよ ス形)のカレントシラー、第2図(A)は%ハ形トラン
ジスタQm−Q*からなる%p%形(電流シンク形)の
カレントミラーであ)、各入力電流INと同じ出力電流
OUTを出力する。
transistor, to the coupling capacitance, R8 is the input resistance %'BB (
-asV) is a high voltage power supply, Vcc (5V), 'El
l(-sJ/) is a low voltage power supply. Figure 2 (α),
(a) is an equivalent circuit diagram of each current mirror 2 and 5.4 in FIG. 1. In Figures 2(a) and (A),
QB s ('4 eQw-Qa is a transistor. Figure 2 (a) shows the current shiller of P%p type (current source type) consisting of PnP transistors Qs and Qa, and Figure 2 (A) shows the current shiller of %p type (current source type). It is a current mirror of the %p% type (current sink type) made up of half-shaped transistors Qm-Q*, and outputs the same output current OUT as each input current IN.

第1図の電話機1と接続する高電圧系回路のB線側(接
続点B)の電圧は抵抗へとカレントミラー2により検出
され、同じくA線側(接続点A)の電圧は抵抗4とカレ
ントミラー3により検出される。この雨検出電流がカレ
ントミラー4の出力点で加算されて、抵抗島の両端に2
線電圧(接続点A、B間電圧電圧比例した電圧vBが検
出され、双方向出力電圧バッファ60入力電圧ν1とな
る。接続点A、Eは電話機1の接続点のため高電圧電源
V、、=−48Vが用いられるので、電話機10オンフ
ツク(ループオフ)。
The voltage on the B line side (connection point B) of the high voltage circuit connected to the telephone 1 in Fig. 1 is detected by the current mirror 2 to the resistor, and the voltage on the A line side (connection point A) is detected by the resistor 4. It is detected by the current mirror 3. This rain detection current is added at the output point of the current mirror 4, and two
Line voltage (voltage vB proportional to the voltage between connection points A and B is detected and becomes the input voltage ν1 of the bidirectional output voltage buffer 60. Connection points A and E are the connection points of the telephone 1, so the high voltage power supply V,... = -48V is used, so the phone 10 on hook (loop off).

オフフック(ループオン)に応じて2線電圧変化する。The two-wire voltage changes depending on off-hook (loop on).

ダイオードD1 mD*と出力トランジスタQ*、Qm
は高電圧系回路の出力回路をなす電流ソースと電流シン
ク能力のある双方向性出力電圧バッファ6を構成し、出
力トランジスタQlaQ、に相補トランジスタを用いて
ダイオードD1 eD、を付加することによりAH級動
作の双方向出力特性を有する。結合容量C,は高電圧系
回路の出力の双方向出力電圧バッファと次の低電圧系回
路の入力を交流的に結合する容量である。ダイオードD
l s Diは結合容量C1とアース間に接続されて低
電圧系回路の入力を保護する双方向電圧クランパー7を
構成する。入力抵抗R8、抵抗R,トオペアンプ5は低
電圧電源’CC= 5 ’ mV、、 =++ −5V
が用いられる低電圧系回路の入力回路な構成する。
Diode D1 mD* and output transistor Q*, Qm
constitutes a bidirectional output voltage buffer 6 with current source and current sink capability, which forms the output circuit of a high voltage circuit, and adds a diode D1 eD, using a complementary transistor to the output transistor QlaQ, to achieve AH class. Has bidirectional output characteristics of operation. The coupling capacitor C is a capacitor that couples the bidirectional output voltage buffer of the output of the high voltage circuit and the input of the next low voltage circuit in an alternating current manner. Diode D
l s Di constitutes a bidirectional voltage clamper 7 that is connected between the coupling capacitor C1 and the ground to protect the input of the low voltage circuit. Input resistor R8, resistor R, and operational amplifier 5 are connected to low voltage power supply 'CC = 5' mV, =++ -5V
This is an input circuit for low-voltage circuits that are used.

第3図は第1図の電話機1側のオンフック。Figure 3 shows on-hook on the telephone 1 side of Figure 1.

オフフックに応じて生じる各回路部分の大振幅電圧変動
の過渡応答特性を示す波形図である。
FIG. 7 is a waveform diagram showing transient response characteristics of large amplitude voltage fluctuations of each circuit portion that occur in response to off-hook.

第3図において、tlBは双方向出力電圧バッファ6の
入力電圧(抵抗島の電圧VB ) # 03は結合容量
Cjの充電電圧、5は結合容量C8の電流、Diは低電
圧系回路の入力電圧である。第3図により第1図の動作
を説明すると、第1図の電話機1のオンフック時には、
電話機1の負荷電流が0のため、双方向出力電圧バッフ
ァ60入力電圧(抵抗R,の電圧)ν1はm5図のよう
にほぼOrとなっておシ、このとき結合容量C5の充電
電圧ジ、結合容量C8の電流り、低電圧系回路の入力電
圧V、も第5図のようにOである。この状態から電話機
1がオフフックに変化すると、電話機1に負荷電流が突
然流れるため、双方向出力電圧バッファ60入力電圧1
1Bは第5図のように急激に低下して例えば−15Fと
なる。このとき結合容量C5も電圧りの低下に伴なりて
充電が始まシ第5図のように充電電圧s+5も低下して
例えば−15Vとなるが、出力トランジスタQ8の出力
抵抗が十分低いためダイオードD、→結合容量C5→ト
ランジスタQ、のエミッタのルートで第3図のように結
合容量C8の大充電電流i、が流れ、結合容量C8の充
電は短時間に終シ充電電圧ν、および充電電流龜も短時
間に大振幅過渡変化する。この充電電流i、が流れてい
るごく短時間の間だけクランプダイオードD、が導通し
て低電圧系回路の入力電圧Vも第3図のように例えば−
r:1.7Vとなるが、この導通期間t、たけ高電圧系
回路から低電圧系回路への信号伝達が中断する。ついで
再び電話機1がオンフックに移行すると、電話機1の負
荷電流が突然流れなくなるため電圧vEは第3図のよう
に急激にほぼOrにもどる。このとき結合容量C3も電
圧IJBの上昇に伴って放電が始まり第3図のように充
電電圧υ、も上昇してOrとなるが、今度は出力トラン
ジスタQ1の出力抵抗が十分低いためトランジスタQ1
のエミッタ→結合容量C5→ダイオードD4のルートで
第3図のように結合容量C8の大放電電流i5が流れ、
結合容量C5の放電は短時間に終シ充電電圧ν、および
放電電流i5も短時間に大振幅過渡変化する。
In Fig. 3, tlB is the input voltage of the bidirectional output voltage buffer 6 (voltage of the resistive island VB), #03 is the charging voltage of the coupling capacitor Cj, 5 is the current of the coupling capacitor C8, and Di is the input voltage of the low voltage circuit. It is. To explain the operation of FIG. 1 with reference to FIG. 3, when the telephone 1 of FIG. 1 is on-hook,
Since the load current of the telephone 1 is 0, the input voltage ν1 of the bidirectional output voltage buffer 60 (voltage of the resistor R) becomes almost Or as shown in the diagram m5, and at this time, the charging voltage of the coupling capacitor C5 is The current of the coupling capacitor C8 and the input voltage V of the low voltage circuit are also O as shown in FIG. When the telephone 1 changes from this state to off-hook, load current suddenly flows to the telephone 1, so the bidirectional output voltage buffer 60 input voltage 1
As shown in FIG. 5, 1B rapidly decreases to, for example, -15F. At this time, the coupling capacitor C5 also starts to be charged as the voltage decreases, and the charging voltage s+5 also decreases to, for example, -15V as shown in FIG. 5, but since the output resistance of the output transistor Q8 is sufficiently low, the diode D , → Coupling capacitor C5 → Transistor Q, as shown in Figure 3, a large charging current i of coupling capacitor C8 flows through the emitter route of transistor Q, and the charging of coupling capacitor C8 ends in a short time. The head also undergoes large amplitude transient changes in a short period of time. The clamp diode D becomes conductive only for a very short time while this charging current i is flowing, and the input voltage V of the low voltage circuit also changes as shown in Fig. 3, for example -
r: 1.7V, but during this conduction period t, signal transmission from the high voltage circuit to the low voltage circuit is interrupted. Then, when the telephone 1 goes on-hook again, the load current of the telephone 1 suddenly stops flowing, and the voltage vE suddenly returns to approximately Or as shown in FIG. At this time, the coupling capacitance C3 also begins to discharge as the voltage IJB rises, and the charging voltage υ also rises to become Or as shown in FIG.
As shown in Fig. 3, a large discharge current i5 of the coupling capacitance C8 flows through the route of emitter → coupling capacitance C5 → diode D4,
The discharge of the coupling capacitor C5 ends in a short time, and the charging voltage ν and the discharge current i5 also undergo large amplitude transient changes in a short time.

この放電電流i5が流れているごく短時間の間だけ今度
はクランプダイオードD、が導通して低電圧系回路の入
力電圧V、も第3図のように例えば+α7rとなるが、
この導通期間t、だけ高電圧系回路から低電圧系回路へ
の信号伝達が中断する。
Only for a very short time while this discharge current i5 is flowing, the clamp diode D becomes conductive, and the input voltage V of the low voltage circuit also becomes, for example, +α7r as shown in Fig. 3.
Signal transmission from the high voltage circuit to the low voltage circuit is interrupted during this conduction period t.

このようにして直流レベルの大振幅過渡変動に対しては
結合容量C8と高電圧系回路の出力の双方向出力電圧バ
ッファ6の出力抵抗R,と低電圧系回路の入力の双方向
電圧クランパー7のオン抵抗R6Hによって定まる時定
数丁’、  =C,CRo+RoN)の時間で結合容量
C1の充放電時間を終えることができ、このため出力抵
抗R6およびオン抵抗R61を低電圧系回路の入力回路
の入力抵抗R8にくらべて十分小さく設定すれば双方向
電圧クランパー7の導通による信号伝達の中断をごく短
時間内に抑えることが可能となる。上記の高電圧系回路
の双方向出力電圧バッファ6の出力トランジスタQ1.
Q*をAB級動作としているのは、いかなる電圧変動に
対してもその出力抵抗R6が常に低くみえるように動作
させるためで、単なるB動作作では出力トランジスタQ
x n (hの動作切換え時Kf?いて一時的に両トラ
ンジスタQt、Qtが共にオフする期間が発生して、上
記の結合容量C8の充放電時間がのびる問題が生じる。
In this way, large amplitude transient fluctuations in the DC level can be handled by combining the coupling capacitor C8, the output resistance R of the bidirectional output voltage buffer 6 at the output of the high voltage circuit, and the bidirectional voltage clamper 7 at the input of the low voltage circuit. The charging/discharging time of the coupling capacitor C1 can be completed in the time constant d', = C, CRo+RoN) determined by the on-resistance R6H of the output resistor R6 and the on-resistance R61 of the input circuit of the low voltage circuit. If it is set sufficiently smaller than the input resistor R8, it becomes possible to suppress interruption of signal transmission due to conduction of the bidirectional voltage clamper 7 within a very short time. Output transistor Q1 of the bidirectional output voltage buffer 6 of the above-mentioned high voltage circuit.
The reason why Q* is set to AB class operation is to operate so that its output resistance R6 always appears low regardless of any voltage fluctuation; in simple B operation, the output transistor Q
When switching the operation of x n (h, Kf?), a period occurs in which both transistors Qt and Qt are temporarily turned off, causing a problem in which the charging and discharging time of the coupling capacitor C8 is prolonged.

以上のように本発明による実施例では、高電圧系回路の
信号成分を容量結合を介して低電圧系回路に伝達する信
号伝達系において、高電圧系回路の出力回路を双方向出
力電圧バッファ6で構成し、低電圧系回路の入力に双方
向電圧クランパ7を設けることにより、直流レベルの大
振幅過渡変化時の結合時定数τ2=C8(Ro+RoN
)と小振幅定常時の結合時定数τ、=C8・へを切シ控
えて、大振幅過渡変化時の小信号伝達の中断時間の短縮
化を可能にしてお)、従来例では大振幅過渡変化時の結
合時定数と小振幅定常時の結合時定数が同一のため、大
振幅過渡変化時の小信号伝達の中断時間の短縮化が行え
なかった。
As described above, in the embodiment according to the present invention, in a signal transmission system that transmits a signal component of a high voltage circuit to a low voltage circuit via capacitive coupling, the output circuit of the high voltage circuit is connected to the bidirectional output voltage buffer 6. By providing a bidirectional voltage clamper 7 at the input of the low voltage circuit, the coupling time constant τ2=C8(Ro+RoN
) and the coupling time constant τ, =C8 during small amplitude steady state, it is possible to shorten the interruption time of small signal transmission during large amplitude transient change), and in the conventional case, large amplitude transient Since the coupling time constant during a change and the coupling time constant during a small amplitude steady state are the same, it was not possible to shorten the interruption time of small signal transmission during a large amplitude transient change.

第4図は本発明による島速クランプ回路の第2の実施例
を示す低電圧系回路入力の双方向電圧クランパー7の回
路図である。第4図において、Q、rmQaはトランジ
スタである。なお各図面を通じて同一符号または記号は
同一または相当部分を示するものとする。第4図の双方
向電圧クランパー7はg1図のダイオードDS sD4
をトランジスタQt−(hに変えた構成である。本実施
例によればトランジスタQt−Qsの動作によりさらに
低いオン抵抗R6Nでの電圧クランプが可能となる。
FIG. 4 is a circuit diagram of a bidirectional voltage clamper 7 having a low voltage circuit input, showing a second embodiment of the island speed clamp circuit according to the present invention. In FIG. 4, Q and rmQa are transistors. Note that the same reference numerals or symbols indicate the same or corresponding parts throughout the drawings. The bidirectional voltage clamper 7 in Figure 4 is a diode DS sD4 in Figure g1.
This is a configuration in which the transistor Qt-(h) is changed. According to this embodiment, the operation of the transistors Qt-Qs enables voltage clamping with an even lower on-resistance R6N.

第5図は本発明による高速クランプ回路の第3の実施例
を示す低電圧系回路入力の双方向電圧クランパー7の回
路図である。第5図において、Qo、Qt。+Q11 
、Q□はトランジスタ、’Ig’!は定電流源、 V1
t□2□、8.、□ は基準電圧源である。
FIG. 5 is a circuit diagram of a bidirectional voltage clamper 7 for low voltage circuit input, showing a third embodiment of the high speed clamp circuit according to the present invention. In FIG. 5, Qo, Qt. +Q11
, Q□ is a transistor, 'Ig'! is a constant current source, V1
t□2□, 8. , □ is the reference voltage source.

I。I.

第5図の双方向電圧クランパー7は定電流源り。The bidirectional voltage clamper 7 in FIG. 5 is a constant current source.

I、をそれぞれトランジスタQ、、QL。とトランジス
タ(’11 mQs* のバイアス電流用として、トラ
ンジスタQ9のエミッタ電位とトランジスタ(’o の
エミッタ電位が等しくできるため負電圧側のクランプ電
圧が基準電圧源VR□2□で設定でき、同様にして正電
圧側のクランプ電圧が基本電圧源’R1!!□で設定で
きる構成である。本実施例によればクランプ電圧がダイ
オード特性とは独立に設定できるのでより高精度な電圧
クランプが可能となる。
I, respectively, are transistors Q,,QL. For the bias current of transistor ('11 mQs*), the emitter potential of transistor Q9 and the emitter potential of transistor ('o) can be made equal, so the clamp voltage on the negative voltage side can be set by the reference voltage source VR□2□, and similarly The configuration is such that the clamp voltage on the positive voltage side can be set using the basic voltage source 'R1! Become.

第6図は本発明による高速クランプ回路の第4の実施例
を示す低電圧系回路入力の双方向電圧クランパー7の回
路図である。第6図において、Dl、D、はダイオード
である。第6図の双方向電圧クランパー7は第1図のダ
イオードD3゜D、を接地レベルに対して導通させるの
ではなしに第6図のダイオードD、、D、を低電圧電源
’cc=+5V、V□、=−5Vに対して導通させる構
成である。本実施例によれば低電圧系回路の入力電圧V
、が低電圧電源Vcc=+5Vよシ高くなるとダイオー
ドD、が導通して入力電圧νを電源Vcc−+5Vまで
の電位にクランプし、入力電圧IJiが低電圧電源V。
FIG. 6 is a circuit diagram of a bidirectional voltage clamper 7 for low voltage circuit input, showing a fourth embodiment of the high speed clamp circuit according to the present invention. In FIG. 6, Dl and D are diodes. The bidirectional voltage clamper 7 of FIG. 6 connects the diodes D, D, of FIG. 6 to the low voltage power supply 'cc=+5V, V, instead of making the diode D3D of FIG. 1 conductive to ground level. □, = -5V is configured to conduct. According to this embodiment, the input voltage V of the low voltage circuit
, becomes higher than the low voltage power supply Vcc=+5V, the diode D becomes conductive and clamps the input voltage ν to a potential up to the power supply Vcc−+5V, and the input voltage IJi becomes the low voltage power supply V.

=g#Vよシ低下するとダイオードD6が導通して入力
電圧V、を電源V、、=−#Vまでの電位にクランプす
るよう動作する。
When the voltage drops by =g#V, the diode D6 becomes conductive and operates to clamp the input voltage V to a potential up to the power supply V, . . . =-#V.

以上のように本発明の実施例によれば、高電圧系回路の
信号成分を容量結合を介して低電圧系回路に伝達する信
号伝達系において、高電圧系回路の信号を出力する電流
シンクおよび電流ソース能力を持つ双方向出力電圧バッ
ファと、この双方向出力電圧バッファと低電圧系回路入
力を交流的に結合する結合容量と、この結合容量とアー
ス間などに接続されて低電圧系回路入力を保護する双方
向電圧クランパーよシ高速クランパーを構成し、高電圧
系回路の過渡的な直流レベル変動による低電圧系回路入
力への信号伝達の影響を上記双方向出力電圧バッファと
双方向電圧クランパーによ)結合容量の充放電を高速化
して短時間に収束させることができる。
As described above, according to the embodiment of the present invention, in a signal transmission system that transmits a signal component of a high voltage circuit to a low voltage circuit via capacitive coupling, a current sink that outputs a signal of the high voltage circuit; A bidirectional output voltage buffer with current source capability, a coupling capacitor that AC-couples the bidirectional output voltage buffer and the low voltage circuit input, and a coupling capacitor connected between the coupling capacitor and the ground to connect the low voltage circuit input. A high-speed clamper is configured to protect the bidirectional output voltage buffer and the bidirectional voltage clamper from the effects of transient DC level fluctuations in the high voltage circuit on signal transmission to the low voltage circuit input. ) The charging and discharging of the coupling capacitance can be accelerated and converged in a short time.

なお上記実施例では電話交換機の加入者回路の2線−4
線変換部に適用した場合について説明したが、本発明に
よる高速クランプ回路はこれに限定されるものではない
In the above embodiment, wire 2-4 of the subscriber circuit of the telephone exchange
Although the case where the present invention is applied to a line converter has been described, the high-speed clamp circuit according to the present invention is not limited to this.

〔発明の効果〕〔Effect of the invention〕

以上の説明のように本発明の高速クランプ回路によれば
、高電圧系回路の信号成分を容量結合を介して低電圧系
回路に伝達する信号伝達系において結合時定数による信
号中断時間を短縮化できるので、この種の信号伝達系を
なす電話交換機の加入者回路の2線−4線変換部などに
使用すれば電話交換機の加入者端末に対するサービス機
能の向上などがはかれる効果がある。
As described above, according to the high-speed clamp circuit of the present invention, the signal interruption time due to the coupling time constant is shortened in the signal transmission system that transmits the signal component of the high voltage circuit to the low voltage circuit via capacitive coupling. Therefore, if it is used in a 2-wire to 4-wire conversion section of a subscriber circuit of a telephone exchange that constitutes this type of signal transmission system, it will have the effect of improving the service function for subscriber terminals of the telephone exchange.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による高速クランプ回路の第1の実施例
を示2全体回路図、第2図(α+ 、 (b>は第1図
の各カレントミラー2と5,4の等価回路図、第3図は
第1図の過渡変化時の各部の動作波形側図、第4図は本
発明による第2の実施例を示す双方向電圧クランパーの
回路図、第5図は本発明による第5の実施例を示す双方
向電圧クランパーの回路図、第6図は本発明による禽4
の実施例を示す双方向電圧クランパーの回路図である。 1・・・電話機 2.3.4・・・カレントミラー 5・・・オペアンプ 6・・・双方向出力電圧バッファ 7・・・双方向電圧クランパー 尺S R1−R6・・・抵抗     へ・・・入力抵抗り、
−D6・・・ダイオード  Q1〜Q1!・・・トラン
ジスタC8・・・結合容量     V□・・・高電圧
電源’CC,’l□ ・・・低電圧電源 1.− 代理人弁理士  小 川 勝 男 11 図 時間t→
1 shows a first embodiment of a high-speed clamp circuit according to the present invention; 2 is an overall circuit diagram; FIG. 2 is an equivalent circuit diagram of each current mirror 2, 5, and 4 in FIG. 3 is a side view of the operation waveforms of each part during the transient change in FIG. 1, FIG. 4 is a circuit diagram of a bidirectional voltage clamper showing a second embodiment of the present invention, and FIG. FIG. 6 is a circuit diagram of a bidirectional voltage clamper showing an embodiment of the present invention.
FIG. 2 is a circuit diagram of a bidirectional voltage clamper showing an embodiment of the present invention. 1... Telephone 2.3.4... Current mirror 5... Operational amplifier 6... Bidirectional output voltage buffer 7... Bidirectional voltage clamper length S R1-R6... Resistor... input resistance,
-D6...Diode Q1~Q1! ...Transistor C8...Coupling capacitance V□...High voltage power supply 'CC,'l□...Low voltage power supply 1. - Representative Patent Attorney Katsutoshi Ogawa 11 Figure Time t→

Claims (1)

【特許請求の範囲】[Claims] 高電圧系回路の信号成分を容量結合を介して低電圧系回
路に伝達する信号伝達系において、高電圧系回路の信号
を出力する電流シンクおよび電流ソース能力を持つ双方
向出力電圧バッファと、該双方向出力電圧バッファと低
電圧系回路入力を交流的に結合する結合容量と、該結合
容量と低電圧系回路入力の間に挿入されて低電圧系回路
入力を保護する双方向電圧クランパーより成り、高電圧
系回路の過渡的な直流レベル変動による低電圧系回路入
力への影響を上記双方向出力電圧バッファおよび双方向
電圧クランパーにより上記結合容量の充放電を高速化し
て短時間に収束させるように構成した高速クランプ回路
In a signal transmission system that transmits signal components from a high-voltage circuit to a low-voltage circuit via capacitive coupling, a bidirectional output voltage buffer with current sink and current source capabilities that outputs a signal from the high-voltage circuit; It consists of a coupling capacitor that AC-couples the bidirectional output voltage buffer and the low voltage circuit input, and a bidirectional voltage clamper that is inserted between the coupling capacitor and the low voltage circuit input to protect the low voltage circuit input. In order to reduce the influence of transient DC level fluctuations in the high voltage circuit on the low voltage circuit input, the bidirectional output voltage buffer and the bidirectional voltage clamper speed up the charging and discharging of the coupling capacitor and converge in a short time. A high-speed clamp circuit configured as follows.
JP61084119A 1986-04-14 1986-04-14 High-speed clamping circuit Pending JPS62241423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61084119A JPS62241423A (en) 1986-04-14 1986-04-14 High-speed clamping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61084119A JPS62241423A (en) 1986-04-14 1986-04-14 High-speed clamping circuit

Publications (1)

Publication Number Publication Date
JPS62241423A true JPS62241423A (en) 1987-10-22

Family

ID=13821628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61084119A Pending JPS62241423A (en) 1986-04-14 1986-04-14 High-speed clamping circuit

Country Status (1)

Country Link
JP (1) JPS62241423A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2015098039A1 (en) * 2013-12-25 2017-03-23 株式会社ソシオネクスト Signal potential conversion circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2015098039A1 (en) * 2013-12-25 2017-03-23 株式会社ソシオネクスト Signal potential conversion circuit

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