JPS62239582A - Semiconductor device reinforced in its resistance to radiation - Google Patents

Semiconductor device reinforced in its resistance to radiation

Info

Publication number
JPS62239582A
JPS62239582A JP8348686A JP8348686A JPS62239582A JP S62239582 A JPS62239582 A JP S62239582A JP 8348686 A JP8348686 A JP 8348686A JP 8348686 A JP8348686 A JP 8348686A JP S62239582 A JPS62239582 A JP S62239582A
Authority
JP
Japan
Prior art keywords
oxide film
radiation
gate
interface
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8348686A
Other languages
Japanese (ja)
Other versions
JPH0579189B2 (en
Inventor
Kunihiko Kasama
笠間 邦彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8348686A priority Critical patent/JPS62239582A/en
Publication of JPS62239582A publication Critical patent/JPS62239582A/en
Publication of JPH0579189B2 publication Critical patent/JPH0579189B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To reduce fixed positive charge accumulated in a gate oxide film and interfacial potential, and to improve a resistance to radiation, by forming a gate electrode in the manner such that a compression stress is applied on the boundary surface of a substrate side in the boundary region of the gate oxide film and an Si substrate. CONSTITUTION:A gate electrode is formed by adjusting its film thickness and forming temperature, etc. in the manner in which compression stress is applied both on the side of a gate oxide film and on the side of an Si substrate in a boundary region of the gate oxide film and the Si substrate. As the result of this, even if ionization radiant rays make an incidence thereon, the accumula tion of positive charge and generation of interfacial potential are suppressed, and resistance to radiation extremely increases. The range of optimum compres sion stress is estimated as 0.5-5X10<7> dyn/cm<2>.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は耐放射線性が強化された半導体装置にかかり、
とくに絶縁ゲート電界効果トランジスタを基本素子とす
る半導体装置の耐放射線性向上に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device with enhanced radiation resistance;
In particular, it relates to improving the radiation resistance of semiconductor devices whose basic elements are insulated gate field effect transistors.

〔従来の技術〕[Conventional technology]

近年、半導体集積回路を宇宙空間、原子炉周辺などで使
用する機会が増加しつつある。そのような厳しい環境内
に8かれた半導体集積回路は撞々の放射綴]貝傷ケ受は
回路の該動作X工び破壊ケ生じ、システムの機能低下ケ
受けや丁い。したがって放射線に強い半導体集積回路の
開発が4まれる。
In recent years, opportunities to use semiconductor integrated circuits in space, around nuclear reactors, etc. have been increasing. Semiconductor integrated circuits built in such a harsh environment are subject to constant radiation damage, which can result in damage to the circuit's operation, resulting in a decline in system functionality. Therefore, the development of semiconductor integrated circuits that are resistant to radiation is required.

高集積度を有する半導体集積回路の基本素子でする絶縁
ゲート電界効果トランジスタ(以下MOSトランジスタ
と略す)′j6エびバイポーラトランジスタの放射線損
傷の主な原因は、シリコン酸化膜中への正tiの蓄積及
びシリコン酸化膜とシリコン基板との界面にゴdける界
面準位密度の増加である。特にMOS)ランジスタはゲ
ート7地縁膜Sよびゲート絶謙膜/シリコン界面の損傷
が直接しきい値電圧の変動とリーク電流との増加に反映
するため集積回路の特性劣化が生じゃ丁い。
The main cause of radiation damage to insulated gate field effect transistors (hereinafter referred to as MOS transistors) and bipolar transistors, which are the basic elements of highly integrated semiconductor integrated circuits, is the accumulation of positive Ti in the silicon oxide film. and an increase in the density of interface states at the interface between the silicon oxide film and the silicon substrate. In particular, in MOS transistors, damage to the gate 7 dielectric film S and the gate insulating film/silicon interface is directly reflected in fluctuations in threshold voltage and increases in leakage current, leading to deterioration in the characteristics of the integrated circuit.

放射線損傷の機構Z以下に簡単に述べる。丁なわち電離
放射線がシリコン酸化膜に入射すると多量の電子−正孔
対が生成する。その後、その一部は再結合して消滅する
が、一部はシリコン酸化膜に捕獲される。電子の移動度
は大きく、正のゲート電圧のもとでは短時間で酸化膜外
に拡散するが。
The mechanism of radiation damage Z is briefly described below. When ionizing radiation is incident on a silicon oxide film, a large number of electron-hole pairs are generated. Thereafter, part of it recombines and disappears, but part of it is captured by the silicon oxide film. The mobility of electrons is high, and they diffuse out of the oxide film in a short time under positive gate voltage.

正孔は移動度が小さく、シリコン酸化膜内に捕獲され、
正の固定電荷が形成される。またシリコン酸化膜−シリ
コン基板界面に捕獲された正孔は界面準位を形成すると
言わiしている。
Holes have low mobility and are captured within the silicon oxide film,
A positive fixed charge is formed. It is also said that holes captured at the silicon oxide film-silicon substrate interface form an interface level.

以上述べた放射線損傷(固定正電荷の蓄積と界面準位の
発生)の大きさはシリコン酸化bQ/y’)コン基板界
面′須域に印加する歪によって犬さく変化する。丁なわ
ち上記界面領域に圧、縮応力が印加さ、rLるとJ:I
i協は減少し、引張応力が印加されると損傷は増大する
傾向がある。こnは王、縮応力が印加されると原子間隔
が減少する之め、正孔による結合の切断か生じても容易
に再結合しやすいためと考えら、tする。一方、引張応
力が界面に印加されると原子間隔が5曽太し、再結合が
起こりにくくなり損傷が蓄積するとそえられる。
The magnitude of the radiation damage (accumulation of fixed positive charges and generation of interface states) described above varies greatly depending on the strain applied to the silicon oxide bQ/y') substrate interface. In other words, pressure and compression stress are applied to the above interface region, rL and J:I
The damage tends to decrease and the damage increases when tensile stress is applied. This is because the atomic spacing decreases when compression stress is applied, so even if bonds are broken by holes, they are likely to recombine easily. On the other hand, when tensile stress is applied to the interface, the atomic spacing increases by 5 times, making it difficult for recombination to occur and causing damage to accumulate.

従来のMOS)ランジスタは、ゲート’tiの材料とし
て、リンなどの不斗吻ゲ導入し/’Cポリシリコン基根
上に形成されたシリコン酸化膜乞ゲートP3縁膜とする
のが一般的であった。
Conventional MOS transistors generally use a silicon oxide film formed on a polysilicon base as a material for the gate P3, with a material such as phosphorus introduced therein. Ta.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述し/’cl米のMOS)ランジスタのゲート電極は
、ポリシリコン膜が用いられているため、シリコン酸化
膜からなるゲート絶以上ケにポリシリコンj摸を形成し
てもゲート絶、盪j漠/シリコン界面領域に加わる応力
はほとんど変化しない。また、シリコン酸化膜の熱膨張
係Pはシリコン結晶の熱膨張係数エリ小さいため、第2
図に示す工うに、シリコン酸化膜とシリコン基板との界
面にSいてシリコン−!ls板側に引張応力、シリコン
酸化膜周に圧縮応力がbpわり、Cのような界面状態の
ちとでは放射線照射に、Lろ界面単位発生の割合が比較
的大きく耐放射線性は充分とは言えないという欠点があ
った。
As mentioned above, since a polysilicon film is used for the gate electrode of the transistor (MOS) transistor, even if a polysilicon pattern is formed over the gate made of a silicon oxide film, the gate electrode will not be removed. /The stress applied to the silicon interface region hardly changes. In addition, the thermal expansion coefficient P of the silicon oxide film is smaller than that of the silicon crystal, so the second
As shown in the figure, S is present at the interface between the silicon oxide film and the silicon substrate. The tensile stress on the LS plate side and the compressive stress on the silicon oxide film periphery are bp, and after an interface state like C, the proportion of L interface units occurring is relatively large when exposed to radiation, although radiation resistance is not sufficient. There was a drawback that there was no

〔問題点を解決するための手段〕[Means for solving problems]

本発明の耐放射線性が強化された半導体装置は。 The present invention provides a semiconductor device with enhanced radiation resistance.

絶縁ゲート電界効果トランジス、りのゲート絶縁膜とシ
リコン基板との界面領域のシリコン基板側界面にQ、 
5 X 10 ’ 〜5 X I Q ’ dyn k
IIt  の圧縮応力が印加されるようにゲート電極が
形成されていることを特徴とする。
In the insulated gate field effect transistor, Q is placed on the silicon substrate side interface in the interface region between the gate insulating film and the silicon substrate.
5 X 10' ~ 5 X I Q' dyn k
The gate electrode is characterized in that the gate electrode is formed so that a compressive stress of IIt is applied.

〔実施例〕〔Example〕

次に1本発明について図面を参照して説明する。 Next, one embodiment of the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を模式的に示し友ものであり
、ゲートを極はゲート酸化膜/シリコン基板界面領域の
ゲート酸化膜側、シリコン基板側にともに圧縮応力かく
わわるようにゲート電極の膜厚、電極形成時の温度等を
調整して形成されている。このときシリコン酸化膜の界
面1gよび内部にはシリコン酸化膜/シリコン基板2層
構造の場合よりさらに大きな圧縮応力かくわわる。以上
のようにゲート絶縁膜中、Hよびゲート絶縁膜/シリコ
ン基板界面にともに圧縮応力が働くため電離放射線が入
射しても正電荷の蓄積、界面準位の発生は抑制され、耐
放射線性は大幅に向上する。
FIG. 1 schematically shows an embodiment of the present invention, in which the gate is placed in such a way that compressive stress is applied to both the gate oxide film side and the silicon substrate side of the gate oxide film/silicon substrate interface region. It is formed by adjusting the film thickness of the electrode, the temperature at the time of electrode formation, etc. At this time, even larger compressive stress than in the case of the silicon oxide film/silicon substrate two-layer structure is generated at the interface 1g of the silicon oxide film and inside the silicon oxide film. As described above, compressive stress acts on both H and the gate insulating film/silicon substrate interface in the gate insulating film, so even if ionizing radiation is incident, the accumulation of positive charges and the generation of interface states are suppressed, and radiation resistance is reduced. Significantly improved.

耐放射線性は圧縮応力の増大とともに向上するが。Although radiation resistance improves with increasing compressive stress.

しだいにその度合は飽和する傾向がある。さらに圧縮圧
力が増加するとともに移動度の減少等の初期特性の劣化
あるいははがれ等の信頼性の低下が起こる。以上の点を
考慮すると、最適の圧縮応力の範囲が0.5〜sxt 
o ’ dyn /ctdと見積もられる。
Gradually, the degree tends to reach saturation. Further, as the compression pressure increases, initial characteristics deteriorate such as a decrease in mobility, or reliability decreases such as peeling. Considering the above points, the optimal compressive stress range is 0.5~sxt
It is estimated that o' dyn/ctd.

次にP型シリコン基板にポリサイド(シリサイド/ポリ
シリコンの2)−構造)ゲー)MOSダイオードとMO
S)ランジスタを形成した場合について述べる。ゲート
電極はポリサイドに限らず。
Next, polycide (silicide/polysilicon 2)-structure) gate) MOS diode and MO are placed on the P-type silicon substrate.
S) The case where a transistor is formed will be described. Gate electrodes are not limited to polycide.

シリサイド、アルミニウム2よびタングステン等の高融
点金属、いずれでもかまわない。シリコン基板界面に0
.5〜5 X 10’ dyn/cr71の圧縮応力が
印加できればよい。
Any of silicide, aluminum 2, and high melting point metals such as tungsten may be used. 0 at the silicon substrate interface
.. It is sufficient if a compressive stress of 5 to 5 x 10' dyn/cr71 can be applied.

第3図にMOSダイオードの電離放射線照射による界面
準位発生量ΔDit  と固定電荷発生量ΔQot  
の応力依存性を示した。いずれの発生量も圧縮応力が増
大するとともに減少し、その後飽和している。特にΔD
it  の減少が著しい。
Figure 3 shows the amount of interface states generated ΔDit and the amount of fixed charge generated ΔQot due to ionizing radiation irradiation of the MOS diode.
showed stress dependence. Both amounts of generation decrease as the compressive stress increases, and then become saturated. Especially ΔD
The decrease in it is significant.

一方、W期界面準位Xよび初期固定゛1ヒ荷は圧縮応力
が大きい領域(> 5 X 10’dyn〆耐)で急激
に大きくなる。したがって圧縮応力には最適領域が存在
する。
On the other hand, the W-period interface state X and the initially fixed 1 load suddenly increase in a region where the compressive stress is large (>5×10'dyn limit resistance). Therefore, there is an optimum region for compressive stress.

WI4図に従来のポリシリコンゲートMOSトランシス
タ(引張応力< 0.5 x 10 ’ dyn/ff
1)と本発明によるポリサイドゲートMOSトランジス
タ(圧縮応力= 2 X 10 ’ ayn、x=)と
の電離放射線照射前後のサブスレッシェオルド特性の一
例を示した。初期特性はほぼ等しいが、放射線照射後の
負方向へのシフト量、サブスレッシェオルドスイングの
変動、いずれも本発明のポリサイドゲートMOSトラン
ジスタが小さいことがわかる。
Figure WI4 shows a conventional polysilicon gate MOS transistor (tensile stress < 0.5 x 10' dyn/ff
1) and a polycide gate MOS transistor according to the present invention (compressive stress=2×10′ ayn, x=), an example of the subthreshold characteristics before and after irradiation with ionizing radiation is shown. It can be seen that although the initial characteristics are almost the same, the amount of shift in the negative direction after radiation irradiation and the variation in subthreshold swing are both smaller in the polycide gate MOS transistor of the present invention.

以上の結果は固定正電荷の蓄積と、界面準位の発生がと
もに小さいことを示している。
The above results indicate that both the accumulation of fixed positive charges and the generation of interface states are small.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、絶縁ゲート電界効果トラ
ンジスタのゲート絶縁膜とシリコン基板との界面領域の
シリコン茶飯側界面に圧縮応力が加わるようにゲート電
極が形成されていることにより、ゲート酸化膜中に蓄積
する固定圧゛1荷、ゲート絶縁膜/シリコン基板界面に
発生する界面準位を大幅に減少させろことができ、耐放
射線性を大きく向上させぬことができる。
As explained above, the present invention has a structure in which the gate electrode is formed so that compressive stress is applied to the interface between the gate insulating film and the silicon substrate of the insulated gate field effect transistor on the silicon side. It is possible to significantly reduce the fixed pressure load accumulated in the semiconductor device and the interface states generated at the gate insulating film/silicon substrate interface, and it is possible to significantly improve radiation resistance.

【図面の簡単な説明】[Brief explanation of drawings]

@1図は本発明の一実1例のゲート電離/ゲート杷縁膜
/シリコン基板3層構造の応力分布を示す模式図、第2
+’=:It:fシリコン酸化、模/シリコン基板2ノ
ー構造の応力分;15を示す模式図、第3図は電離放射
1派照・村による界面単位発生量と固定゛屯荷蓄積隘の
応力依存性/d′長わ丁グラフ、第・1図は電離放射線
照射前後のサブスレッシ−オルト特性を示すグラフで、
実線が本発男の一実施例のポリサイトゲ−)MOS)ラ
ンジスタ、破線が従来のポリシリゲートMO3)ランジ
スタを示す。 代理人 弁理士  内 原   音 第1図 S しlノコレ基扱界面の応力(x to +/(:m’ 
)第3図
Figure 1 is a schematic diagram showing the stress distribution of a three-layer structure of gate ionization/gate edge film/silicon substrate in one example of the present invention.
+'=:It:fSilicon oxidation, stress component of silicon substrate 2 no structure; Schematic diagram showing 15, Figure 3 shows the amount of ionizing radiation generated per interface and the fixed load accumulation due to radiation Figure 1 is a graph showing the subthreshold-ortho characteristics before and after ionizing radiation irradiation.
The solid line shows the polysilicate MOSFET transistor of one embodiment of the present invention, and the broken line shows the conventional polysiligate MOMOS transistor. Agent Patent Attorney Uchi Hara Oto Figure 1
)Figure 3

Claims (1)

【特許請求の範囲】[Claims] 絶縁ゲート電界効果トランジスタのゲート絶縁膜とシリ
コン基板との界面領域のシリコン基板側界面に0.5×
10^7〜5×10^7dyn/cm^2の圧縮応力が
印加されるようにゲート電極が形成されていることを特
徴とする耐放射線性が強化された半導体装置。
0.5× at the silicon substrate side interface in the interface region between the gate insulating film and the silicon substrate of the insulated gate field effect transistor.
A semiconductor device with enhanced radiation resistance, characterized in that a gate electrode is formed so that a compressive stress of 10^7 to 5 x 10^7 dyn/cm^2 is applied.
JP8348686A 1986-04-10 1986-04-10 Semiconductor device reinforced in its resistance to radiation Granted JPS62239582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8348686A JPS62239582A (en) 1986-04-10 1986-04-10 Semiconductor device reinforced in its resistance to radiation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8348686A JPS62239582A (en) 1986-04-10 1986-04-10 Semiconductor device reinforced in its resistance to radiation

Publications (2)

Publication Number Publication Date
JPS62239582A true JPS62239582A (en) 1987-10-20
JPH0579189B2 JPH0579189B2 (en) 1993-11-01

Family

ID=13803805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8348686A Granted JPS62239582A (en) 1986-04-10 1986-04-10 Semiconductor device reinforced in its resistance to radiation

Country Status (1)

Country Link
JP (1) JPS62239582A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007503117A (en) * 2003-08-18 2007-02-15 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Field effect transistor with increased carrier mobility

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007503117A (en) * 2003-08-18 2007-02-15 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Field effect transistor with increased carrier mobility
US7923785B2 (en) 2003-08-18 2011-04-12 Globalfoundries Inc. Field effect transistor having increased carrier mobility

Also Published As

Publication number Publication date
JPH0579189B2 (en) 1993-11-01

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