JPS62234296A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To optimize the timing of writing and erasing in accordance with individual devices by making variable the frequency of an oscillator to set the writing and erasing time in an electrically erasable ROM cell. CONSTITUTION:A ring oscillator loop-links the inverter group of the odd number step and is composed of this, non-volatile memory transistor groups 6-6'' and capacities 7-7'' linked to this. An optimum writing erasing cycle time in accordance with the manufactured element is known beforehand while the clock is put from an external part to an input/output terminal 3. So as to be the same as the frequency, transistor groups 6-6'' are programmed. Thus, the oscillating frequency in accordance with the capacities 7-7'' is selected, frequency-divided by a frequency-divider 4, made into an output 5 and the optimum timing of the writing, and erasing is set.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory device having an internal oscillation circuit that determines the timing of a nonvolatile memory that can be electrically written and erased.

BACKGROUND OF THE INVENTION In recent years, electrically erasable nonvolatile memories have been used more widely because of their ease of use and higher functionality than ultraviolet erasable nonvolatile memories.

In particular, recent non-volatile memories have a function that when data to be written is added, the existing data in the memory cell is erased and the added new data is written, so that it can be used like a random access memory. It's starting to look like this. Since a memory cell such as this requires timing on the order of milliseconds for "writing" or "erasing", it is necessary to create this timing within the semiconductor memory device. At this time, for setting this timing, a method is adopted in which a ring oscillation circuit is used to oscillate, and the frequency of the clock is divided to determine the necessary time.

Problems to be Solved by the Invention In the conventional example, the writing and erasing times of memory cells were set at the design stage, so that all elements had the same cycle time. Therefore, for a device that can be written and erased at high speed, there is wasted time, and on the other hand, a device that takes a little time to write and erase may become defective. Furthermore, not only variations in the characteristics of the memory cells but also variations in the oscillation circuit itself are added, which limits design and manufacturing margins. The present invention aims to solve the above problems.

Means for Solving the Problem of Interval Roughness The present invention provides a semiconductor device that includes a ring oscillator that generates the primary oscillation that determines the write/erase time of a memory cell, and a capacitor group with a switch that can variably set the oscillation frequency. It is a storage device.

According to the present invention, the required oscillation frequency can be freely programmed and obtained by selecting the capacitance.
Optimal timing can be set according to each individual semiconductor memory device.

Embodiment FIG. 1 is an embodiment showing the configuration of an internal oscillation circuit according to the present invention. 1 is a ring oscillator, 2 is a capacitive nonvolatile memory group, 3 is an input/output terminal, 4 is a frequency divider, and 6 is an output signal terminal that determines write/erase timing. Oscillation is generated by the ring oscillator 1, and an optimized frequency can be obtained by selectively determining each capacitance coupled to the nonvolatile memory group 2 as necessary and freely programming it. FIG. 2 is a specific example of the block diagram of FIG. 1, in which the ring oscillator is a loop combination of a group of odd-numbered inverters, and a plurality of nonvolatile memory transistors 6, 6'.

. . 6" and capacitances (capacitors) 7.7', . . . 7" coupled by these. The optimal write/erase cycle time according to the performance of the fabricated element is known in advance by inputting a clock externally to the input/output terminal 3, and the nonvolatile memory transistor group e, Program e', . . . 6'. As a result, the oscillation frequency is selected according to the capacitances 7.7', . Data writing and erasing operations can be ensured at that timing.

Effects of the Invention As described above, according to the present invention, optimum write/erase timing can be created in a semiconductor memory device with a simple circuit configuration, and is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of one embodiment of the present invention. 7.7', 7'...capacitance serving as a load for the ring oscillator.

Claims (1)

[Claims] Erasable and electrically erasable nonvolatile semiconductor memory
A semiconductor memory device comprising an internal oscillation circuit that determines write timing, and a capacitor group with a selection switch that can variably set the oscillation frequency of the internal oscillation circuit.