JPS62233961A - Pb dial interface circuit - Google Patents

Pb dial interface circuit

Info

Publication number
JPS62233961A
JPS62233961A JP7760586A JP7760586A JPS62233961A JP S62233961 A JPS62233961 A JP S62233961A JP 7760586 A JP7760586 A JP 7760586A JP 7760586 A JP7760586 A JP 7760586A JP S62233961 A JPS62233961 A JP S62233961A
Authority
JP
Japan
Prior art keywords
circuit
dial
power supply
interface circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7760586A
Other languages
Japanese (ja)
Inventor
Kenji Munakata
宗像 健二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7760586A priority Critical patent/JPS62233961A/en
Publication of JPS62233961A publication Critical patent/JPS62233961A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To decrease remarkably the delay in the signal transmission and the momentary interruption of a line at PB sending by operating a voltage comparator circuit at PB dialing so as to short-circuit of a resistor of a CR balanced power supply circuit. CONSTITUTION:Resistors R1, R2, a side tone balancing circuit network 3, a reception amplifier 7, a voltage comparator circuit 8, an electronic switch circuit (ES) 9 and a transmission amplifier 4 are connected to line terminals (LA, LB) l, 2 and an output voltage VT' of a power supply circuit (N) 43 is fed as a DC power supply for a PB dial interface circuit 5 and a PB dial oscillator 6. In depressing a dial at PB dialing, a level of a terminal M is made active, a transistor (TR) T6 is turend on, a differential circuit comprising TRs T2-T5 is operated, a TR T1 of the ES 9 is turned on to short-circuit R3 thereby quickening the charging to a capacitor C, the output voltage VT' of the circuit N 43 rises to turn off the ES 9. Thus, the leading of the voltage between the terminals LA1 and LB2 is quickened by decreasing the line momentary interruption time.

Description

【発明の詳細な説明】 し産業上の利用分野〕 本発明はPBダイヤルインタフェース回路に関し、特に
PBダイヤルインタフェース回路付通話回路網において
PBダイヤル発信時の発振特性を改善するPBダイヤル
インタフェース回路に関する4 〔従来の技術〕 従来、この種のPBダイヤルインタフェース回路では、
PBダイヤル発信回路として市販のPBダイヤル集積回
路を使用するため、PBダイヤル信時は通話時よりも電
源電圧を高くする必要がある。
[Detailed Description of the Invention] Field of Industrial Application] The present invention relates to a PB dial interface circuit, and more particularly to a PB dial interface circuit that improves the oscillation characteristics when making a PB dial call in a telephone network with a PB dial interface circuit. Conventional technology] Conventionally, in this type of PB dial interface circuit,
Since a commercially available PB dial integrated circuit is used as the PB dial transmission circuit, it is necessary to use a higher power supply voltage when making a PB dial call than when making a call.

第2図は従来のダイヤルインタフェース回路付通話回路
網の一例を示す回路図、第3図(a)は第2図における
発信時の線路端子間の波形図である4第2図において、
線路端子く以下LA、LB)1.2には抵抗R1,抵抗
R2および側音平衡回路網(以下Z)3か直列に接続さ
れ、この抵抗R2とR2の接続点とLB2との間に送話
用増幅器(以下TA)4が接続される。TA4は出力増
幅器(以下A1)40と前段増幅器(以下A2)41と
、ス・イッチ(以下5W)42と、CR平滑回路による
電源回路(以下N)43とからなる。
FIG. 2 is a circuit diagram showing an example of a conventional telephone communication network with a dial interface circuit, and FIG. 3(a) is a waveform diagram between line terminals during transmission in FIG. 2.
A resistor R1, a resistor R2, and a sidetone balancing circuit (hereinafter referred to as Z) 3 are connected in series to the line terminals (LA, LB) 1.2, and a signal is sent between the connection point of the resistors R2 and R2 and LB2. A speech amplifier (hereinafter referred to as TA) 4 is connected. TA4 consists of an output amplifier (hereinafter referred to as A1) 40, a pre-stage amplifier (hereinafter referred to as A2) 41, a switch (hereinafter referred to as 5W) 42, and a power supply circuit (hereinafter referred to as N) 43 using a CR smoothing circuit.

N43は抵抗R3とコンデンサCにより構成され、その
出力電圧■□゛がA241とPBダイヤルインタフェー
ス回路(以下PI)5およびPBダイヤル発振!i1(
以下osc)6の直流電源(VC,:〉として供給され
る。5W42は前記出力電圧v丁′とA241の電源端
子に接続され通常はオン状態であるが、PBダイヤル発
信時は03C6が動作するとそのM端子がオンとなり5
W42はオフ状態となってA241への電源供給を止め
る。
N43 is composed of resistor R3 and capacitor C, and its output voltage ■□゛ is connected to A241, PB dial interface circuit (hereinafter referred to as PI) 5, and PB dial oscillation! i1(
5W42 is connected to the output voltage V' and the power terminal of A241 and is normally in the on state, but when 03C6 is activated when making a PB dial call. The M terminal is turned on and 5
W42 turns off and stops supplying power to A241.

さらにLAI、LB2の間には受話用増幅器(以下RA
 ) 7が定電流源■を介して接続され、PI5の出力
0は送話のA+40の入力に接続される。
Furthermore, a receiving amplifier (hereinafter referred to as RA) is installed between LAI and LB2.
) 7 is connected via a constant current source ■, and the output 0 of PI5 is connected to the input of transmitter A+40.

ここでPBダイヤル発信状態にすると、os06の動作
でそのM端子がオンとなり5W42がオフとなって前記
出力電圧VT゛はPI5と0SC6に1%給され、PB
ダイヤル信号はPI5.A+40を通してLAN、LB
2間に送出される。OS (E ()として市販のLS
Iを使用すると、その出力信号の安定化のためには前記
出力電圧VT°が3V以上必要であり、通話時よりら高
くなる。本例ではl) B発振時に直流特性が変化する
際、前記出力電圧VT°の上昇まで抵抗R3を通してコ
ンデンサCに充電するまでの間、PI5の出力か安定化
せず、PBダイヤル押下からPI5の出力0が発生する
まで数msかかり、LAI、LB2間の波形は第3図(
a)に示すように一時瞬断し、安定出力を得るまでに数
msの遅れが生じる。
Here, when the PB dial is set to the transmission state, the M terminal is turned on by the operation of os06, 5W42 is turned off, and the output voltage VT' is 1% supplied to PI5 and 0SC6, and the PB dial is turned on.
The dial signal is PI5. LAN, LB through A+40
It will be sent out between 2. LS commercially available as OS (E ())
When I is used, the output voltage VT° needs to be 3V or more in order to stabilize the output signal, which is higher than during a call. In this example, l) When the DC characteristics change during B oscillation, the output of PI5 does not stabilize until the capacitor C is charged through the resistor R3 until the output voltage VT° rises, and the output of PI5 does not stabilize after the PB dial is pressed. It takes several ms until the output 0 occurs, and the waveform between LAI and LB2 is shown in Figure 3 (
As shown in a), there is a momentary interruption and a delay of several milliseconds occurs before stable output is obtained.

〔′発明が解決しようとする問題点〕['Problem that the invention seeks to solve]

上述した従来のPBダイヤルインタフェース回路付通話
回路網では、PBダイヤル発信時に直流特性か」−昇し
、PB発信出力可能な電圧レベルに達するまで、PBダ
イヤルインタフェース回路および送話用増幅器の電源回
路のコンデンサへの充電に時間がかかり、ダイヤルスイ
・ソチ押下がら数msの間口線か瞬断するので、交換機
によっては誤動作することかある欠点がある。
In the above-mentioned conventional communication circuit network with a PB dial interface circuit, when a PB dial is made, the DC characteristic increases, and the power supply circuit of the PB dial interface circuit and the transmitting amplifier is It takes time to charge the capacitor, and there is a momentary disconnection of the front line for a few milliseconds when the dial switch is pressed, so some exchanges may malfunction.

r問題点を解決するための手段〕 本発明のPBダイヤルインタフェース回路は、送話用増
幅器と受話用増幅器とPBダイヤルインタフェース回路
とを備え、2個の線路端子間の2個の抵抗と側音平衡回
路網が直列に接続され、前記2個の抵抗の接続点と前記
側音平衡回路網と線路端子との接続点の間に前記送話用
増幅器とPBダイヤルインタフェース回路の出力および
電源回路か接続された1〕Bダイヤルインタフ工−ス回
路付通話回路において、前記線路端子間に接続された電
圧比較回路と、前記2個の抵抗の接続点と電源回路出力
端子間に電子スイッチ回路が並列に接続された電子スイ
ッチ回路とを備え、前記電圧比較回路の入力および出力
にそれぞれ前記電源回路の出力および前記電子スイッチ
回路の入力が接続されている。
Means for Solving Problems] The PB dial interface circuit of the present invention includes a transmitting amplifier, a receiving amplifier, and a PB dial interface circuit, and has two resistances between two line terminals and a sidetone A balanced circuit network is connected in series, and the transmitting amplifier and the output of the PB dial interface circuit and the power supply circuit are connected between the connection point of the two resistors and the connection point of the sidetone balance network and the line terminal. In the connected 1] B dial interface circuit with communication circuit, an electronic switch circuit is connected in parallel between the voltage comparison circuit connected between the line terminals, the connection point of the two resistors, and the power supply circuit output terminal. An output of the power supply circuit and an input of the electronic switch circuit are connected to the input and output of the voltage comparison circuit, respectively.

〔実施例] 次に、本発明について図面を参照して説明する。〔Example] Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示すPBダイヤルインタフ
ェース回路付通話回路網の回路図、第3図(1))は第
1図における発信時の線路端子間の波形図である。
FIG. 1 is a circuit diagram of a telephone communication network with a PB dial interface circuit showing an embodiment of the present invention, and FIG. 3 (1)) is a waveform diagram between line terminals during a call in FIG. 1.

第1図において、従来例と同じ構成要件には第2図と同
じ符号を付して説明を省略する。本実施例は従来例にト
ランジスタT2.〜T5からなる差動回路、スイッチト
ランジスタT6.比較電源を構成するダイオードD1〜
D9.抵抗R5,R6からなる電圧比較回路(以下VC
O)8と、トランジスタT1.フローティング防止用の
抵抗R4からなる電子スイ・ソチ回路(以下ES)9を
付加してなる。
In FIG. 1, the same components as in the conventional example are given the same reference numerals as in FIG. 2, and their explanations will be omitted. This embodiment is based on the conventional example of transistor T2. ~T5, a differential circuit consisting of a switch transistor T6. Diode D1 that constitutes the comparison power supply
D9. A voltage comparison circuit (hereinafter referred to as VC) consisting of resistors R5 and R6
O)8 and transistor T1. An electronic switch circuit (hereinafter referred to as ES) 9 consisting of a resistor R4 for preventing floating is added.

PI3発信時にダイヤルを押下すると、M端子がオンで
トランシタT6がオンしてトランジスタT2、T3の差
動回路が動作する。、ダイヤル押下時はN43の出力電
圧VT゛は通話状態を維持するため2■程度であり、I
−ランジスタT3側に電流か7fnれ、BS9のトラン
・ジスタT1がオンして抵抗R8を短絡し、コンデンサ
C/\の充電を早め前記出力電圧vT”の上昇を早める
。該出力電圧7丁’ カ上昇シテVT ” > VB 
 (約3.25V)となると、前記差動回路はトランジ
スタT21!]!Iに電流が流れるのでES9はオフす
る。従ってダイヤル押下時のLAI、LB2間の電圧は
第3図(b)に示すようになり、従来の回路に比べて回
線瞬断時間が短縮され立上がりが早くなる。
When the dial is pressed when transmitting PI3, the M terminal is turned on, transistor T6 is turned on, and the differential circuit of transistors T2 and T3 is operated. , when the dial is pressed, the output voltage VT' of N43 is about 2■ to maintain the talking state, and I
- A current of 7fn is applied to the transistor T3 side, and the transistor T1 of BS9 is turned on to short-circuit the resistor R8, accelerating the charging of the capacitor C/\ and hastening the rise of the output voltage vT''. Power rise VT” > VB
(approximately 3.25V), the differential circuit has a transistor T21! ]! Since current flows through I, ES9 is turned off. Therefore, when the dial is pressed, the voltage between LAI and LB2 becomes as shown in FIG. 3(b), and the instantaneous line interruption time is shortened and the voltage rises quickly compared to the conventional circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、Paダイヤル発信時に電
圧比較回路を動作させCR平衡電源回路の抵抗を短絡す
ることにより、通話時の直流状態からPaダイヤル発信
時の直流状態へのスピードア・ソアを計り、PB発信時
の回線の瞬断および信号送出の遅れを大幅に短縮する効
果がある。
As explained above, the present invention operates the voltage comparator circuit when making a Pa dial call and short-circuits the resistance of the CR balanced power supply circuit, thereby speedily changing the DC state from the DC state during a call to the DC state when making a Pa dial call. This has the effect of significantly reducing line interruptions and signal transmission delays during PB transmission.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すPBダイヤルインタフ
ェース回路付通話回路網の回路図、第2図は従来のPB
ダイヤルインタフェース回路付通話回路網の一例を示す
回路図、第3図(a>、(1つ)はそれぞれ第1図、第
2図における発信時の線路端子間の波形図である。 1.2・・・線路端子(LA、LB)、3・0.側音平
衡回路網(Z)、4・・・送話用増幅器(TA)−5・
・・PBダイヤルインタフェース回路(PI)、6・・
・P Bダイヤル発振器(O3C)、7・・・受話用増
器(RA>、8・・・電圧比較回路(■CO)、9・・
・電子スイッチ回路(ES>、40・・・出力増幅器(
AI)、41・・・前段増幅器(A2)、42・・・ス
イッチ(SW) 、43・・・電源回路(N)、C・・
・コンデンサ、■)1.〜D、・・・グイオート、■・
・・定電流源、R1,〜R6・・・抵抗、T1.〜T5
・・・トランジスタ、T6・・・スイッチトランジスタ
Fig. 1 is a circuit diagram of a telephone network with a PB dial interface circuit showing an embodiment of the present invention, and Fig. 2 is a circuit diagram of a conventional PB dial interface circuit.
A circuit diagram showing an example of a telephone communication network with a dial interface circuit, and FIG. 3 (a> and (one)) are waveform diagrams between line terminals during transmission in FIGS. 1 and 2, respectively. 1.2 ...Line terminal (LA, LB), 3.0. Sidetone balance circuit network (Z), 4.Talking amplifier (TA)-5.
...PB dial interface circuit (PI), 6...
・P B dial oscillator (O3C), 7... Receiving amplifier (RA>, 8... Voltage comparison circuit (■CO), 9...
・Electronic switch circuit (ES>, 40...output amplifier (
AI), 41... Pre-stage amplifier (A2), 42... Switch (SW), 43... Power supply circuit (N), C...
・Capacitor, ■)1. 〜D、・・・Guioto、■・
・・Constant current source, R1, ~R6 ・・Resistor, T1. ~T5
...transistor, T6...switch transistor.

Claims (1)

【特許請求の範囲】[Claims] 送話用増幅器と受話用増幅器とダイヤルインタフェース
回路とを備え、2個の線路端子間に2個の抵抗と側音平
衡回路網が直列に接続され、前記2個の抵抗の接続点と
前記側音平衡回路網と線路端子との接続点の間に前記送
話用増幅器とPBダイヤルインタフェース回路の出力お
よび電源回路が接続されたPBダイヤルインタフェース
回路付通話回路網において、前記線路端子間に接続され
た電圧比較回路と、前記2個の抵抗の接続点と電源回路
出力端子間に電子スイッチ回路が並列に接続された電子
スイッチ回路とを備え、前記電圧比較回路の入力および
出力にそれぞれ前記電源回路の出力および前記電子スイ
ッチ回路の入力が接続されてなることを特徴とするPB
ダイヤルインタフェース回路。
A transmitting amplifier, a receiving amplifier, and a dial interface circuit are provided, and two resistors and a sidetone balancing circuit are connected in series between two line terminals, and a connection point between the two resistors and a side tone balancing circuit are connected in series between two line terminals. In a communication circuit network with a PB dial interface circuit, in which the transmitting amplifier and the output and power supply circuit of the PB dial interface circuit are connected between the connection points between the sound balance circuit network and the line terminals, and an electronic switch circuit in which an electronic switch circuit is connected in parallel between the connection point of the two resistors and the power supply circuit output terminal, and the power supply circuit is connected to the input and output of the voltage comparison circuit, respectively. A PB characterized in that the output of the electronic switch circuit and the input of the electronic switch circuit are connected to each other.
Dial interface circuit.
JP7760586A 1986-04-03 1986-04-03 Pb dial interface circuit Pending JPS62233961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7760586A JPS62233961A (en) 1986-04-03 1986-04-03 Pb dial interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7760586A JPS62233961A (en) 1986-04-03 1986-04-03 Pb dial interface circuit

Publications (1)

Publication Number Publication Date
JPS62233961A true JPS62233961A (en) 1987-10-14

Family

ID=13638560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7760586A Pending JPS62233961A (en) 1986-04-03 1986-04-03 Pb dial interface circuit

Country Status (1)

Country Link
JP (1) JPS62233961A (en)

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