JPS62231535A - Digital signal processing system - Google Patents
Digital signal processing systemInfo
- Publication number
- JPS62231535A JPS62231535A JP7491286A JP7491286A JPS62231535A JP S62231535 A JPS62231535 A JP S62231535A JP 7491286 A JP7491286 A JP 7491286A JP 7491286 A JP7491286 A JP 7491286A JP S62231535 A JPS62231535 A JP S62231535A
- Authority
- JP
- Japan
- Prior art keywords
- error correction
- signal processing
- bit
- time slot
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 title claims abstract description 30
- 238000012937 correction Methods 0.000 claims abstract description 33
- 238000006243 chemical reaction Methods 0.000 claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 238000004891 communication Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 238000003672 processing method Methods 0.000 claims description 4
- 108010076504 Protein Sorting Signals Proteins 0.000 claims description 3
- 238000003780 insertion Methods 0.000 abstract description 2
- 230000037431 insertion Effects 0.000 abstract description 2
- 238000012544 monitoring process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はディジタル信号処理方式に関し、特にブロック
符号を用いて誤り訂正を行うディジタル無線通信回線の
ディジタル信号処理方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing system, and particularly to a digital signal processing system for a digital wireless communication line that performs error correction using block codes.
ディジタル伝送の発達普及に伴い、多値直交振幅変調（
１６ＱＡＭ、６４ＱＡＭ方式等）を用いた高能率ディジ
タル無線通信回線が実用化され、雑音に対するビットｖ
Ａｂ率の改善を目的として誤り訂正符号化方式（Ｆｏｒ
ｗａｒｄ Ｅｒｒｏｒ Ｃｏｒｒｅｃｔｉｏｎ）が採用
されるようになってきた。マイクロ波帯等のディジタル
無線通信回線においては、送信端局側の符号変換器でデ
ィジタル多重化端局装置から入力されたバイポーラ信号
をユニポーラ信号に変換したのち、送信信号処理装置で
速度変換を行って無線回線の監視および制御に必要なフ
レーム同期信号、監視制御信号、パリティチェック信号
等の付加ビットを挿入して伝送し、受信端局側では受信
信号処理装置で上記の付加ビットの情報を抽出したのち
、逆速度変換を行って入力信号と同じビットレートのユ
ニポーラ信号を復元し、これを符号変換してバイポーラ
信号としてディジタル多重化端局装置に送シ出す操作が
行われている。このようなディジタル無線通信回線に誤
）訂正符号化方式を導入するに当って、従来は送信端局
側の送信信号処理装置の出力に誤り訂正符号化装置（ｌ
Ｉ′ＥＣエンコーダ）を接続し、ここで速度変換され付
加ビットを含む信号を一定ビット長のブロックに分割し
、分割された一定ビット長のブロックを情報ビットとし
て処理し、情報ビットに誤り訂正に必要な誤り訂正符号
を付加してブロック符号化して伝送し、受信端局側では
受信信号処理装置の前に挿入された誤り訂正復号装置（
ＦＥＣデコーダ）でｖＡｂ訂正を行い、付加された誤り
訂正符号を除いた情報ビットのみを送り出し、この情報
ビットから受信信号処理装置で無線回線監視用の付加ビ
ットを除去してデータ信号のみを復元する構成がとられ
ている。With the development and spread of digital transmission, multilevel quadrature amplitude modulation (
High-efficiency digital wireless communication lines using 16QAM, 64QAM, etc.) have been put into practical use, and bit v
Error correction coding method (For
ward error correction) has come to be adopted. In digital wireless communication lines such as microwave bands, a code converter on the transmitting terminal side converts the bipolar signal input from the digital multiplexing terminal equipment into a unipolar signal, and then a transmitting signal processing device performs speed conversion. additional bits such as frame synchronization signals, supervisory control signals, parity check signals, etc. necessary for monitoring and controlling the wireless line are inserted and transmitted, and at the receiving end station, information on the above additional bits is extracted by a receiving signal processing device. Thereafter, reverse speed conversion is performed to restore a unipolar signal with the same bit rate as the input signal, and this is code-converted and sent to the digital multiplexing terminal equipment as a bipolar signal. When introducing an error correction coding system to such a digital wireless communication line, conventionally an error correction coding device (l
I'EC encoder), which divides the speed-converted signal containing additional bits into blocks of a constant bit length, processes the divided blocks of constant bit length as information bits, and applies error correction to the information bits. The necessary error correction code is added, block coded and transmitted, and the receiving terminal station uses an error correction decoding device (
FEC decoder) performs vAb correction, sends out only the information bits without the added error correction code, and from these information bits, the received signal processing device removes the additional bits for wireless line monitoring and restores only the data signal. The structure is taken.
上述したように、誤り訂正符号化方式を採用した従来の
ディジタル信号処理方式では、送イｄ端局側の送信信号
処理装置において−たん速度変換を行って無線回線監視
用の付加ビットを挿入したのち、’）：”ＥＣエンコー
ダで再び速度変換を行って県シ訂正符号を挿入するとい
う２段階の速就変換を行っている。従って、速度変換に
必要な電圧制御発振器（ＶＣＯ）やカウンタなどの回路
が両装置に重複して設けられておシ、同様な回路が二重
に存在し構成が複雑で不経済であるとい９問題点がある
。受信端局側においても同様であり、ＦＥＣデコーダと
受信信号処理装置とに同様な速度変換用の回路が重複し
て存在するという問題点かある。As mentioned above, in conventional digital signal processing systems that employ error correction coding, the transmitting signal processing device at the transmitting end station performs speed conversion and inserts additional bits for wireless line monitoring. Afterwards, '):'' A two-step speed conversion is performed in which the speed is converted again using the EC encoder and a prefecture correction code is inserted. Therefore, the voltage controlled oscillator (VCO), counter, etc. necessary for speed conversion are There are 9 problems in that the same circuits are duplicated in both devices, and the configuration is complicated and uneconomical.The same is true on the receiving terminal side, and FEC There is a problem in that similar speed conversion circuits are redundantly present in the decoder and the received signal processing device.
このような問題点は、無線回線監視用の付加ビットを挿
入する周期（無線フレーム長）とブロック符号化のため
のブロック長との関係を適当に選定すれば除去すること
が可能である。Such problems can be eliminated by appropriately selecting the relationship between the period of inserting additional bits for radio channel monitoring (radio frame length) and the block length for block encoding.
本発明の目的は、無線フレーム長とブロック長を例えは
同一に選定し、無線回線監視用の付加ビットと誤し訂正
符号用の冗長ビットのタイムスロットとを１回の速度変
換によ）同時に挿入または除去することにより、速度変
換用のＶＣＯ，カウンタ等の回路の重複を除去した経済
的なディジタル信号処理方式を提供することである。The object of the present invention is to select the radio frame length and the block length to be the same, and simultaneously convert the additional bits for radio line monitoring and the time slots of redundant bits for error correction code (by one speed conversion). It is an object of the present invention to provide an economical digital signal processing system in which duplication of circuits such as VCOs and counters for speed conversion is eliminated by insertion or removal.
本発明のディジタル信号処理方式は、情報ビットに誤り
訂正符号を付加したブロック符号を用いて誤り訂正を行
うディジタル無線通信回線のディジクル信号処理方式に
おいて、送信端局が６人力データ信号に速度変換を施し
て無線回線監視用の付加ビットと前記誤り訂正符号用の
タイムスロットとを付加した送信ディジタル信号列を発
生する送信信号処理装置と、この送信信号処理装置の出
力に接続され前記送信ディジタル信号列のうち前記タイ
ムスロットを除いた部分を前記情報ビットとして処理し
前記誤り訂正符号を作成して前記タイムスロットに挿入
し前記ブロック符号を送出する誤り訂正符号化装置とを
備え、受信端局が、受信復調された前記ブロック符号を
復号し誤り訂正された前記情報ビットに前記タイムスロ
ットが付加された受信ディジタル信号列を出力する誤り
訂正復号装置と、このｔＡシ訂正復号装置の出力に接続
され逆速度変換を行って前記付加ビットおよび前記タイ
ムスロットを除去して前記入力データ１ご号を＠元送出
する受信信号処理装置とを備えて構成されている。The digital signal processing method of the present invention is a digital signal processing method for a digital wireless communication line that performs error correction using a block code in which an error correction code is added to information bits. a transmission signal processing device that generates a transmission digital signal train to which additional bits for radio line monitoring and a time slot for the error correction code are added; an error correction encoding device that processes a portion of the data excluding the time slot as the information bits, creates the error correction code, inserts it into the time slot, and transmits the block code; an error correction decoding device that decodes the received demodulated block code and outputs a received digital signal sequence in which the time slot is added to the error-corrected information bit; and a received signal processing device that performs speed conversion, removes the additional bits and the time slot, and transmits the input data No. 1.
次に図面を参照して本発明の詳細な説明する。 Next, the present invention will be described in detail with reference to the drawings.
第１図（ａ）及び（ｂ）は本発明の一実施例のブロツク
図、第２図はその動作を説明するだめの谷部の符号構成
図であシ、第１図（ａ）は送信端局側の１５号処理部の
構成を、第１図（ｂ）は受信端局側の信号処理部の構成
を示している。FIGS. 1(a) and (b) are block diagrams of one embodiment of the present invention, FIG. 2 is a block diagram of the code for explaining its operation, and FIG. 1(a) is a block diagram of an embodiment of the present invention. FIG. 1(b) shows the configuration of the No. 15 processing section on the terminal station side, and FIG. 1(b) shows the configuration of the signal processing section on the receiving terminal station side.
第１図（ａ） において、ディジタル多重化端局装置（
図示せず）から送られたバイポーラ信号１０１は、符号
変換器１でユニポーラ信号に変換され送信信号処理装置
２に加えられる。送信信号処理装［２は第２図人に示す
に一１ビットのデータ符号Ｄ１・・・・・・Ｄｋ−、か
ら成る入力データ信号１０２を速度変換し、無線回線監
視用の付加ビットＦを付加すると同時に付加ビットＦの
後に誤り訂正符号用のｎ−に個の冗長ビットのタイムス
ロット（“０”を表示）を挿入し、第２図Ｂに示すｎビ
ットの送信ディジタル信号列１０３をＦＥＣデコーダ３
に送出する。In Figure 1(a), a digital multiplexing terminal equipment (
A bipolar signal 101 sent from a device (not shown) is converted into a unipolar signal by a code converter 1 and applied to a transmission signal processing device 2 . The transmission signal processing device [2 converts the speed of the input data signal 102 consisting of 11-bit data code D1...Dk- as shown in FIG. At the same time, a time slot of n- redundant bits (indicated as "0") for error correction code is inserted after the additional bit F, and the n-bit transmission digital signal string 103 shown in FIG. 2B is subjected to FEC. Decoder 3
Send to.
ＦＥＣデコーダ３は、送信ディジタル信号列１０３のう
ち冗長ビットのタイムスロットヲ除くにビット（データ
信号ＤＩ＋付加ピッ）Ｆ）を情報ビットとし、帰還回路
を有するシフトレジスタから構成される従来公知の符号
化回路で処理して誤り訂正符号Ｐ１〜Ｐｎ−ｋを発生し
、この誤り訂正符号を冗長ビットのタイムスロットに挿
入して第２図ＣＫ示す符号化率ｋ ／ ｎのブロック符
号１０４を送信装置の変調器（図示せず）に送）出す。The FEC decoder 3 uses the bits (data signal DI+additional bits) F) of the transmitted digital signal string 103 except for the time slots of the redundant bits as information bits, and performs conventional encoding consisting of a shift register having a feedback circuit. The circuit generates error correction codes P1 to Pn-k, inserts these error correction codes into redundant bit time slots, and transmits the block code 104 with a coding rate k/n shown in FIG. to a modulator (not shown).
この構成によれば、１回の速度変換によりて無線回線の
監視制御に必要な付加ビットＦと誤υ訂正に必要な誤り
訂正符号ＰＩ％Ｐ、にとを付加することができ、ＦＥＣ
エンコーダには速度変換用のＶＣＯ及びカウンタ回路を
備える必要がなく装置の経済化が達成される。According to this configuration, it is possible to add the additional bit F necessary for wireless line monitoring control and the error correction code PI%P necessary for error υ correction by one speed conversion.
There is no need to provide the encoder with a VCO and a counter circuit for speed conversion, and the device can be made more economical.
第１図（ｂ）に示す受信端局側の構成についても同様で
あり、受信復調されたｎビットのベースバンド信号１０
５（第３図Ｃ）はＦＥＣデコーダ４において復号処理さ
れ、誤り訂正された情報ビットに冗長ビットのタイムス
ロットが付加されたｎビットの受信ディジタル信号列１
０６（第３図Ｂ）として出力される。受信信号処理装置
５はこの信号列から付加ピッ）Ｆの情報を抽出したのち
、逆速度変換を行ってに一１ビットのデータ信号１０７
（第２図人）を出力する。この信号は符号変換器６でバ
イポーラ信号１０８に変換されディジタル多重化端局装
置（図示せず）に送られる。The same applies to the configuration of the receiving terminal station shown in FIG. 1(b), where the received and demodulated n-bit baseband signal 10
5 (FIG. 3C) is an n-bit received digital signal string 1 which has been decoded by the FEC decoder 4 and has a redundant bit time slot added to the error-corrected information bits.
06 (Figure 3B). The received signal processing device 5 extracts the information of the additional bit F from this signal string, performs reverse speed conversion, and generates an 11-bit data signal 107.
(Figure 2 person) is output. This signal is converted into a bipolar signal 108 by the code converter 6 and sent to a digital multiplexing terminal equipment (not shown).
上述の実施例においては、一つの２値入力デ一タ信号に
ついてのみ説明したが、例えば１６ＱＡＭの場合には４
系列の２値デ一タ信号が送信装置の変調器に入力され、
それぞれに同様の回路が設けられる。又、上述の説明で
は、無線回線監視用の付加ビットＦを挿入する無線フレ
ーム長をブロック符号化のブロック長と一致するよう選
んだ場合について述べたが、ブロック長を２無線フレー
ム又はそれ以上に選定しても同様な構成が可能である。In the above embodiment, only one binary input data signal was explained, but for example, in the case of 16QAM, 4
A series of binary data signals are input to a modulator of a transmitter,
A similar circuit is provided for each. Furthermore, in the above explanation, the case was described in which the length of the radio frame into which the additional bit F for radio line monitoring is inserted was selected to match the block length of block encoding. A similar configuration is possible even if selected.
なお、上述の説明では省略したか、送信信号処理装置お
よび受信信号処理装置において入力データ信号にスクラ
ンブル及びデスクランブル処理を行う構成としても差支
えない。Although omitted in the above description, it is also possible to adopt a configuration in which scrambling and descrambling processing is performed on the input data signal in the transmission signal processing device and the reception signal processing device.
以上詳細に説明したように、本発明のディジタル信号処
理方式によれば、無線回想監視用の付加ビットとブロッ
ク符号化のだめの冗長ビットのタイムスロットの挿入を
同時に行うため、速度変換に必要なＶＣＯやカウンタ等
の回路を２重に設ける必要がなく、装置の経済化が達成
できるという効果がある。As explained in detail above, according to the digital signal processing method of the present invention, time slots for additional bits for wireless retrospective monitoring and redundant bits for block encoding are inserted simultaneously, so that the VCO required for speed conversion is There is no need to provide duplicate circuits such as circuits and counters, and there is an effect that the device can be made more economical.
第１図（ａ）は本発明の一実施例の送信端局側の信号処
理部のブロック図、第１図Φ）は本発明の一実施例の受
信端局側の信号処理部のブロック図、第２図は第１図（
ａ）及び（ｂ）の動作を説明するための符号構成図であ
る。
１．６・・・・・・符号変換器、２・・・・・・送（Ｈ
化°号処理装置、３・・・・・・ＦＥＣエンコーダ、４
・・・・・・Ｆ Ｅ Ｃｆコーグ、５・・・・・・受信
信号処理装置。FIG. 1(a) is a block diagram of a signal processing section on the transmitting terminal station side according to an embodiment of the present invention, and FIG. 1(Φ) is a block diagram of a signal processing section on the receiving terminal station side according to an embodiment of the present invention. , Figure 2 is the same as Figure 1 (
It is a code|symbol block diagram for demonstrating the operation|movement of a) and (b). 1.6... code converter, 2... sending (H
Code processing device, 3...FEC encoder, 4
...F E Cf Korg, 5... Reception signal processing device.
Claims (1)
いて誤り訂正を行うディジタル無線通信回線のディジタ
ル信号処理方式において、送信端局が、入力データ信号
に速度変換を施して付加信号用の付加ビットと前記誤り
訂正符号用のタイムスロットとを付加した送信ディジタ
ル信号列を発生する送信信号処理装置と、この送信信号
処理装置の出力に接続され前記送信ディジタル信号列の
うち前記タイムスロットを除いた部分を前記情報ビット
として処理し前記誤り訂正符号を作成して前記タイムス
ロットに挿入し前記ブロック符号を送出する誤り訂正符
号化装置とを備え、受信端局が、受信復調された前記ブ
ロック符号を復号し誤り訂正された前記情報ビットに前
記タイムスロットが付加された受信ディジタル信号列を
出力する誤り訂正復号装置と、この誤り訂正復号装置の
出力に接続され逆速度変換を行って前記付加ビットおよ
び前記タイムスロットを除去して前記入力データ信号を
復元送出する受信信号処理装置とを備えたことを特徴と
するディジタル信号処理方式。In a digital signal processing method for a digital wireless communication line that performs error correction using a block code in which an error correction code is added to information bits, a transmitting terminal station performs speed conversion on an input data signal and converts it into additional bits for an additional signal. a transmission signal processing device that generates a transmission digital signal sequence to which the time slot for the error correction code is added; and a transmission signal processing device that is connected to the output of the transmission signal processing device and generates a portion of the transmission digital signal sequence excluding the time slot. an error correction encoding device that processes the information bits, creates the error correction code, inserts it into the time slot, and transmits the block code, and a receiving terminal station decodes the received and demodulated block code. an error correction decoding device that outputs a received digital signal string in which the time slot is added to the error-corrected information bits; A received signal processing device that removes slots to restore and transmit the input data signal.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7491286A JPS62231535A (en) | 1986-03-31 | 1986-03-31 | Digital signal processing system |
| EP87104681A EP0244629B1 (en) | 1986-03-31 | 1987-03-30 | Radio transmission system having simplified error coding circuitry and fast channel switching |
| DE87104681T DE3788532T2 (en) | 1986-03-31 | 1987-03-30 | Radio transmission system with simplified error correction circuit and fast channel switching. |
| AU70903/87A AU605142B2 (en) | 1986-03-31 | 1987-03-31 | Radio transmission system having simplified error coding circuitry and fast channel switching |
| CA000533414A CA1278828C (en) | 1986-03-31 | 1987-03-31 | Radio transmission system having simplified error coding circuitry and fast channel switching |
| US07/032,645 US4862457A (en) | 1986-03-31 | 1987-03-31 | Radio transmission system having simplified error coding circuitry and fast channel switching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7491286A JPS62231535A (en) | 1986-03-31 | 1986-03-31 | Digital signal processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62231535A true JPS62231535A (en) | 1987-10-12 |
Family
ID=13561070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7491286A Pending JPS62231535A (en) | 1986-03-31 | 1986-03-31 | Digital signal processing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62231535A (en) |
-
1986
- 1986-03-31 JP JP7491286A patent/JPS62231535A/en active Pending
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