JPS6222476A - Manufacture of bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To enable a bipolar semiconductor device to have sufficiently high dielectric strength even if the substrate has a low resistivity and to improve the degree of integration and the electric characteristics of the device, by providing islands on which a high dielectric strength element and a low dielectric strength element are to be formed, respectively, and forming an N-type layer on the whole surface of the semiconductor substrate such that a P-type layer is present under the N-type layer only in the island for high dielectric element region. CONSTITUTION:An oxide film 13 is provided and patterned on a P-type layer 12. The first alkali etching is carried out so that a P<+> type layer is removed in the regions where low dielectric strength elements are to be formed, and the oxide film 13 is further removed. After that, another oxide film 14 is newly provided and patterned. The second alkali etching is carried out so that V-shaped grooves 15 are formed so as to provide island regions having different heights. An oxide film 17 is provided on the whole surface of an N<+> type buried layer 16 and a polysilicon layer 18 is deposited so as to have a thickness similar to that of the semiconductor substrate 11. The semiconductor substrate 11 is polished or etched from the surface opposite to the principal surface thereof until the tip ends of the V-shaped grooves 16 are exposed. Thus, the semiconductor substrate 11 is provided with the island regions having different heights and isolated by the dielectric within the same chip. Then, P-type and N-type regions are formed, and finally electrodes 19 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a bipolar semiconductor device in which a high breakdown voltage element and a low breakdown voltage element are mounted on the same chip.

(Prior Art) Generally, in order to form a high breakdown voltage element on a dielectric isolation substrate, it is necessary to form a deep island for the element on a high resistivity substrate. When these high-voltage elements and low-voltage elements are mounted on the same chip, it is necessary to form an island of low-voltage elements with a different depth from that of the high-voltage elements. This is shown in the publication number, etc. FIG. 2 is a diagram showing a conventional manufacturing method of this type of semiconductor device.
This will be explained below based on the drawings.

After forming an oxide film 2 on the main surface side of an N-type (100) silicon substrate 1, a pattern as shown in FIG. 2(a) is formed by a normal photolithography process. Next, the substrate 1 is etched by, for example, a KOH-based alkaline etching process to form a flat portion 3t of a desired depth, as shown in FIG. After the oxide film 2 is completely removed and a new oxide film 4 is formed, a pattern is formed by ordinary photoetching as shown in FIG. 2(C). Next, using these oxide film patterns as a mask, a V-groove 5 is formed by alkaline etching such as KOI (based on KOI) as shown in FIG. When forming an NPN (NPN) transistor, a donor impurity such as antimony, arsenic, or phosphorus is diffused to reduce the collector resistance, and an N+ layer 6 is formed by thermal diffusion, as shown in FIG. 2(e).

After forming an oxide film 7 on the entire surface of the N layer 6, a polysilicon layer 8 is formed as shown in FIG. 2(f).

Next, the substrate 1 is polished from the opposite side of the main surface until the tips of the grooves 5 are exposed as shown in FIG. 2 (2).

Then, diffusion and electrode formation are performed, and as shown in FIG. 2(G), a semiconductor substrate is formed which has islands of different depths in the low breakdown voltage element region A and the high breakdown voltage element region B within the same chip.

(Problems to be Solved by the Invention) However, in the method for manufacturing a semiconductor device as described above, since a low breakdown voltage element is formed by matching the substrate concentration to a high breakdown voltage element,
In the case of low-voltage devices (e.g. particle NPN) transistors, the collector resistance becomes large and the I-V characteristics (hF
, ), which deteriorates its electrical characteristics.Also, in order to obtain high breakdown voltage characteristics, it is necessary to increase the specific resistance of the substrate, so when a voltage is applied, the depletion layer extends greatly and becomes deep. The need for islands led to poor agglomeration. For example, to satisfy high voltage characteristics of 400V or more, 1
The specific resistance of the substrate is required to be 0Ω-1 or more, and when considering the extension of the depletion layer when a voltage is applied, the depth of the island becomes 50 μm or more, making it impossible to expect an improvement in the degree of integration.

It is an object of the present invention to provide a method for manufacturing a bipolar semiconductor device that eliminates the above-mentioned problems with the electrical characteristics and degree of integration of low breakdown voltage elements and has a high degree of integration and excellent electrical characteristics of low and low breakdown voltage elements. purpose.

(Means for Solving the Problems) The present invention is a method for manufacturing a bipolar semiconductor device, in which a second conductivity type layer is formed using a substrate having a lower resistivity than the substrate conventionally required for high voltage elements. After that, the low breakdown voltage element part is subjected to first anisotropic etching to remove the second conductivity type layer, and second anisotropic etching to form islands for forming high and low breakdown voltage pixel elements. When the first conductivity type layer is formed on the entire surface, the first conductivity type layer is formed only on the island in the high voltage element region.
A second conductivity type layer is formed under the conductivity type layer.

(Function) According to the present invention, as described above, since the second conductivity type layer is formed under the first conductivity type layer only in the island of the high voltage element region, for example, the P type layer and the N By setting the impurity concentration of the type layer to a predetermined concentration and setting the distance between this P-type layer and the P-type layer on the main surface to an appropriate value, the potential difference between the P-type layer and the N-type layer becomes small, and it can be applied to high voltages. The electric field strength does not reach a critical value and the withstand voltage is improved.

For this reason, sufficient high voltage characteristics can be obtained even if the specific resistance of the substrate is lowered, and the electrical characteristics of low voltage devices can be improved, and the extension of the depletion layer when voltage is applied is also reduced, making the island depth shallower. can do.

(Embodiment) FIG. 1 is a diagram showing a method of manufacturing a bipolar semiconductor device according to an embodiment of the present invention, and the following description will be made with reference to FIG. 1.

FIG. 1(a) shows a semiconductor N-type (100) substrate 11 in which an activator impurity such as boron is diffused over the entire main surface to form a P-type layer 12. Here, the impurity concentration of the P-type layer 12 is set to be lower than, for example, 4 x 10" tons/cj or more, since the P-type layer acts as an etching stopper and alkali etching does not proceed (note that this concentration depends on the etching conditions). ). Next,
An oxide film 13 is formed on the P-type layer 12, and patterned as shown in FIG. 1(b) using a normal photolithography process. Then, a first alkali etching is performed to remove the P layer in the low breakdown voltage element region, as shown in FIG. 1(c). Further, after removing the oxide film 13, a new oxide film 14 is formed, and then a pattern is formed by a normal photolithography process as shown in FIG. 1(d). Next, a second alkali etching is performed to form a V-groove 15, thereby forming island regions having different thicknesses as shown in FIG. 1(e). Then, the oxide film 14 is removed and arsenic is removed.

For example, donor impurities such as antimony and phosphorus are diffused in the T infrastructure to form the N+ buried layer 16 as shown in FIG. 1(f).
form. Here, the impurity concentration of the N buried layer 16 is desirably 30Ω/hole or less in terms of sheet resistance. The impurity concentration of the P-type layer is about lXl0" to lXl0" -3, which is the concentration at which a P-type layer is formed under the N buried layer 16 (the concentration that changes the vicinity of the surface of the P" layer to an N layer). ).

Next, an oxide film 17 is formed on the entire surface of the N buried layer 16, and a polysilicon layer 18 is further formed to have the same thickness as the semiconductor substrate 11, as shown in FIG. 1(b). and semiconductor substrate 11
The semiconductor substrate is polished or etched from the opposite side of the main surface until the tip of the V-groove 15 is exposed, thereby producing a semiconductor substrate having dielectrically separated island regions of different thicknesses in the same chip as shown in FIG. Form. Then, by forming a P-type region and an N-type region, and further forming an electrode 19, as shown in FIG.
) A semiconductor device is formed in which a high breakdown voltage element and a low breakdown voltage element are mounted together, in which a P layer exists at the bottom of an island.

Note that in the above example, the islands in the high voltage element area were also etched in the first alkali etching, but this was
It is also possible to etch the high-voltage element area in the second etching without etching the high-voltage element area in the first etching.In the first etching, the P-type layer in the low-voltage element area is etched, and in the second alkali etching, only the islands of the high-voltage element are etched. It is sufficient if the P-type layer remains.

FIG. 3 is a cross-sectional view schematically showing the case where the P layer exists and the case where the P layer does not exist at the bottom of the island. Generally, the withstand voltage is determined by the electric field strength, and when a voltage is applied and the electric field strength exceeds a critical value at a certain point, a current flows and the voltage at that point becomes the withstand voltage. As shown in Figure 3(a), if there is no P layer at the bottom, there is a DPF with a field h-plate electrode.
Even if the electric field at the surface is relaxed by deepening tJ22, P!
The electric field becomes stronger at corner part A of IIj22 and exceeds a critical value even at a low applied voltage. However, when a P layer exists as in the present invention shown in FIG. 2(b), the corner part A
Before reaching the critical value, the depletion layer 26 extending from the second layer 22 collides with the P layer 27 at the bottom, and the depletion layer corresponding to the potential difference with the N layer 21 and 23 at the point of collision becomes the P'' layer 27. A depletion layer 26 as shown by the broken line in FIG. 2(b) extends from
is formed. At this time, the impurity concentrations of the P'' layer 2 upper layer 7 and the N layer 23 are set to the values mentioned above, and the distance glt between the 2nd layer 22 and the P layer 27 is set to an appropriate value, for example, 6
To obtain 00v, set t#20 to 30μm, and P
Since the potential difference between the first layer 27, the N layer 21, and the N+ layer 23 becomes smaller, even if the depletion layer 26 extends to the eighth layer 23 side, the electric field strength does not reach a critical value up to a high voltage, and the withstand voltage improves. Therefore, as mentioned above, in conventional high-voltage/low-voltage hybrid devices, it was necessary to increase the resistivity of the substrate and increase the depth of the islands to match the high-voltage elements in order to obtain high-voltage characteristics. By providing the P'' layer 27 as described above, sufficient high voltage characteristics can be obtained even if the substrate resistivity is reduced, and since there is an N layer on the side, the collector resistance of the low voltage element = h
It is possible to improve electrical characteristics such as FE. Furthermore, as the specific resistance of the substrate becomes smaller, the extension of the depletion layer when a voltage is applied becomes smaller, and as a result, the depth of the island can be made shallower and the degree of integration can be improved.

(Effects of the Invention) As explained above, according to the present invention, islands are formed for forming high-voltage and low-voltage pixel elements, and N is applied to the entire surface of a semiconductor substrate.
When the mold layer was formed, the P-type layer was formed under the N-type layer only in the islands of the high-voltage element region, so that sufficient high-voltage characteristics could be obtained even if the substrate resistivity was lowered. Therefore, the depth of the island can be made shallow, the degree of integration can be improved, and the electrical characteristics of the low voltage element can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a method for manufacturing a bipolar semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a conventional method for manufacturing a bipolar semiconductor device, and FIG. 3(a)
(b) shows P without and with P layer at the bottom, respectively.
FIG. 3 is a cross-sectional view for explaining the shape of a depletion layer when a reverse voltage is applied to the N junction. 11... Semiconductor substrate, 12... P-type layer, 13, 14
17... Insulating film, 15... V groove, 16... N layer, 18... Polycrystalline semiconductor layer, 19... Electrode. Patent Applicant: Oki Electric Industry Co., Ltd. Yato 4 official J Abu no Seishi Rinho) Rice's statement 1
[Facing] Fig. 2 (b) A (Japanese nf'4 1 雛, 1;

Claims (1)

[Claims] 1. (a) Step of forming a second conductivity type layer over the entire main surface of a first conductivity type (100) semiconductor substrate; (b) Anisotropic etching using an insulating film as a mask. conduct,
a step of removing a part of the semiconductor substrate including the second conductivity type layer in a region where a shallow island is to be formed; (c) removing the insulating film and performing anisotropic etching using a new insulating film as a mask; , forming islands of different depths separated by V-grooves; (d) after removing the newly formed insulating film, a first conductivity type layer is formed in waves over the entire main surface including the etched surface; (e) forming an insulating film on the entire main surface side, and forming a polycrystalline semiconductor layer on the insulating film to a thickness comparable to that of the first conductivity type semiconductor substrate; (f) ) removing the first conductivity type semiconductor substrate from the opposite side of the main surface until the V-groove is exposed; (g) removing a second conductivity type or A method for manufacturing a bipolar semiconductor device, comprising the steps of diffusing impurities of a first conductivity type and forming an electrode to form a semiconductor element.