JPS62224031A - Bariation-proof - Google Patents

Bariation-proof

Info

Publication number
JPS62224031A
JPS62224031A JP6571086A JP6571086A JPS62224031A JP S62224031 A JPS62224031 A JP S62224031A JP 6571086 A JP6571086 A JP 6571086A JP 6571086 A JP6571086 A JP 6571086A JP S62224031 A JPS62224031 A JP S62224031A
Authority
JP
Japan
Prior art keywords
insulating film
radiation
semiconductor device
oxide film
electrons
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6571086A
Other languages
Japanese (ja)
Inventor
Masaharu Sakagami
坂上 正治
Masao Endo
正男 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6571086A priority Critical patent/JPS62224031A/en
Publication of JPS62224031A publication Critical patent/JPS62224031A/en
Pending legal-status Critical Current

Links

Landscapes

  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain a radiation proof semiconductor device in which sufficiently long life is provided even under a circumstance of radioactive rays in existence, by piling two or more kinds of insulating films in which electrons are different in mobility from holes. CONSTITUTION:Two or more kinds of insulating films 4 and 5, in which electrons are different in mobility from holes, are piled in a semiconductor device having an insulating film on at least one part of the semiconductor substrate 6 surface. The radiation resistance is further improve by making layer thickness of an insulating film 4 arranged at a semiconductor substrate 6 side particularly 50% or less of the whole insulating film thickness. When at least one of two kinds of the insulating films 4 and 5 is composed of an insulating film having 3X10<17>/cm<2> or more in electron-trap density, the radiation resistance is further improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路などで酸化物などの絶縁膜を有する
半導体装置に係り、特に放射線の照射に対しても電気的
特性に変化を生じる恐れの少ない半導体装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device having an insulating film such as an oxide, such as an integrated circuit, and in particular a semiconductor device whose electrical characteristics change even when exposed to radiation. Concerning semiconductor devices with little fear.

〔従来の技術〕[Conventional technology]

従来、放射線照射下での半導体装置の電気的特性の変化
を軽減するため、絶縁膜である酸化膜形成プロセス温度
の最適化や酸化膜形成後の窒素雰囲気中での高温アニー
リング、あるいは酸化膜中へのイオンの注入等半導体製
造プロセスを改良する試みがなされている「イー・エッ
チ・ニコリャン、及びジエイ・アール・ブリユース;モ
ス フイジイックス アンド テクノロジー第807頁
から第808頁J  (IE、11.N1collia
n and J、R,I3rews:、、MOS Ph
ys−ics and  Technology、p 
807−808)、また、特願昭60−74372には
、シリコン基板上に熱酸化法により膜厚10nm〜40
nmのシリコン酸化膜を形成し、その後上記シリコン酸
化膜上に化学蒸着法を用い600℃〜850 ”Cの温
度で絶縁膜を積層して形成するバイポーラ・1〜ランジ
スタの製造法が記載されている。しかし、積層する2種
類の絶縁膜中での電荷蓄積挙11!IJに基づくMM膜
の組合せについては一分に配慮されていなかった。
Conventionally, in order to reduce changes in the electrical characteristics of semiconductor devices under radiation irradiation, optimization of the process temperature for forming an oxide film, which is an insulating film, high-temperature annealing in a nitrogen atmosphere after oxide film formation, or Attempts have been made to improve semiconductor manufacturing processes such as ion implantation into
n and J,R,I3rews:,,MOS Ph
ys-ics and Technology, p.
807-808), and in Japanese Patent Application No. 60-74372, a film with a thickness of 10 nm to 40 nm is deposited on a silicon substrate by a thermal oxidation method.
A method for manufacturing bipolar transistors is described in which a silicon oxide film of 100 nm in thickness is formed, and then an insulating film is laminated on the silicon oxide film at a temperature of 600°C to 850"C using a chemical vapor deposition method. However, no consideration has been given to the combination of MM films based on IJ and charge accumulation in two types of insulating films to be laminated.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術では、半導体装置を放射線照射下で使用す
ると、酸化膜中に正の電荷が蓄積され、その蓄積される
正電荷の量は、第2図に示すように放射線吸収線量の増
加に伴なって増加してゆき。
In the above conventional technology, when a semiconductor device is used under radiation irradiation, positive charges are accumulated in the oxide film, and the amount of accumulated positive charges increases as the absorbed dose of radiation increases, as shown in FIG. It continues to increase.

この結果、吸収線量が106ラド以上になると。As a result, if the absorbed dose becomes 106 rad or more.

例えばMOS (Metal−Oxide−3emic
onducfor)電界効果型トランジスタでは第3図
に示すように。
For example, MOS (Metal-Oxide-3emic
(onducfor) As shown in FIG. 3 in a field effect transistor.

そのしきい電圧が0.5  V以上も変化するなど、電
気的特性に大きな変化を生じて使用不能になってしまう
The threshold voltage changes by 0.5 V or more, resulting in a large change in electrical characteristics, making the device unusable.

また、2層絶縁膜を有するバイポーラ・トランジスタで
は耐放射線性能が改善されるが、上記のMOSトランジ
スタと同様に、放射線吸収線量の増加に伴なって絶縁膜
中に蓄積される正電荷量が増加してゆき、それに伴なっ
て電流増幅率が低下するなどの性能劣化が生じる。
In addition, although radiation resistance performance is improved in bipolar transistors with a two-layer insulating film, the amount of positive charge accumulated in the insulating film increases as the absorbed dose of radiation increases, similar to the above-mentioned MOS transistor. As a result, performance deterioration such as a decrease in current amplification factor occurs.

なお、第2図はシリコン酸化膜厚200nm、ゲートバ
イアス電圧+2Vの条件での蓄積正電荷量を示し、第3
図はシリコン酸化膜厚50nm、酸化膜形成プロセス温
度950℃の条件の場合である。そして、第3図の実線
はp−チャネル、破線はn−チャネルを示す。
Furthermore, Figure 2 shows the amount of accumulated positive charge under the conditions of a silicon oxide film thickness of 200 nm and a gate bias voltage of +2V.
The figure shows the case where the silicon oxide film thickness is 50 nm and the oxide film forming process temperature is 950°C. The solid line in FIG. 3 indicates the p-channel, and the broken line indicates the n-channel.

本発明の目的は、耐放射線性に優れ、放射線が存在する
環境下でも充分に永い寿命を与えることができる耐放射
線性半導体装置を堤供することにある。
An object of the present invention is to provide a radiation-resistant semiconductor device that has excellent radiation resistance and can provide a sufficiently long life even in an environment where radiation is present.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、半導体基板表面の絶縁膜として、電子およ
びホールの移動度が異なる2種類以上の絶縁膜を重ねて
形成し、絶縁膜間の電子またはホールの移動度の比が2
以上で移動度の大きい絶縁膜を半導体基板側に配置する
ことにより達成される。
The above purpose is to form two or more types of insulating films with different mobilities of electrons and holes as an insulating film on the surface of a semiconductor substrate, so that the ratio of the mobility of electrons or holes between the insulating films is 2.
The above is achieved by arranging an insulating film with high mobility on the semiconductor substrate side.

とくに、半導体基板側に配置した絶縁膜層厚を全JI4
!I縁膜厚の50%以下にすることにより耐放射線性が
一層向上する。
In particular, the total thickness of the insulating film layer placed on the semiconductor substrate side is JI4
! Radiation resistance is further improved by making it 50% or less of the I edge film thickness.

また、2種類の絶縁膜のうち、少なくとも一方は電子ト
ラップ密度が3X10”/−以上の絶縁膜で構成するこ
とにより、さらに一層耐放射線性が向上する。
Moreover, by forming at least one of the two types of insulating films with an insulating film having an electron trap density of 3×10″/− or more, the radiation resistance is further improved.

〔作用〕[Effect]

本発明は、放射線照射下での半導体酸化膜中の電子・ホ
ール対生成、捕獲挙動解析の研究結果に基づいて発生し
たものである。すなわち、半導体装置に放射線を照射す
ると酸化膜などの絶縁膜中に放射線の吸収線量に応じた
量の電子とホールの対が生成する。これらの電子やホー
ルの一部は絶縁膜中に存在する欠陥で捕獲されるが、電
子の移動度の方がホールの移動度よりはるかに大きいた
め、生成した電子の多くは絶縁膜の外部に逃げる。
The present invention was developed based on research results of analysis of electron/hole pair generation and capture behavior in a semiconductor oxide film under radiation irradiation. That is, when a semiconductor device is irradiated with radiation, pairs of electrons and holes are generated in an insulating film such as an oxide film in an amount corresponding to the absorbed dose of radiation. Some of these electrons and holes are captured by defects in the insulating film, but since the mobility of electrons is much greater than that of holes, many of the generated electrons are trapped outside the insulating film. run away.

一方、生成したホールの多くは絶縁膜中の欠陥で捕獲さ
れ、正電荷蓄積の主因となる。捕獲されたホールと自由
電子との再結合により捕獲ホールの一部が消滅する。こ
のように放射線照射下では、電子とホールの生成、移動
、一部絶縁膜中での捕獲、再結合による捕獲電荷の消滅
の過程をくり返して徐々に絶縁膜中に正電荷が蓄積し、
半導体装置の性能が低下する。
On the other hand, many of the generated holes are captured by defects in the insulating film and become the main cause of positive charge accumulation. A portion of the trapped holes are annihilated by recombination of the trapped holes and free electrons. In this way, under radiation irradiation, positive charges gradually accumulate in the insulating film by repeating the process of generating electrons and holes, moving, partially capturing them in the insulating film, and extinguishing the captured charges by recombination.
The performance of the semiconductor device deteriorates.

絶縁膜中の自由電子およびホールの密度、および捕獲電
荷密度は次の方程式群を解いて得ることができる。独立
変数として、時間tと絶縁膜厚方向の空間座′W4(絶
縁膜表面から半導体基板側に測った屈#l)xを考える
The density of free electrons and holes in the insulating film and the density of trapped charges can be obtained by solving the following group of equations. As independent variables, consider the time t and the spatial locus 'W4' in the direction of the insulating film thickness (curvature #l measured from the insulating film surface to the semiconductor substrate side) x.

(1)自由電子、ホール密度方程式 %式% (2)電子流、ホール゛流 (:3)電界方程式 、 aE    q ”   (p+pt  n  nt)   ・・・(5
)at    ε ox (4)捕獲?重子、捕獲ホール密度方程式%式%(6) く5) i’li子、ホールの捕獲速度Tn=tnn 
(Nn  nt)       ’・・(8)Tp=t
pp (Np  pt)       ・・・(9)(
6)電子、ホールの再結合速度 Rn = r n n p t           
°= (10)Rp= rpp n t       
    −(11)(7)捕獲電荷量およびフラットバ
ンドシフト量Qt” p t  n t       
     −(12)ここで、nは自由電子密度、pは
ホール密度、n(は捕獲電子密度、ptは捕獲ホール密
度、Jnは電子流、Jpはホール流、Goは自由電子生
成速度、Gpはホール生成速度(anl Gpは放射線
吸収線量から決まる)、Tnは電子捕獲速度、Tpはホ
ール捕獲速度、R7は自由電子と捕獲ホールの再結合速
度、Rpはホールと捕獲電子の再結合速度、μ。は電子
移動度、μPはホール移動度、Eは電界、D、は電子拡
散係数(1)o=μn K T / q : kはボル
ツマン定数、Tは温度、qは紫電荷量)、Dpはホール
拡散係数(Dp=μp KT/q)、EOXは絶縁膜の
誘電率、Nnは電子トラップ密度、Npはホールトラッ
プ密度。
(1) Free electron, hole density equation % formula % (2) Electron flow, hole flow (:3) Electric field equation, aE q ” (p + pt n nt) ... (5
) at ε ox (4) Capture? Shigeko, captured hole density equation % formula % (6) 5) i'li child, hole capture speed Tn = tnn
(Nn nt) '...(8) Tp=t
pp (Np pt) ... (9) (
6) Recombination rate of electrons and holes Rn = r n n p t
°= (10) Rp= rpp n t
-(11) (7) Capture charge amount and flat band shift amount Qt” p t n t
-(12) where n is the free electron density, p is the hole density, n( is the trapped electron density, pt is the trapped hole density, Jn is the electron current, Jp is the hole current, Go is the free electron production rate, and Gp is the Hole generation rate (anl Gp is determined from the radiation absorption dose), Tn is the electron capture rate, Tp is the hole capture rate, R7 is the recombination rate of free electrons and trapped holes, Rp is the recombination rate of holes and trapped electrons, μ . is the electron mobility, μP is the hole mobility, E is the electric field, D is the electron diffusion coefficient (1) o = μn K T / q: k is Boltzmann's constant, T is temperature, q is the amount of violet charge), Dp is the hole diffusion coefficient (Dp=μp KT/q), EOX is the dielectric constant of the insulating film, Nn is the electron trap density, and Np is the hole trap density.

Q、は全捕獲電荷量、ΔVpaはフラットバンドシフト
、xo、lは絶縁膜厚、tn HjP +  f’n 
+ rpは定数である。
Q, is the total captured charge, ΔVpa is the flat band shift, xo, l is the insulation film thickness, tn HjP + f'n
+ rp is a constant.

上記の式(1)〜(13)を解いて得た結果の例を第5
図および第6図に示す。第5図は、酸化膜厚1000人
のシリコンMOSキャパシタの酸化膜中の蓄積正電荷の
分布を照射量をパラメータとして示したものである。こ
の図から、10’Rad以上の高照射量では、捕獲正電
荷は酸化膜の界面近傍に集中して分布することが予測さ
れ、電荷分布を測定した実験事実と一致する。第6図は
、酸化膜厚1000人のシリコンMOSキャパシタのフ
ラットバンドシフトとγ線照射量の関係を示すもので、
解析結果と実験データとはよく一致していることがわか
る。これらの結果から、式(1)〜(13)の計算モデ
ルの妥当性が示された。
Examples of the results obtained by solving equations (1) to (13) above are shown in the fifth section.
As shown in FIG. FIG. 5 shows the distribution of accumulated positive charges in the oxide film of a silicon MOS capacitor with an oxide film thickness of 1000, using the irradiation dose as a parameter. From this figure, it is predicted that at a high irradiation dose of 10' Rad or more, the captured positive charges will be concentrated and distributed near the interface of the oxide film, which is consistent with the experimental fact of measuring the charge distribution. Figure 6 shows the relationship between flat band shift and γ-ray irradiation amount for a silicon MOS capacitor with an oxide film thickness of 1000.
It can be seen that the analytical results and experimental data are in good agreement. These results demonstrated the validity of the calculation models of equations (1) to (13).

式(6) 、  (7) 、  (12)および(13
)から見られるように、絶縁膜中の捕獲電荷によるフラ
ットバンドシフト(tl!気的時的特性量代表例)を抑
制するには、(i)電子やホールの捕獲抑制、とくに半
導体基板近傍での捕獲抑制、(it)再結合による捕獲
電荷の消滅促進、および(iii )重子の捕獲による
正電荷の打消し、が有効である。上記(i)に関しては
、式(9)から見られるように、半導体基板近傍でのホ
ール密度を低減することが有効である。このためには、
第4図に示すように半導体装置の絶縁膜を基板近傍の絶
縁層Aと残りの絶縁膜層Bとに分けた場合、A層のホー
ル移動度をB層のホール移動度より大きくなるよう絶縁
膜を形成し、BMからAmへのホールの流れ込みを抑制
し、かつ、A層のホールの移動速度を高めることが有効
である。また、(ii)に関しては、式(1o)から見
られるように、半導体基板近傍での捕獲ホールと自由電
子の再結合促進が有効であり、この丸めにはA層および
B層両者の電子移動度をできる限り小さくし、電子の絶
縁膜から外部に逃げる量を減少させるのが望ましい。と
くに、B層の電子移動度をA層の電子移動度より小さく
し、AMからB[への電子の流出を防ぐことが有効であ
る。また(in)に関しては、電子トラップ密度を増加
させることが有効である。
Equations (6), (7), (12) and (13
), in order to suppress the flat band shift (tl! representative example of temporal characteristic quantity) due to trapped charges in the insulating film, it is necessary to (i) suppress the trapping of electrons and holes, especially in the vicinity of the semiconductor substrate. It is effective to suppress the capture of , (it) promote the disappearance of captured charges by recombination, and (iii) cancel positive charges by capturing deuterons. Regarding (i) above, as seen from equation (9), it is effective to reduce the hole density near the semiconductor substrate. For this purpose,
As shown in Fig. 4, when the insulating film of a semiconductor device is divided into an insulating layer A near the substrate and the remaining insulating film layer B, the insulation film is insulated so that the hole mobility of the A layer is larger than that of the B layer. It is effective to form a film to suppress the flow of holes from BM to Am and to increase the moving speed of holes in the A layer. Regarding (ii), as seen from equation (1o), it is effective to promote the recombination of trapped holes and free electrons near the semiconductor substrate, and this rounding requires electron transfer in both layers A and B. It is desirable to minimize the amount of electrons escaping from the insulating film. In particular, it is effective to make the electron mobility of the B layer lower than that of the A layer to prevent electrons from flowing out from AM to B[. Regarding (in), it is effective to increase the electron trap density.

以上の考え方に従って、第1図に示すようなシリコン半
導体のゲート絶縁体がA層およびB層の2層から成る半
導体素子に対して、捕獲電荷密度を解析した例を、第7
図に示す。この例では、絶縁膜Aのホール移動度を絶縁
膜Bのホール移動度の5倍とし、絶縁膜Aの膜厚を全膜
厚の15%とした。図かられかるように、絶縁膜Δと絶
縁膜Bの組合せで絶縁膜を構成した場合には、絶縁膜A
のみまたは絶縁膜Bのみで構成した場合より、シリコン
基板近傍の捕獲電荷密度が減少し、その結果フラットバ
ンドシフトは小さくなる。
Based on the above idea, an example in which the trapped charge density was analyzed for a semiconductor device whose gate insulator is made of two layers, A layer and B layer, of a silicon semiconductor as shown in FIG.
As shown in the figure. In this example, the hole mobility of the insulating film A was set to five times that of the insulating film B, and the film thickness of the insulating film A was set to 15% of the total film thickness. As can be seen from the figure, when the insulating film is composed of a combination of insulating film Δ and insulating film B, insulating film A
The trapped charge density in the vicinity of the silicon substrate is reduced compared to the case where only the insulating film B is used or the insulating film B is used. As a result, the flat band shift becomes smaller.

第8図に、絶縁膜Aのホール移動度μ^と絶縁膜F3の
ホール移動度μBの比を種々の値に選び、絶縁膜A層J
すX^/全絶縁膜厚XOxを変化させたときのフラット
バンドシフトの変化を解析した結果を示す。μ^/μB
が2以上で、X^/xoxを0.5以下とすればフラッ
トバンドシフトは単一の絶縁膜の場合よりも低下する。
In FIG. 8, the ratio of the hole mobility μ^ of the insulating film A to the hole mobility μB of the insulating film F3 is selected to various values, and the ratio of the hole mobility μ^ of the insulating film A layer J
The results of analyzing the change in flat band shift when changing the total insulating film thickness XOx are shown. μ^/μB
is 2 or more and X^/xox is 0.5 or less, the flat band shift will be lower than in the case of a single insulating film.

したがって、このような2層の酸化膜を採用すれば、放
射線照射による性能劣化を小さくシ、半導体装置の寿命
を延長できる。
Therefore, by employing such a two-layer oxide film, performance deterioration due to radiation irradiation can be minimized and the life of the semiconductor device can be extended.

絶縁膜Aの電子移動度μΔ′ と絶縁膜Bの電子移動度
μB′ に対しμ^′/μB′を2以上に選んでも、第
8図に示したのと殆ど同様に、フラットバンドシフトを
低減できる。
Even if μ^'/μB' is selected to be 2 or more for the electron mobility μΔ' of the insulating film A and the electron mobility μB' of the insulating film B, the flat band shift is almost the same as shown in Fig. 8. Can be reduced.

第9図に、B層の電子トラップ密度を種々の値に選び、
絶縁膜A層厚/全絶縁膜厚を変化させたときのフラット
バンドシフトの変化を示した。B層の電子トラップ密度
を3X1017以上にすれば。
Figure 9 shows that the electron trap density of the B layer is selected to various values,
The graph shows the change in flat band shift when the thickness of the insulation film A layer/total insulation film thickness is changed. If the electron trap density of the B layer is set to 3X1017 or more.

フラットバンドシフトを低減でき、放射線照射による性
能劣化を小さく抑えることができる。
Flat band shift can be reduced, and performance deterioration due to radiation irradiation can be kept to a minimum.

〔実施例〕〔Example〕

以下、本発明の一実施例を第10図により説明する6本
実施例では、シリコン半導体上にまず高温下で熱酸化法
により熱酸化膜を全膜厚の50%以下の厚さで形成し、
その上に化学蒸着法により堆積酸化膜を形成したもので
ある。堆積酸化膜のみ、および熱酸化膜のみの場合のフ
ラットバンドシフトの実験値を第11図に示す。これら
の値にフィツトするようホールおよび電子の移動度、電
子トラップ密度を決定した。その結果に基づいて、2層
酸化膜の熱酸化膜厚ン全酸化膜厚を変化させフラットバ
ンドシフトの変化を解析した結果を同図に示した。この
図から、熱酸化膜厚/堆積酸化膜厚を0.5以下に選べ
ば、単一の酸化膜よりフラットバンドシフトを小さく抑
えられることがわかる。したがって1本実施例によれば
放射線照射下で使用しても性能劣化の小さく抑えられる
効果がある。
An embodiment of the present invention will be described below with reference to FIG. 10. In this embodiment, a thermal oxide film is first formed on a silicon semiconductor by a thermal oxidation method at a high temperature to a thickness of 50% or less of the total film thickness. ,
A deposited oxide film is formed thereon by chemical vapor deposition. FIG. 11 shows experimental values of flat band shift in the case of only a deposited oxide film and only a thermal oxide film. Hole and electron mobilities and electron trap densities were determined to fit these values. Based on the results, the thermal oxide film thickness and the total oxide film thickness of the two-layer oxide film were changed and the changes in the flat band shift were analyzed, and the results are shown in the same figure. This figure shows that if the thermal oxide film thickness/deposited oxide film thickness is selected to be 0.5 or less, the flat band shift can be suppressed to be smaller than that of a single oxide film. Therefore, according to this embodiment, performance deterioration can be suppressed to a small level even when used under radiation irradiation.

第12図の他の実施例を示す。この例では、シリコン基
板上にまず高温下で窒化膜を形成し、その上に堆積酸化
膜を形成する。この場合も実施例・1と同様に窒化膜厚
を全11優厚の50%以下とする。
Another embodiment of FIG. 12 is shown. In this example, a nitride film is first formed on a silicon substrate at high temperature, and then a deposited oxide film is formed thereon. In this case, as in Example 1, the nitride film thickness is set to 50% or less of the total 11 thicknesses.

窒化膜のホール移動度は堆積酸化膜のホール移動度に比
べてはるかに大きいため、このような半導体装置を放射
線照射下で使用しても、性能劣化を小さく抑えられる。
Since the hole mobility of a nitride film is much higher than that of a deposited oxide film, even if such a semiconductor device is used under radiation irradiation, performance deterioration can be suppressed to a small level.

第13図に他の実施例を示す。この例では、シリコン基
板上に最初に例えば1000℃以−ヒで熱酸化膜を形成
し、その後、例えば900℃以下で熱酸化膜を形成する
。このとき、1000℃以上で形成した酸化膜厚さを全
酸化膜厚さの50%以上となるようにする。こうするこ
とにより、 90(1℃の比較的低温でシリコン基板側
に形成したち密な酸化膜のホール移動度を相対的に大き
くすることができ、したがって放射線照射に対し性能劣
化の小さい半導体装置を実現できる。
FIG. 13 shows another embodiment. In this example, a thermal oxide film is first formed on a silicon substrate at, for example, 1000° C. or higher, and then a thermal oxide film is formed at, for example, 900° C. or lower. At this time, the thickness of the oxide film formed at 1000° C. or higher is set to be 50% or more of the total oxide film thickness. By doing this, it is possible to relatively increase the hole mobility of the dense oxide film formed on the silicon substrate side at a relatively low temperature of 90°C (1°C), thereby creating a semiconductor device with little performance deterioration due to radiation irradiation. can be realized.

なお、半導体絶縁膜中に主構成元素以外の元素を微量注
入もしくは絶縁膜形成時に添加し、電子またはホールの
移動度を膜厚の各位置ごとに調整する方法を採用しても
よい。また、絶縁膜中の電子トラップ密度の′I14整
にも上記の方法が適用できる。
Note that a method may be adopted in which an element other than the main constituent elements is injected into the semiconductor insulating film in a small amount or added at the time of forming the insulating film, and the mobility of electrons or holes is adjusted for each position in the film thickness. The above method can also be applied to adjusting the electron trap density in the insulating film.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、放射線照射下で使用しても電気的特性
の変化を小さく抑えられるので、半導体装置の寿命を大
幅に延長する効果がある。
According to the present invention, changes in electrical characteristics can be suppressed to a small extent even when used under radiation irradiation, so that the life of the semiconductor device can be significantly extended.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例、第2図は酸化膜中の捕獲正
電荷量と放射線吸収線量の関係図、第3図はMOSトラ
ンジスタのしきい電圧変化と放射線吸収線量の関係図、
第4図は2層絶縁膜の説明図、第5図は酸化膜中捕獲正
電荷分布の解析例、第6図はMOSキャパシタのフラッ
トバンドシフトの解析値と実験値の比較例、第7図は絶
縁膜中捕獲電荷分解の解析例、第8,9図はフラットバ
ンドシフトと2層膜厚比の関係図、第10図は本発明の
一実施例、第11図はフラットバンドシフトと2層1模
厚比の関係図、第12.13図は本発明の他の実施例で
ある。 1・・・絶縁膜A、2・・・絶縁膜B、3・・・半導体
基板。 4・・・熱酸化膜、5・・・堆積酸化膜、6・・・Si
基板。 7・・・窒化膜、8・・・900℃以下で形成した熱酸
化膜、9・・・1000℃以上で形成した熱酸化膜1、
 )
FIG. 1 is an example of the present invention, FIG. 2 is a relationship between the amount of positive charge captured in the oxide film and the absorbed dose of radiation, and FIG. 3 is a diagram of the relationship between the threshold voltage change of a MOS transistor and the absorbed dose of radiation.
Figure 4 is an explanatory diagram of a two-layer insulating film, Figure 5 is an example of analysis of the distribution of positive charges trapped in an oxide film, Figure 6 is an example of comparison between analytical and experimental values of flat band shift of a MOS capacitor, and Figure 7 8 and 9 are relationship diagrams of flat band shift and two-layer film thickness ratio, FIG. 10 is an example of the present invention, and FIG. 11 is an example of flat band shift and two-layer film thickness ratio. A relationship diagram of layer 1 thickness ratio, FIG. 12.13, is another embodiment of the present invention. 1... Insulating film A, 2... Insulating film B, 3... Semiconductor substrate. 4... Thermal oxide film, 5... Deposited oxide film, 6... Si
substrate. 7... Nitride film, 8... Thermal oxide film formed at 900°C or lower, 9... Thermal oxide film 1 formed at 1000°C or higher,
)

Claims (1)

【特許請求の範囲】 1、半導体基板表面の少なくとも一部に絶縁膜を有する
半導体装置において、電子およびホールの移動度が異な
る2種類以上の絶縁膜を重ねて形成したことを特徴とす
る耐放射線半導体装置。 2、特許請求の範囲第1項において、電子またはホール
の移動度の比が2以上の2種類の絶縁膜を重ねて形成し
たことを特徴とする耐放射線半導体装置。 3、特許請求の範囲第2項において、ホールまたは電子
の移動度が大きい絶縁膜を半導体基板側に配置したこと
を特徴とする耐放射線半導体装置。 4、特許請求の範囲第3項において、半導体基板側に配
置した絶縁膜の膜厚を全絶縁膜厚の50%以下にしたこ
とを特徴とする耐放射線半導体装置。 5、特許請求の範囲第1項において、少なくとも一方の
絶縁膜の電子トラップ密度が3×10^1^7/cm^
3以上であることを特徴とする耐放射線半導体装置。
[Claims] 1. A radiation-resistant semiconductor device having an insulating film on at least a portion of the surface of a semiconductor substrate, characterized in that two or more types of insulating films having different mobilities of electrons and holes are stacked and formed. Semiconductor equipment. 2. A radiation-resistant semiconductor device according to claim 1, characterized in that two types of insulating films having a mobility ratio of electrons or holes of 2 or more are formed by overlapping each other. 3. A radiation-resistant semiconductor device according to claim 2, characterized in that an insulating film having high hole or electron mobility is disposed on the semiconductor substrate side. 4. A radiation-resistant semiconductor device according to claim 3, characterized in that the thickness of the insulating film disposed on the semiconductor substrate side is 50% or less of the total insulating film thickness. 5. In claim 1, the electron trap density of at least one insulating film is 3×10^1^7/cm^
A radiation-resistant semiconductor device characterized by having a radiation resistance of 3 or more.
JP6571086A 1986-03-26 1986-03-26 Bariation-proof Pending JPS62224031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6571086A JPS62224031A (en) 1986-03-26 1986-03-26 Bariation-proof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6571086A JPS62224031A (en) 1986-03-26 1986-03-26 Bariation-proof

Publications (1)

Publication Number Publication Date
JPS62224031A true JPS62224031A (en) 1987-10-02

Family

ID=13294844

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6571086A Pending JPS62224031A (en) 1986-03-26 1986-03-26 Bariation-proof

Country Status (1)

Country Link
JP (1) JPS62224031A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60107837A (en) * 1983-11-17 1985-06-13 Nec Corp Semiconductor device, radiation resistance thereof is reinforced, and manufacture thereof
JPS60193342A (en) * 1984-03-15 1985-10-01 Nec Corp Manufacture of semiconductor device
JPS60223132A (en) * 1984-04-19 1985-11-07 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
JPS6158270A (en) * 1984-08-29 1986-03-25 Hitachi Ltd Semiconductor device and manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60107837A (en) * 1983-11-17 1985-06-13 Nec Corp Semiconductor device, radiation resistance thereof is reinforced, and manufacture thereof
JPS60193342A (en) * 1984-03-15 1985-10-01 Nec Corp Manufacture of semiconductor device
JPS60223132A (en) * 1984-04-19 1985-11-07 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
JPS6158270A (en) * 1984-08-29 1986-03-25 Hitachi Ltd Semiconductor device and manufacture thereof

Similar Documents

Publication Publication Date Title
Kamins Field-effects in polycrystalline-silicon films
Hughes et al. Radiation effects and hardening of MOS technology: Devices and circuits
Simoen et al. Low-frequency noise behavior of SiO/sub 2/--HfO/sub 2/dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness
KR20080053217A (en) Nonvolatile semiconductor memory device and method of manufacturing the same
Lee et al. Performance of gamma irradiated p-channel 6H-SiC MOSFETs: High total dose
US5698883A (en) MOS field effect transistor and method for manufacturing the same
CN104022104B (en) Charge protection for III-nitride devices
Fan et al. Voltage-and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/n-channel MOS capacitor
KR100278459B1 (en) Semiconductor device and manufacturing method thereof
JP5841013B2 (en) Semiconductor device
Yamaguchi et al. Band diagram and carrier conduction mechanisms in ZrO/sub 2/MIS structures
JPS62224031A (en) Bariation-proof
JPH0265254A (en) Semiconductor device
Ma et al. Charge-trapping memory based on tri-layer alumina gate stack and InGaZnO channel
Simone et al. Ionizing radiation hardening of a CCD technology
JPS5890778A (en) Semiconductor device
Deki et al. Instability of critical electric field in gate oxide film of heavy ion irradiated SiC MOSFETs
JPS62221157A (en) Radiation-resistive semiconductor device
KR102679913B1 (en) Fixed charge expression method, manufacturing method of thin film transistor, and thin film transistor
EP0115035B1 (en) Semiconductor structure tolerant to ionizing radiation
JPS6193641A (en) Semiconductor device
US8759903B1 (en) Method of fabricating total dose hard and thermal neutron hard integrated circuits
JPS60148143A (en) Semiconductor device with enforced withstand radiation property thereof
JP2595982B2 (en) Semiconductor device
JPS6346980B2 (en)