JPS62221877A - Inverter protection system - Google Patents

Inverter protection system

Info

Publication number
JPS62221877A
JPS62221877A JP61062436A JP6243686A JPS62221877A JP S62221877 A JPS62221877 A JP S62221877A JP 61062436 A JP61062436 A JP 61062436A JP 6243686 A JP6243686 A JP 6243686A JP S62221877 A JPS62221877 A JP S62221877A
Authority
JP
Japan
Prior art keywords
polarity
load
period
voltage
circuit section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61062436A
Other languages
Japanese (ja)
Other versions
JPH0817575B2 (en
Inventor
Masahiro Osada
雅裕 長田
Kazuyuki Ogiwara
荻原 一行
Takehiro Matsumoto
武浩 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sawafuji Electric Co Ltd
Original Assignee
Sawafuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sawafuji Electric Co Ltd filed Critical Sawafuji Electric Co Ltd
Priority to JP61062436A priority Critical patent/JPH0817575B2/en
Publication of JPS62221877A publication Critical patent/JPS62221877A/en
Publication of JPH0817575B2 publication Critical patent/JPH0817575B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To simplify the organization of a circuit and prevent over current from flowing, by checking the detected polarities of load voltage and oscillating circuit section output, and by controlling a rest period. CONSTITUTION:An inverter circuit is composed of transistors 1-1-1-4 and free wheeling diodes 2-1-2-4, and current is fed to a load 3. In parallel with the transistors 1-2, 1-4, voltage detecting resistor 5-1-5-4 are respectively arranged, and a polarity detecting section 6 for detecting the polarity of load voltage, a rectangular wave oscillating circuit section 7, and a polarity comparing circuit section 8 are set. Then, the polarity of voltage generated on the load 3 is detected and is compared with the output polarity of the oscillating circuit section 7, and just during a period when both the polarities are different, a rest period when all switching elements are turned OFF. As a result, the discharge period of a condenser is separated from a period when the transistors are ON for charge, and over current can be prevented from flowing.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、インバータ保護方式、特にブリッヂ接続され
たスイッチング素子を有するインバータ回路において、
上記スイッチング素子を制御する発振回路の出力の極性
と負荷に生じている電圧の極性とを比較し、スイッチン
グ素子のオン・オフ転換器に休止期間をもうけるように
したインバータ保護方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inverter protection system, particularly an inverter circuit having bridge-connected switching elements.
The present invention relates to an inverter protection system that compares the polarity of the output of an oscillation circuit that controls the switching element with the polarity of the voltage generated in the load, and provides a rest period for the on/off converter of the switching element.

〔従来の技術〕[Conventional technology]

従来から、第3図図示の如き構成をもつインバータ回路
が知られている。
Conventionally, an inverter circuit having a configuration as shown in FIG. 3 has been known.

第3図において、符号1−1ないし1−4は夫々トラン
ジスタ、2−1ないし2−4は夫々フリーボイリング・
ダイオード、3は負荷であって3−Rは抵抗負荷で3−
Cはコンデンサ負荷、4は直流電源を表している。
In FIG. 3, numerals 1-1 to 1-4 are transistors, respectively, and 2-1 to 2-4 are free-boiling transistors, respectively.
Diode, 3 is the load, 3-R is the resistive load, 3-
C represents a capacitor load, and 4 represents a DC power supply.

従来上記の如き構成のインバータ回路が知られているが
、負荷としてコンデンサ負荷3−cが接続される場合に
は1次の如き問題が内在している。
Conventionally, inverter circuits having the above configuration are known, but when a capacitor load 3-c is connected as a load, a first-order problem is inherent.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第3図図示の如くコンデンサ負荷3−Cが接続されてい
る場合において、今、トランジスタ1−2と1−3とが
オンされていた状態からオフされかつそれに伴ってトラ
ンジスタ1−1と1−4とがオンされるとき、第3図図
示icの如き大きい放電電流が生じる。これは、第3図
図示(+)(−)の如くコンデンサ負荷3−Cが充電さ
れている状態において、トランジスタ1−1と1−4と
がオンされることから、いわば2倍の電圧によってコン
デンサ負荷3−Cが逆方向に充電されようとする形とな
るからである。第4図はこの間の状況をタイムチャート
で表したものである。
In the case where the capacitor load 3-C is connected as shown in FIG. 4 is turned on, a large discharge current as shown in FIG. 3 occurs. This is because transistors 1-1 and 1-4 are turned on when the capacitor load 3-C is charged as shown in FIG. 3 (+) and (-), so the voltage is doubled. This is because the capacitor load 3-C tends to be charged in the opposite direction. Figure 4 shows the situation during this time in a time chart.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記の点を解決しており、上記電圧検出抵抗
を配置し、負荷に生じる電圧の極性を検出して上述の如
き場合における問題点を解決している。
The present invention solves the above problems by arranging the voltage detection resistor and detecting the polarity of the voltage generated in the load.

第1図は1本発明の原理構成図であって本発明の実施例
を構成するものである。図中の符号1−1ないし1−4
は夫々トランジスタ、2−1ないし2−4は夫々フリー
ホイリング・ダイオード。
FIG. 1 is a diagram illustrating the principle of the present invention and constitutes an embodiment of the present invention. Codes 1-1 to 1-4 in the diagram
are transistors, and 2-1 to 2-4 are freewheeling diodes.

3は負荷、5−1ないし5−4は夫々電圧検出抵抗を表
している。また6は負荷電圧の極性を検出する極性検出
部、7は矩形波発振回路部、8は極゛ 性比較回路部を
表している。
3 represents a load, and 5-1 to 5-4 each represent a voltage detection resistor. Further, 6 represents a polarity detection section for detecting the polarity of the load voltage, 7 represents a rectangular wave oscillation circuit section, and 8 represents a polarity comparison circuit section.

第1図図示の回路における動作、特にトランジスタ1−
1と1−4との第1群のスイッチング素子およびトラン
ジスタ1−2と1−3との第2群のスイッチング素子が
交互にオンされることに関して、従来の構成と実質的に
変わりはない。ただ。
The operation of the circuit shown in Figure 1, especially the transistor 1-
There is no substantial difference from the conventional configuration in that the first group of switching elements 1 and 1-4 and the second group of switching elements of transistors 1-2 and 1-3 are alternately turned on. just.

抵抗5−1ないし5−4がもうけられ、負荷3上に生じ
ている電圧の極性を検出するようにしている。
Resistors 5-1 to 5-4 are provided to detect the polarity of the voltage present on the load 3.

即ち負荷3の図示右側の電圧(RV)と図示左側の電圧
(LV)とを抽出し。
That is, the voltage (RV) on the right side in the figure and the voltage (LV) on the left side in the figure of the load 3 are extracted.

RV−LV≧十△■ となる期間を第1の極性とみなし、またLV−RV≧+
△■ となる期間を第2の極性とみなし、極性検出部6がこの
旨を極性比較回路部8に通知する。
The period in which RV-LV≧10△■ is regarded as the first polarity, and the period in which LV-RV≧+
The period of Δ■ is regarded as the second polarity, and the polarity detection section 6 notifies the polarity comparison circuit section 8 of this fact.

矩形波発振回路部7は矩形波出力を発しており。The rectangular wave oscillation circuit section 7 emits a rectangular wave output.

極性比較回路部8は、当該矩形波発振回路部7の出力の
極性と上記極性検出部6からの極性とを比較する。そし
て1両者の極性が異なっている期間だけ、スイッチング
素子全体をオフ状態におく所の休止期間を与えるように
している。
The polarity comparison circuit section 8 compares the polarity of the output of the rectangular wave oscillation circuit section 7 and the polarity from the polarity detection section 6. A rest period in which the entire switching element is turned off is provided only during the period in which the polarities of the two are different.

〔作用〕[Effect]

上記の動作状況は、第2図図示のタイムチャートによっ
て明らかにされている。第2図において。
The above operating situation is made clear by the time chart shown in FIG. In fig.

「休止」としている期間が、上記休止期間に対応してい
る。そして、当該休止期間は、負荷3に存在するコンデ
ンサの電圧が1図示ハツチングで示すように、放電によ
って減衰してゆく期間に相当している。
The period marked as "suspension" corresponds to the above-mentioned suspension period. The rest period corresponds to a period in which the voltage of the capacitor present in the load 3 is attenuated due to discharge, as shown by hatching in the figure.

このために、負荷3に存在するコンデンサが放電する期
間を待って2例えばトランジスタ1−2と1−3との組
からトランジスタ1−1と1−4との組に転換されるこ
ととなる。即ちコンデンサが放電する期間と、スイッチ
ング素子がオンされて充電される期間とが分離される形
となり、過大な電流が流れることが防止される。
For this purpose, after waiting for a period during which the capacitor present in the load 3 is discharged, for example, the set of transistors 1-2 and 1-3 is changed to the set of transistors 1-1 and 1-4. That is, the period in which the capacitor is discharged and the period in which the switching element is turned on and charged are separated, and excessive current is prevented from flowing.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く9本発明によれば、上述の休止期間を
置くように制御するに当たって1発振回路部出力の極性
と負荷の極性とを照合するだけの処理によって、上記休
止期間を生じさせることができる。このために2例えば
、上記休止期間を置くに当たって1発振回路部出力波形
自体に、予め定めた電圧零の期間をもうけるようにする
などの。
As explained above, according to the present invention, the above-mentioned rest period can be caused by simply checking the polarity of the output of the oscillation circuit section and the polarity of the load when performing control to cause the above-mentioned rest period. can. For this purpose, for example, in providing the above-mentioned rest period, a predetermined zero voltage period is provided in the oscillation circuit output waveform itself.

従来公知の構成にくらべて2回路構成がきわめて簡単に
なる。即ちデジタル処理によっても所期の目的を達成す
ることが可能になっている。
The two-circuit configuration is extremely simple compared to conventionally known configurations. In other words, it is now possible to achieve the intended purpose even through digital processing.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理構成図であって本発明の実施例を
構成するもの、第2図はその動作を説明するタイムチャ
ート、第3図は従来の構成、第4図はその動作を説明す
るタイムチャートを示す。 図中、1はスイッチング素子(トランジスタ)。 2ばフリーホイリング・ダイオード、3は負荷。 3−Cはコンデンサ負荷、4は直流電源、5は電圧検出
抵抗、6は極性検出部、7は矩形波発振回路部、8は極
性比較回路部を表す。
Fig. 1 is a diagram showing the principle configuration of the present invention, which constitutes an embodiment of the present invention, Fig. 2 is a time chart explaining its operation, Fig. 3 is a conventional configuration, and Fig. 4 is its operation. A time chart for explanation is shown. In the figure, 1 is a switching element (transistor). 2 is a freewheeling diode, 3 is a load. 3-C is a capacitor load, 4 is a DC power supply, 5 is a voltage detection resistor, 6 is a polarity detection section, 7 is a rectangular wave oscillation circuit section, and 8 is a polarity comparison circuit section.

Claims (1)

【特許請求の範囲】[Claims] フリーホイリング・ダイオードが外付けされあるいは内
蔵されるスイッチング素子をそなえ、当該スイッチング
素子をブリッヂ接続し、当該ブリッヂ接続の中性点間に
コンデンサを含む負荷を接続したインバータ回路におい
て、上記ブリッヂ接続における非対向位置に存在する少
なくとも上記スイッチング素子に夫々並列に電圧検出抵
抗を接続し、当該夫々の電圧検出抵抗上に発生した検出
電圧を抽出して上記負荷に生じている電圧の極性を検出
し、かつ当該極性と上記スイッチング素子を制御する発
振回路出力の極性とを比較するよう構成してなり、該比
較結果にもとづいて、上記ブリッヂ接続されている第1
群のスイッチング素子がオフされた後に第2群のスイッ
チング素子をオンせしめない休止期間をもうけるように
したことを特徴とするインバータ保護方式。
In an inverter circuit that includes a switching element with an external or built-in freewheeling diode, the switching element is connected in a bridge, and a load including a capacitor is connected between the neutral point of the bridge connection. Connecting voltage detection resistors in parallel to at least the switching elements located at non-opposing positions, extracting the detection voltages generated on the respective voltage detection resistors and detecting the polarity of the voltage occurring in the load; and is configured to compare the polarity with the polarity of the output of the oscillation circuit that controls the switching element, and based on the comparison result, the first
An inverter protection system characterized in that after the switching elements of the group are turned off, there is a rest period in which the switching elements of the second group are not turned on.
JP61062436A 1986-03-20 1986-03-20 Inverter protection method Expired - Lifetime JPH0817575B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61062436A JPH0817575B2 (en) 1986-03-20 1986-03-20 Inverter protection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61062436A JPH0817575B2 (en) 1986-03-20 1986-03-20 Inverter protection method

Publications (2)

Publication Number Publication Date
JPS62221877A true JPS62221877A (en) 1987-09-29
JPH0817575B2 JPH0817575B2 (en) 1996-02-21

Family

ID=13200136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61062436A Expired - Lifetime JPH0817575B2 (en) 1986-03-20 1986-03-20 Inverter protection method

Country Status (1)

Country Link
JP (1) JPH0817575B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012147573A (en) * 2011-01-12 2012-08-02 Yaskawa Electric Corp Inverter apparatus and motor drive system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57148591A (en) * 1981-02-26 1982-09-13 Ibm Step motor drive circuit
JPS60229676A (en) * 1984-04-26 1985-11-15 Mitsubishi Electric Corp Pwm inverter
JPS60249874A (en) * 1984-05-24 1985-12-10 Shinko Electric Co Ltd Preventing method of irregular magnetization of transformer for inverter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57148591A (en) * 1981-02-26 1982-09-13 Ibm Step motor drive circuit
JPS60229676A (en) * 1984-04-26 1985-11-15 Mitsubishi Electric Corp Pwm inverter
JPS60249874A (en) * 1984-05-24 1985-12-10 Shinko Electric Co Ltd Preventing method of irregular magnetization of transformer for inverter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012147573A (en) * 2011-01-12 2012-08-02 Yaskawa Electric Corp Inverter apparatus and motor drive system

Also Published As

Publication number Publication date
JPH0817575B2 (en) 1996-02-21

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