JPS62221071A - Butterfly arithmetic circuit and fast fourier transform device using same - Google Patents

Abstract

PURPOSE:To increase the working speed of a butterfly arithmetic of an FFT by using an addition circuit using a redundant binary digit whose carry is not transmitted to higher digit to form the addition circuit of the butterfly arithmetic circuit of an FFT and therefore reducing the time of addition down to a fixed level regardless of the number of digits. CONSTITUTION:All input and output data of a butterfly arithmetic circuit are treated by the redundant binary digits and the real number multiplication and the real number addition are all carried out with redundant binary digits. In an addition circuit applying the arithmetic of redundant binary numbers, the sum of digits can obtained so that the carry of a lower digit is not transmitted to the higher digit. That is, the addition is completed with the 1st operation where the sum of digits is expressed by an intermediate carry and an intermediate sum and the 2nd operation where the addition is performed between the intermediate carry given from a lower digit and the intermediate sum. As a result, the time of operation is decided by the number of logical stages of the elements forming a relevant redundant binary addition circuit and regardless of the number of digits. This increases the operating speed of the addition and furthermore increases the working speed of a butterfly arithmetic circuit and an FFT.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a butterfly arithmetic circuit and a fast Fourier transform device using the same.

[Prior art]

When a function defined in the time domain and a function in the frequency domain obtained by Fourier transformation thereof are both periodic functions, both of these functions are expressed by a series of discrete sampling values of finite elements. As is well known, a relationship defined by discrete Fourier transform and inverse transform exists between the two. Fast Fourier transform (hereinafter referred to as rFFTJ) involves multiplication,
This is a well-known method for reducing the number of additions and subtractions and improving conversion speed. The calculation is achieved by repeating the butterfly calculation many times as a basic calculation. It is known to configure such a butterfly calculation circuit as hardware. This butterfly arithmetic circuit is composed of - times of complex number multiplication circuits, - times of complex number addition circuits, and - times of complex number subtraction circuits. In addition, FFT hardware that uses such a butterfly calculation circuit as a basic circuit is also a sequential processing type in which data processing is performed sequentially in time series using one butterfly calculation circuit, and m-win processing is performed using separate butterfly calculation circuits. A cascade processing type that is connected in cascade to enable pipeline processing, a parallel processing type that has half the number of input points of butterfly calculation circuits arranged in parallel and processes one stage at a time, and a parallel arrangement and a cascade arrangement. A two-dimensional parallel processing type in which a combination of butterfly calculation circuits is configured in a mesh pattern is known.

[Problems to be solved by the invention]

In any of the above-mentioned types of FFT hardware, a signed binary number or a two's complement representation binary number system is adopted as the calculation method. The adder in the butterfly arithmetic circuit is a ripple carrier adder (rRCA).
A carry look-ahead adder (hereinafter abbreviated as rCLAJ) is likely to be commonly used. Since this RCA has the same configuration for each digit, it is easy to design a pattern for IC, but since the carry from the lower digit propagates to the upper digit, the calculation time increases in proportion to the number of digits added. There are drawbacks. Further, in CLA, the addition time increases in proportion to the logarithm of the number of digits to be added, but the higher the digit, the more complicated the circuit configuration becomes, and the disadvantage is that the pattern design when integrated into an IC becomes more complicated. Such drawbacks still exist as drawbacks of butterfly arithmetic circuits and FFT devices. That is, there is a drawback that the circuit configuration becomes complicated in order to realize high-speed calculation. Furthermore, in order to perform FFT in real time, there is a demand for a faster FFT device. The present invention has been made based on the above-mentioned viewpoint, and its purpose is to improve the calculation speed of a butterfly calculation circuit and an FFT device.

[Means to solve the problem]

The present invention provides a butterfly calculation circuit comprising a multiplication circuit that outputs data obtained by multiplying input data by a twiddle factor, and an addition/subtraction circuit that calculates the sum and difference of two input data and outputs the obtained data. , the partial product generation circuit in the multiplication circuit processes the multiplicand, which is the input data, as a redundant binary number and outputs the partial product as a redundant binary number, and 5. The sum of the partial products in the multiplication circuit A butterfly arithmetic circuit for a fast Fourier transform device, characterized in that the arithmetic circuit and the addition/subtraction circuit are configured with a redundant binary adder circuit in which a carry is not propagated to higher digits due to an addition operation using redundant binary numbers; This is a fast Fourier transform device that includes an arithmetic circuit as a basic circuit.

[Effect]

The butterfly arithmetic circuit performs one complex multiplication, one complex addition, and one complex subtraction. Complex number operations are actually divided into real and imaginary parts, so in order to obtain the real part of one output data, one stage of real number multiplication and two stages of real number addition/subtraction are required along the signal flow. shall be. In addition, since real number multiplication is obtained as the sum of partial products, the butterfly arithmetic circuit requires many addition circuits (subtraction can be performed in addition circuits, so hereinafter, including subtraction circuits, we will also refer to them as addition circuits). . In the present invention, all input and output data of the butterfly arithmetic circuit are handled as redundant binary numbers, and all real number multiplications and real number additions are performed using redundant binary numbers. An adder circuit using redundant binary arithmetic can express the sum of each digit so that a carry of a lower digit does not propagate to an upper digit. That is, the first operation expresses the sum of each digit with two digits of intermediate carry and intermediate sum, and the second operation performs intermediate carry from the lower digits and addition to the intermediate sum. You can make the addition end with . As a result, the calculation time is determined by the number of logic stages of the elements constituting the redundant binary adder circuit, regardless of the number of digits. Therefore, since the speed of addition operation is improved, the speed of butterfly operation and FFT is improved. Further, the above-described redundant binary addition circuit is suitable for IC implementation because each digit can have the same configuration.

【Example】

The present invention will be explained below based on specific examples. (1) Definition The FFT device of this embodiment inputs a sampling value series (X, . . .・・・
Y,) is output as output data. The input/output data is expressed as a one-digit binary number in two's complement representation. 1-digit binary number Can-+ a in two's complement representation
nz -an] In e2, the first most significant digit is -
The other first digits have a weight of 2'-1, and a takes (0, 1). Redundant binary numbers are used inside the FFT device. 1-digit redundant binary number Cah-+ an-x ”'ao)
In R2, the ii digit has a weight of 21-1, and a is (-
It is defined as a number that takes 1,0°1). Also, in order to binarize the redundant binary number, one digit of the redundant binary number is
Expressed in bits, Ca+ 311= [:as'tadl]x

[0]1=

[00]2 [1] R□=[01)2 (-1) R,= l”l 01.The redundant binary numbers expressed in binary numbers in this way are hereinafter referred to as binary-evolution redundant binary numbers. The discrete Fourier transform and its inverse transform are defined by the following formula. The twiddle factor W is defined by the following formula: W = exp (-j2π/N) The butterfly arithmetic circuit is Two outputs C and D are output, and their relationship is defined by the following formula: C=A+B-WK D=A-B-WK Furthermore, let ASB, C, and D be complex numbers, and their real parts , if the imaginary part is expressed with the subscript R1■, the following relational expression holds true: C□=Ai+B++CO3φ+B, SINφC+ =
At −Bi SINφ+BX COSφDA=
A, -BII CO3φ-B! SINφD,=A□
10B, SINφ-B, COSφ However, w'=cosφ-
j SINφ. (2) Overall configuration FIG. 1 is a block diagram showing the configuration of an FFT apparatus according to an embodiment. 1 inputs N points of input data, performs predetermined rearrangement, and converts each data into binary coded redundant 2
This is a data input section that converts it into a base number and outputs it to the FFT calculation section 2. 2 is an FFT calculation section in which butterfly calculation circuits are arranged in a mesh pattern. The FFT calculation unit 2 performs Fourier transform on N points of input data to generate N points of output data. 3 is the binary evolution redundancy 2 output from the FFT calculation unit 2.
Convert the base output data to a binary number expressed in two's complement, and
This is a data output unit that sequentially outputs point data. (3) Data input unit The data input unit 1 includes an A/D converter 11 that samples analog signals in time and space and converts them into digital signals;
An input control unit 14 that provides sampling timing, an input buffer 12 that sequentially inputs N points of digital data to a predetermined address, and a counter that inputs a timing signal from the input control unit 14 and sequentially determines the address of the input buffer 12. 15 and 2 input to the input buffer 13
Redundant binary conversion unit 13 that converts a base number into a binary coded redundant binary number
Tokara. The power buffer 12 has buffer registers BX, -BX8 that store data at N points. The counter 15 is an N-ary counter, and is updated every time a timing signal is input from the input control unit 14, and its output is reversed from the upper direction of the bit to the lower direction.
2 address signal. As a result, the N point data is
Rearranged in a predetermined order, registers BX, -Bx8
is memorized. One data unit of the redundant binary converter 13 is
It is constructed as shown in FIG. A binary number in two's complement representation can be viewed as a redundant binary number with the most significant digit having a weight of 12"-1. In other words, the most significant digit has its sign inverted and the other digits are output as is. You can convert it to redundant binary numbers by doing this. Therefore,
The most significant digit of register BX is divided (the digit is the output as the lower bit of each digit of the binary coded redundant binary number) ado~ad, -2, and the output of the most significant digit is the upper bit asn-1, If the other bits aSO to asa-2, adI, and -1 are set to 0, a binary coded redundant binary number is obtained. (4) Data output unit The data output unit 3 includes a binary conversion unit 31 that converts a binary coded redundant binary number into a two's complement binary number, and an output buffer 32 consisting of buffer registers B Y + to B Y H. ,
It consists of an output control section 33 and a counter 34. One data unit of the binary converter 31 is configured as shown in FIG. To convert a redundant binary number into a two's complement binary number, divide the redundant binary number into a binary number consisting of positive elements and a binary number consisting of negative elements, and calculate the difference in their binary operations. Just ask. The binary number (adfi-1 to ado) 2 consisting of the lower bit string of each digit of the binary redundant binary number represents a binary number consisting of positive elements, and the binary number consisting of the upper bit string of each digit (a llll+- 1”” a.m.), ha.
It represents a binary number consisting of negative elements. Therefore, by subtracting the above binary number, it can be converted into a binary number. At this time, subtraction can be calculated as addition of binary numbers in two's complement representation, so the binary numbers in two's complement representation (Oa dr+
-1~a do) c2 and binary number in two's complement representation (la
wn-t~N5lI)e2+ (1) It can be obtained by adding c2. However, Nsi is a value obtained by inverting a□. Further, O and 1 of the most significant bits of the addend and the summand are sign bits in two's complement representation, and the most significant digit b1 of the sum obtained at this time is the sign bit. The converted data is output to the output buffer 32, the address of the output buffer 32 is selected by the counter 34 updated by the output control section 33, and the sampling value series data Y1 to YN are sequentially output. (5) FFT calculation unit (a) FFT calculation unit The FFT calculation unit 2 has a butterfly calculation circuit of N/2 (=
v) Log the stages arranged in parallel, N (=U)
It has a mesh-like structure connected in cascade. The connection relationship is as shown in FIG. 4 in the case of 8-point data. In this case, the entire system is composed of three stages, and each stage is composed of four butterfly calculation circuits. (b) Butterfly calculation circuit One butterfly calculation circuit consists of a multiplication circuit 21 that multiplies the twiddle factor W, its output and input
The subtraction circuit 23 includes an addition circuit 22 that performs an addition operation with , and a subtraction circuit 23 that subtracts the output of the multiplication circuit 21 from the input A. As a result, an output having a predetermined relationship with respect to the input is obtained. The example in FIG. 5 is an example of time thinning, but it may also be configured with frequency thinning in which the sum and difference of two human forces are calculated and the difference is multiplied by a twiddle factor. Since the input and output data of the butterfly calculation circuit are complex numbers, they are calculated separately into a real part and an imaginary part. Specifically, it is configured as shown in FIG. The data of inputs Δ and B are input to A's buffer and B's buffer, respectively.
It is input into the human buffer. 24 is a memory that stores data regarding twiddle factors. Result of multiplication of B person buffer data and twiddle factor, Sl, S2, S3, S4
are B, CO3-, B, SINφ, BtC, respectively.
O3φ, B, and SINφ are output. In addition, S5 and S6 contain the addition and subtraction results, B1CO3φ10B+SINφ, B, CO
Sφ-B*SINφ is output. Furthermore, S7, S8,
As a result of addition and subtraction, All+BRCO3φ+BISINφ At−BヮSINφ+B, COSφ A, −BICOSφ−BfSINφ A□0B, SINφ−B, and COSφ are output to S9 and SIO, respectively, and Cm , Ct, DR, and Dt are obtained. 25a to 25d are upper digit processing circuits. The output of the redundant binary number of the butterfly arithmetic circuit also becomes the input of the redundant binary number of another butterfly arithmetic circuit. Therefore, it is necessary to match the number of significant digits of input and output. However,
Since addition using redundant binary numbers involves carry processing, the number of digits increases by 1 for each addition. Therefore, in order to keep the number of effective digits constant, it is necessary to reduce or reduce the increased number of high-order digits. The upper digit processing circuit performs a process of reducing the increased number of digits+1 digit to one digit. 26a to 26d are shifter circuits. In order to match the number of significant digits of input and output and improve calculation accuracy,
Outputs the value divided by (shifted to one lower digit). In such a case, the shifter circuit is operated to output 1/2 data. (b) Multiplier circuit The structure of the multiplier circuit is as shown in FIG. This multiplication circuit calculates partial products using the 2-bit Booth method. In this multiplication circuit, the multiplicand is a binary coded redundant binary number, and the multiplier is given as a two's complement binary number. In the case of 12-digit arithmetic, six partial products are generated, and they are generated in parallel by the first partial product generation circuit 41 to the sixth partial product generation circuit 46. And each partial product is 3
The partial product addition circuits (51 to 53) perform primary addition in parallel. The addition results of the partial product addition circuits 51 and 52 are subjected to secondary addition in the partial product addition circuit 61. Next, the outputs of the partial product adder circuits 53 and 61 are added three-dimensionally by the partial product adder circuit 71. At this time, the upper two digits are digits generated due to addition using redundant binary numbers, and the upper three digits are converted to one digit and output. The partial product generating circuit is specifically shown in FIG. A
is the deciphering part of the multiplier. In the first partial product, -2C2! ,
l+Cx□+C21-1 is calculated. The possible values of this result are (-2, -1, 0, 1, 2). When it is 0, it outputs 0. When it is 1, it outputs the multiplicand as it is, and when it is 1, it outputs the multiplicand as is.
When , the multiplicand is shifted upwards by one digit and output, -1
When , the level of each bit of the multiplicand is inverted and output,
When the value is -2, a partial product is generated by shifting the multiplicand upwards by two digits, inverting it, and outputting it. The figure shows a third partial product generating circuit. The 5.6.7th bit of the multiplier C,, Cs, C, is decoded and -
2, F34 becomes high level and the multiplicand (I, ,
, I, p) is (P dp+l + P sp+1
) is output as 2, F1a becomes high level and the multiplicand (I lip+ I, ,) becomes (P sp+
It is output as I r P dP or ). Also, -
When it is 1, F32 becomes high level and the multiplicand (I - P
, I dp) is output as (PdP, Psp). Also, when it is 1, F31 becomes high level and the multiplicand (I
-P, I, -) is output as (P,,.P,,). The output terminal of each partial product has a structure in which digits are aligned and each digit is arranged horizontally as shown in FIG. Such partial products are sequentially added in a regular manner by a redundant binary adder. In this example, the adder is configured to have three roles. (c) Adder circuit The adder circuit adds binary coded redundant binary numbers, and its one-digit configuration is shown in FIGS. 9 and 10. FIG. 10 is a further simplified version of the logic circuit of FIG. In addition using redundant binary numbers, redundancy can be used to prevent carries from lower digits from propagating. Therefore, addition involves the first step of calculating the sum of each digit (hereinafter this sum will be expressed as two digits; the upper digit will be referred to as the "middle carry" and the lower digit will be referred to as the "intermediate sum"), and the first step will be the sum of the intermediate sum and the lower digit. It can be calculated in two steps: the second step is to calculate the sum with the intermediate carry for each digit. That is, the representation of the intermediate sum and intermediate carry in the first step is devised so that no further carry occurs during the calculation in the second step. The intermediate sums and carries generated are shown in Table 1. In the case of 1.3.4.6, the expression method for intermediate carry and intermediate sum is unique, but no matter what kind of carry there is from the lower digits, the carry is not carried in the second step operation. It will never occur. In the case of 2 and 5, the method of expressing the intermediate carry and intermediate sum is not unique, but depending on the method of expression, an additional carry may occur in the second step operation. However, if the state of the lower digits is determined and expressed as a table according to that state, the second
No carry occurs in step operations. That is,
2.5, if there is a possibility of a carry of -1 from the lower digit, the intermediate sum is set to 1, and when there is a possibility of a carry of 1 from the lower digit, the intermediate sum is set to 1. sum -
By setting it to 1, it is possible to prevent carry from occurring in the second step calculation. FIG. 9 shows a first digit circuit for executing such an operation. S! 1 indicates the status of the addend and summand of the lower digit, and is a signal that becomes low level when at least one of them is negative. The summand is (ai1+adl), the addend is (b@+, bdt), and the addition result is (Za
□+Zdf). Both are binary coded redundant binary numbers. Further, (': at, = a□) represents an intermediate carry using a binary coded redundant binary number (negative logic). If such one-digit adders are connected as shown in FIG. 11, an N-digit redundant binary adder can be constructed. (6) Evaluation Table 2 shows the results of comparing the number of transistor elements and the number of logic stages in one butterfly arithmetic circuit between the two's complement binary system and the redundant binary system. The transistor is C
The evaluation was performed using MOS and the circuit shown in FIG. The redundant binary system is characterized in that the number of logic stages does not change even if the number of bits increases, and the calculation speed can be kept constant regardless of the number of bits. In case of 1024 points data input,
The butterfly operation circuit requires 10 stages, and the FFT operation section can be configured with 380 logic stages. Including the 8 stages of the output binary number converter, the device can be configured with a total of 388 stages. The number of stages can be 172 or less in the 16-bit binary system, and therefore the conversion speed can be 172 or less. (7) Another embodiment The structure is shown in FIG. 12. The FFT calculation unit 2 includes N/2 butterfly calculation circuits B arranged in one stage in parallel;
~B It is composed of H/2. After completing the first stage of processing,
The output data of the N points is input again to the FFT calculation circuit via the shifter circuit 8 and the multiplexer 9. FFT is performed by executing such calculations for a predetermined number of stages. The shifter circuit 8 is
This is a circuit for controlling the combination of input data for calculations at each stage, and its specific 1-bit configuration is the 13th
As shown in the figure. The figure shows a case where the number of input data points is 64. Since one of the two outputs of the butterfly arithmetic circuit can always be input to one of the same arithmetic circuits, the number of input/output terminals of the shifter circuit is 32. Control signal C5~
C6 is inputted after each stage's calculation is completed, and the flow of data is controlled by switching the gates so that the output data of that stage becomes the input data of the next stage. With such a configuration, the number of butterfly calculation circuits can be reduced to half the number of input data points.

【Effect of the invention】

The present invention is characterized in that the adder circuit in the FFT butterfly arithmetic circuit is configured with an adder circuit using redundant binary numbers in which carry does not propagate upward. Therefore, regardless of the number of digits, the addition time can be reduced to a constant value, and the speed of butterfly calculation and FFT can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an FFT device according to a specific embodiment of the present invention, and FIGS. 2 and 3 show the configurations of a redundant binary conversion section and a binary conversion section, respectively. FIG. 4 is a block diagram showing the configuration of the FFT calculation section, FIGS. 5 and 6 are block diagrams showing the configuration of the butterfly calculation circuit, and FIG. 7 is the configuration of the multiplication circuit. 8 is an electrical circuit diagram showing the configuration of the partial product generation circuit, FIGS. 9 and 10 are electrical circuit diagrams showing the 1-digit configuration of the adding circuit, and FIG. is a block diagram showing the configuration of an adder circuit, FIG. 12 is a block diagram showing the configuration of an FFT device according to another embodiment,
FIG. 13 is an electrical circuit diagram showing the configuration of a shifter circuit used in the device.

Claims (8)

[Claims] (1) A butterfly operation circuit comprising a multiplication circuit that outputs data obtained by multiplying input data by a twiddle factor, and an addition/subtraction circuit that outputs data obtained by calculating the sum and difference of two input data. The partial product generation circuit in the multiplication circuit processes the multiplicand, which is the input data, as a redundant binary number and outputs the partial product as a redundant binary number, and the circuit for calculating the sum of partial products in the multiplication circuit 1. A butterfly calculation circuit for a fast Fourier transform device, characterized in that said addition/subtraction circuit is constituted by a redundant binary addition circuit which performs an addition operation using redundant binary numbers so that a carry does not propagate to higher digits. (2) The multiplication circuit calculates each partial product in parallel,
Redundant 2, which calculates the sum of the partial products two by two by tree-like connection
2. The butterfly arithmetic circuit for a fast Fourier transform device according to claim 1, wherein the butterfly arithmetic circuit is constituted by a parallel multiplier circuit formed by a combinational circuit using a base addition tree. (3) The multiplication circuit is constructed using a 2-bit Booth method that converts the multiplier into a radix-4 extended SD (signed digit) representation and calculates a partial product for each digit. A butterfly arithmetic circuit for a fast Fourier transform device according to claim 2. (4) Basic calculation of the butterfly calculation circuit, which consists of a multiplication circuit that outputs data obtained by multiplying input data by a twiddle factor, and an addition and subtraction circuit that calculates the sum and difference of two input data and outputs the data obtained. In a fast Fourier transform device configured as a circuit, the partial product generation circuit in the multiplication circuit processes the multiplicand, which is its input data, as a redundant binary number and outputs the partial product as a redundant binary number; The calculation circuit for the sum of partial products and the addition/subtraction circuit in
A fast Fourier transform device comprising a redundant binary adder circuit that prevents carry from propagating to higher digits due to addition operations based on base numbers. (5) The arrangement of the butterfly arithmetic circuit is configured in the form of a mesh in which parallel processing circuits each having N/2 butterfly circuits arranged in parallel are connected in cascade in a predetermined connection relationship in log_2N stages for input data at N points. A fast Fourier transform device according to claim 4, characterized in that: (6) For input data at N points, a parallel processing circuit in which N/2 butterfly calculation circuits are installed in parallel, and N output data from the parallel processing circuit are processed in a predetermined order that differs for each processing step. 5. The fast Fourier transform apparatus according to claim 4, further comprising a control means for repeating the processing to be rearranged by logic and input to the parallel processing circuit by a number of log_2N steps. (7) Redundancy 2 that converts N points of input data into redundant binary numbers
Claim 4, characterized in that it has a decimal converter.
The fast Fourier transform device described in . (8) The fast Fourier transform device according to claim 4, further comprising a binary transform unit that converts the N-point data after Fourier transform into a binary number.