JPS62219141A - Mutual supervisory system in processor - Google Patents

Abstract

PURPOSE:To eliminate the waste to consume time due to an unnecessary polling by making mutually different the period of a polling signal sent from the process to execute the data communication mutually to an opponent side. CONSTITUTION:When the time limit t1 of the timer of a process 11 is shorter than the time limit t2 of a process 21 and the timer 22 of the process 21 receives the polling signal from the process 11, resetting is executed by the output of a detecter 23 two times when the signal is received and when a response signal (ACK signal) is returned to the process 11 in response to it, and finally, counting is started from the time to return the response signal. Since the time during from the time when the polling signal is received to the time when the response signal is returned, is significantly short, the time is neglected and then, t1<t2 is obtained. Consequently, next when the polling from the process 11 is executed after t1 is elapsed, the timer 22 of the process 21, before it never arrives at the time limit t2, is reset by the output of the detecting device 23.

Description

[Detailed Description of the Invention] [Summary] In a processor system in which a plurality of processors are connected via, for example, a packet switching network, each processor uses a The processor is equipped with a timer that is reset by sending or receiving a polling signal or data signal between the processor and the other processor, and this timer times out at a different time for each processor so that the polling signal is sent to the other process. This prevents polling of both processors from occurring at the same time.

[Industrial application field]

The present invention relates to a method for monitoring abnormalities in a process in a processor at the other end of data communication in a network system in which a plurality of processors are connected by, for example, a packet switching network.

This kind of monitoring wastes resources such as memory if the memory for data communication remains unreleased even if there is an abnormality in the other processor and data communication is impossible. This is being implemented to free up these resources as soon as possible.

[Conventional technology]

In a system in which two processors perform processing while exchanging data with each other, each processor polls the other processor at certain intervals and returns a response in order to confirm that there are no abnormalities in the other processor. When a response signal indicating that there is no abnormality is returned, it is confirmed that there is no abnormality! I recognized it.

Considering the case where one processor A polls the other processor B, when processor B is polled, processor B can identify that there is no abnormality in processor A because processor 8 has polled. When polling is not performed, it is not possible to identify whether the problem is due to an abnormality in processor A or not.

In order to solve this problem, processor B also polls processor A and requests its response.

[Problems to be Solved by Invention C] In this way, in a system where both processors poll each other, if the polling cycles are the same, both processors will poll at the same time when the timings match. Although polling from one side alone can identify that there is no abnormality in both processors, this results in extremely wasteful processing.

Also, when a processor is processing multiple processes, the processes may communicate with different processors, or even if the processors are the same, there may be differences in whether the processing is performed normally or not. Therefore, it is necessary for each processor to monitor the status of the other processor.

[Means for solving problems]

FIG. 1 is a principle diagram of the present invention, in which three processors 1
0,20. '30 are interconnected by a network 40, preferably equipped with switching functionality, such as a packet communications network, with processor 10 connecting process 11.16, processor 20 connecting process 21.26, and processor 30 connecting process 21.26 to process 21.26; Processes 31 and 36 are being processed, and process 11 of processor 10 is processing process 2 of processor 20.
1 and the process 16 of the processor 10 is the processor 30
process 31 of processor 20 and also process 26 of processor 20
It is assumed that each of the processes 36 and 36 of the processor 30 is exchanging data.

These processes 11, 16, 21, 26, 31. 36
are each timer 12.1? , 22, 27. 32, 37
These timers are used for polling by sending polling buckets with different time limits LI, j2 between processes exchanging data with each other.

These processes 11, 16, 21, 26, 31.36 further include detectors 13.18, 23.2B.

33 and 38 are provided, and the timers 12, 17,
22, 27, 32, and 37 are reset to start a new time measurement.

[For production]

An example of data exchange between the process 11 of the processor 10 and the process 21 of the processor 20 will be explained with reference to the time chart of FIG. 2.

Process 11 timer time limit 1. is shorter than the time limit t2 of the timer of process 21.
When the timer 22 receives the polling signal from the process 11, it is reset by the output of the detector 23 twice, once when this signal is received and when a response signal (ACK signal) is returned to the process 11 in response. However, the time measurement starts from the time when the response signal is returned. The time from receiving this polling signal to sending back the response signal is extremely short, so if we ignore this time, it will be 1, < 1
2, the next time there is polling from the process 11 after t1 has elapsed, the timer 22 of the process 21 is reset by the output of the detector 23 before the time limit t2 is reached.

As shown on the left side of FIG. 2, when an abnormality occurs in the process 11, polling is not performed even after time t1 has elapsed since the previous polling, and when time t2 has elapsed, the timer 22 of the process 21 reaches its time limit,
In contrast to what has been done up until now, the process 21 will poll the process 11, and the polling will be repeated at this period of t2 until the abnormality in the process 11 is resolved.

If the abnormality in process 11 is resolved, process 11 will eventually change to process 2, since the time limit t of the timer of process 11 is shorter than the time limit L2 of the timer of process 21.
Return to the state of polling 1.

What has been described above applies between the process 26 of the processor 20 and the process 36 of the processor 30, and between the process 16 of the processor 10 and the process 31 of the processor 30.
The same is true between the timers 22 and 2 of the processor 20.
7 are both t2, timers 32 and 3 of the processor 30.
For the processor 10, the time limit of the timer 12 of the process 11 is shown as t11, and the time limit of the timer 17 of the process 16 is shown as t2. By setting the time limits of the timers of the processors connected to the network to be different, the above-described effect can be achieved regardless of which processor the data is transmitted to.

Furthermore, although the above explanation has only been about the sending and receiving of polling signals and response signals thereto, it is equivalent to polling signals in that it is possible to identify an abnormality in the other party's process even if a data signal is sent and received normally. It is clear that unnecessary polling can be avoided by resetting the timer by transmitting and receiving this data signal.

〔Example〕

Figure 3 shows the functional configuration when a logical path is formed between processor A and processor B. An application process (Func AsFunc B) that wants to perform data communication between these processors is Communication is performed via communication processes (IPCA, IPCB).

FIG. 4 shows an embodiment of a processor to which the polling method according to the present invention is applied.
It has a value of 0,150.

This intercomputer communication process 50 includes a transmission function section 51,
It includes a reception function section 52 and a timer 53, and when the reception function section 52 receives a data packet from another processor via a packet switching network, it transfers the data to the application process 40, and when it receives a polling packet. Sometimes a polling response signal (ACK
The timer 5 requests the transmission function section 51 to send a signal (signal), and when data or polling packets are received.
Send a reset signal to 3.

The transmission function unit 51 transmits each packet to the packet switching network via the transmission/reception control unit 90 in response to a data transmission request from the application process 40, an ACK signal transmission request from the reception function unit 52, and a polling transmission request from the timer. Send.

The second application process 140 is provided with a second intercomputer communication process 150, but the timers of these processes 40, 140 are different from the timers of the partner processors that perform data communication with this application process 40, 140. The sending time of the polling sending request signal is set so that the polling period is different.

After sending the polling packet to the other processor, A
In this embodiment, the above-mentioned timer 53 is also used to measure the time until the CK signal is returned, and if the ACK signal is not returned within a predetermined time, This timer 53 notifies the application process 40 that there is an abnormality in the partner processor.

〔Effect of the invention〕

Since the cycles of polling signals sent from processes that communicate with each other to the other side are different from each other, polling signals from both processors are not sent at the same time, thus wasting time due to unnecessary polling. A special effect can be achieved in that consumption waste can be eliminated.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a time chart of polling signals, FIG. 3 is a diagram showing the functional configuration of data communication, and FIG. 4 is a diagram showing an embodiment of a processor to which the present invention is applied. It is a block diagram. 10.20.30 is a processor, 40 is a line network, 12.
17, 22, 27, 32, and 37 are timers.

Claims (1)

[Claims] A plurality of processors (10, 20
, 30--), each processor has a timer (12, 17, 22, 27, 32, 37---
---), and these timers poll the other side at different time periods between processor processes that mutually transmit data.