JPS62217785A - Data control circuit - Google Patents

Abstract

PURPOSE:To correctly expand burst data to continuous data by permitting a data volume discrimination circuit to discriminate the volume of the burst data so as to control a clock generator circuit and changing output numbers such as a serial clock number. CONSTITUTION:A shift clock inputs an input data IND 7 to a shift register 9. Whenever data is inputted to the shift register 9 in serial eight bit terms, a load clock is inputted to a parallel register 8, and the output (eight bits) of the shift register 9 is transferred to the parallel register 8. D1, D2... comprise parallel data at the top of a sound burst. The volume of burst data of one field is 34168 bits, 4271 words translated into one word of eight bits. As a result the final word number of the burst is D4271. The clock WCK of an address counter in an address circuit 10 arises in synchronization with the load clock PCK, and its address is sequentially counted up.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a buffer RAM control circuit for a transmission rate converter that converts burst data into continuous data, and particularly relates to a buffer RAM control circuit for a transmission rate converter that converts burst data into continuous data.
The present invention relates to a data control circuit suitable for expanding burst data having different amounts of data depending on the field, such as a USE audio burst signal.

[Conventional technology]

Systems for multiplexing PCM audio and video signals include a subcarrier method and a single time division multiplexing method. Regarding the former,
For example, it is reported in the Report of the Satellite Broadcasting Reception Technology Study Group, Part 1, "Satellite Broadcasting Receiver" (Reference 1), published by the Radio Technology Association (June 1920). Regarding the latter, N
Reported in HK Giken Monthly Report Volume 27, No. 7 (July 1980) [New Transmission Method for High-Definition Television ~MUSE~'' (Reference 2) (MUSE: MJkltip
le 5ub-Nyquizt SamplingE?
Lcoding). The audio signal transmission method in the MUSE method is RF multiplexing on vacant vertical blanking.
This is a time division multiplexing method. The symbol rate of PSK modulation is 16.2Hz, which is the same as the video resample clock.

The bit rate of data expanded by the decoder is 2.048
Although it is written that it is MH2, nothing is presented about data distribution during data compression.

[Problem that the invention seeks to solve]

The latter document showing the above-mentioned prior art does not provide any information regarding data allocation during data compression or data decompression means in the receiver. M in document 2
The time division multiplexing method for audio signals in the USE method simply time-compresses and multiplexes PCM signals in the digital signal format of the subcarrier method used in the Japanese broadcasting satellite B5-2 (see Document 1). This subcarrier method is in the practical stage, and by using the Kono format, encoders or decoders can be shared.

The vertical blanking frequency is equal to the field frequency=Hz (NTSC system). When the PCM audio signal is uniformly distributed to each field, the amount of data per field is: PCM audio transmission rate 2.048M h p
, r divided by the field frequency.

In other words, 2.048 x 10'÷'' rainbow = 34167-! -1
,00115. In this way, a fraction of -i is generated. As a countermeasure for this, for example, normally 34167 bits are sent per field, and 7 extra bits of data are sent once every 15 fields. Alternatively, normally send 34168 bits, 15
It is necessary to provide a field that is reduced by 8 bits once.

As described above, there is a problem in that the amount of burst data within a field is non-uniform.

An object of the present invention is to compress the data on the time axis and to solve the problem of irrespective of the amount of data that occurs when the data is distributed to each field.

-1, and to provide a data control circuit that correctly processes data even when the fraction of write data to RAId is less than the number of 1 word pits.
be.

[Means for solving problems]

The above purpose is to send, on the transmitting side, an identification code indicating the amount of data, separately from the data, for burst data of field units having different amounts of data.1. On the receiving side, a separate circuit detects this identification code and determines the amount of data.

A clock generation circuit whose clock generation is controlled by this data amount determination circuit, this clock? A serial-to-parallel conversion register and buffer RAIt that receives the clock of the generation circuit as input, a write address circuit that is also controlled by the clock generation circuit, and a read address circuit that operates asynchronously with the write side.

This is achieved by providing a parallel-to-serial conversion register for data output.

[Effect]

The data amount determination circuit determines the amount of received burst data and controls the clock generation circuit.

The clock generation circuit outputs a serial clock and a parallel load clock for a serial-to-parallel conversion register that converts input data from serial to parallel, and an address counter clock for a write address circuit. Serial clock number, road clock.

The number of outputs and the number of address counter clocks are controlled by the data amount discrimination circuit, and the number of outputs changes. As a result, burst data can be continuously written into the buffer RAM without data loss.

〔Example〕

Hereinafter, one embodiment of the invention will be described with reference to FIG.

1 is a data amount determination circuit that determines the amount of received burst data, 2 is a judgment output terminal, 3 is a clock generation circuit for data writing, 4 is a shift clock terminal of the shift register 9, and 5 is a load clock terminal of the parallel register 8. ,
6 is an address count clock terminal of the write address circuit 10, 7 is a received input data terminal, 11 is a read address circuit that receives a clock (RCK) as input, 12
is a multiplexer (JfPX) that switches write address and read address, 13 bar f-9 memory tRA
M, 14 is a parallel register that serially outputs parallel data read from m13; 15 is an output data terminal; 16 is a control signal detection circuit.

FIG. 1 shows an example of a circuit for receiving MUSE signals, and the signal transmission format will first be explained. The audio data transmission format is set according to document (2). As mentioned above, 341 per field
This field is set to 68 bits, and this field is set as a normal field, and the field reduced by 8 bits to 34168 bits is set as a leap field.

1 of 14 normal fields and 1 leap field
The format will be five rounds of the field. As a means of identifying whether the transmitted field is a normal field or a leap field, a leap field identification code is sent on the transmitting side.

For example, it is provided at the beginning or end of the data burst.

Furthermore, it is possible to transmit using the control signal area used in video. (Refer to Table 3 in Reference 2)
By detecting this leap field identification code,
The amount of burst data is determined by a data amount determining circuit. Next, the circuit operation will be explained using the circuit shown in FIG. 1 and the time chart shown in FIG.

In FIG. 2, 17α and 17b are audio burst signals,
18 is a video signal indicating time division multiplexing.

The lower part of Figure 2 (A
) Shown in (B). 107 is a signal of the input data (IND), 104 is a signal (S(1)) of the shift clock terminal 4 of the clock generation circuit 3, which is a shift clock; 119 is a signal of the first bit output terminal 19 of the shift register 9 (S
D), 105 is a signal <pcx) of the rod clock terminal 7 of the clock generation circuit 3 and is a load clock. 120
is the 8-bit data (RD) of parallel register 8, 10
6 is the counter clock of write address times M10 (
WCK), and 121 indicates the address (ADD) of the write address circuit 10.

The number written above the input data 107 is a serial data number in burst units, and the numbers written inside the input data 107 and inside the output signal 19 are serial numbers within one 8-bit word.

Input data 107 is input to shift register 9 using shift clock 104 . Every time 8 bits of data are serially input to the shift register 9, the load clock 105 is input to the parallel register, and the output (8 bits) of the shift register 9 is transferred to the parallel register 8. Data 106 in parallel register 8 corresponds to one word of RAM write data. As shown at tl in FIG. 2(A), from the beginning of the audio burst, parallel data 1zo(
RD) is followed by Dl, D2, and so on. The amount of burst data for one field is 34,168 bits, which is 4,271 words when converted to 8-bit l-word. Therefore, the final word number of the burst is D427 as shown in Figure 2 (B).
It is 1.

Address counter clock 106 of address circuit IO
(TI7CK) is o-tokuo,ri105 (
It occurs in synchronization with P(1), and the addresses increase sequentially.

RAM 13 and general-purpose RAM 6 bits (lX819ㅅ)
When using , one cycle of the address is 1 to 8192.

As mentioned above, the data word is 1 field unit.
~4271, and therefore the word number (RD) and address number (ADD) do not necessarily match.

In Figure 2(B), the word number (RD) and address number (
ADD) is an example of a coincidence. Second (A
) In the figure, the new data word starts from Dl, while the address is the last address of the previous field, A4271.
Since the data word number and address number do not match, the data word number and address number do not match. On the read side, the read address is continuously counted up (1 to 8
192), decompressed (continuous) data can be easily read without any control of the read clock.

The end of the leap field audio burst signal has 8 bits less than other fields. For example, m 3 c/
i) Shown in the figure. 17C is a leap field audio burst signal, and as shown by the dotted line 22, this field does not contain data in other fields.

The leap field is determined by the control signal detection circuit detecting the leap field identification code. At the time of the IJ-p field, the data amount determination circuit 1 controls the clock generation circuit 3 and converts the shift clock 104 (S(1) into the audio burst signal 17 C tail ta (input data bit 34160
) to stop. Similarly, the load clock 105 (4
270 outputs) and stop.

As a result, the transfer of the input data 107 to the shift register 9 is stopped at the input data pit number 1 up to 34160, and the 8 bits of data n are not input. Also, the last parallel data 120 is D427G. Address clock 106 also stops in synchronization with load clock 105, and address A 427G is held.

In the next field (Fig. 3(B)), the shift clock 104 is regenerated at 1+, and the load clock 105 is generated at ts.
, the counter clock 106 is regenerated.

In this way, Leapfield allows you to input data and
Since the RAM address skips 1 word and 8 bits, data can be written to the RAM without any apparent loss of data, and on the read side, the data is read like a normal field without being identified as a leap field. can be read from RAM.

Next, FIG. 4 shows an embodiment in which stable operation of the circuit is achieved by changing the data allocation for each field and reducing the speed of digital signal processing.

In FIG. 4, the edict demodulates a QDPSK modulated audio signal, and 24a and 24b are IDATA.

This is the output terminal of each QDATA. This parallel 2
The serial signal obtained by parallel-to-serial conversion of the bit signal is used in the previous circuit example [l! This corresponds to the input data 7 in Figure 1]. In the MUSE method, this input data 7 is 32
．． It is a very high speed signal of 4MbP #. As shown in Fig. 4, if the 2-bit parallel signal from the QDPSE demodulation circuit is decompressed in parallel using two decompression circuits, the signal processing speed can be reduced to 1/2, resulting in stable circuit operation. I can do it.

26b is serial parallel conversion circuit for IDATA and QDATA, 13g and 13A are IDAT.
A. RA for expansion of each QDATA! h1.14
α, 14b is a parallel-to-serial conversion circuit for IDAT4 QDATA. n's parallel-to-serial conversion circuit is the IDATA after decompression.

It converts QDAl''A into a serial signal, and the path is the serial output data terminal after decompression.

In this circuit, the IDATA system and QDATA system operate in exactly the same way, so only the IDATA system will be explained.

In addition, the burst data to be distributed to the fields is based on the control signal multiplex format shown in Figure 12 of Reference 2 (page 128), so that the audio in the field with the smaller line number (hereinafter referred to as the odd field) is horizontal, the line with the higher number, and the field with the larger number (hereinafter referred to as the odd field).
It can be seen that the sounds of the even field (hereinafter referred to as even field) are arranged in 37 horizontal lines. In terms of the number of bits, the odd field is 346 lines/37 lines proportionally distributed.
24 bits can be allocated to even field 33712.

Therefore IIMTA.

Ql) ATA When divided into two systems, the number of odd/even bits becomes 17312/16856 bits. If these are written to RAM in 1 word of 8 bits, the number of words becomes 2164.
Word (odd), 2]07 word (even).

By the way, at Leapfield, IDATA
.

Since there are 8 bits less in total than QDATA, IDATA
.

Each QDATA is reduced by 4 bits. Therefore,
The last written word of the leap field data burst signal is one word of 4 bits, which is less than 8 bits.

The circuit operation including data processing at this time will be explained below.

The circuit operation of FIG. 4 will be explained in conjunction with the time charts of FIGS. 5 to 8. 4 is an audio burst signal in an odd field, and □□□ is an audio burst signal in an even field. 124a is an IDATA signal (IND) input to the serial-to-parallel conversion circuit 26a; 125 is a shift clock (SCK) for the serial-to-parallel conversion circuit 26a;
131! This is the first bit output signal (SD) of the serial-to-parallel conversion circuit 26g. 126 is the load clock (PCK) of the serial-parallel conversion circuit 26a.
, 132 is the 8 bits/,a of the serial-parallel conversion circuit
Rarel data (RD). 133 is a counter clock (WCK) of the write address circuit 10, and 134 is a write address (ADD). ID in odd field
ATA is 17,312 bits, so the input IDATA 24α of the serial-to-parallel conversion circuit 26α is up to 17,312 bits.A shift clock 125 is generated in response to this, and the parallel clock 126 converts it into parallel data 132 in 8-bit increments and writes it into the RAM. . As mentioned above, in odd fields, shift clock 12
The clock generation circuit outputs 17312 clocks 5, 2164 parallel clocks 126, and 2164 counter clocks 133 each. In the even field, 16856 shift clocks 125, 2107 load clocks 126, and 2107 counter clocks 134 are output from the clock generation circuit. Odd field detection is performed by the control signal detection circuit 16, and through the data amount discrimination circuit,
Controls the clock generation circuit.

Odd field signals are in IIUSE format (
According to the diagram on page 281 of Reference 2, the field before the frame pulse line is an odd field, and the field after the frame pulse line is an even field.

An example of Leap field signal processing will be explained with reference to FIG. IDATA 124g has 4 bits (for IDATA) less than other fields, as shown in A.

At this time, the shift clock 125 stops at 17308 bits, and the subsequent 4 bits of data are not input to the shift register and are held until the next field. Further, the load clotter 126 stops at 2163 pieces.

Similarly, the address counter clock 133 stops at 2163, so the address is held at A2339 until the next field.

Then, at the beginning of the next field after the leap field,
As shown in FIG. 3B, the shift clock 125 is regenerated from the beginning t6 of the data, and IDATA 124α is input to the serial-parallel conversion circuit 26α following the last 4 bits of the previous field. When the data in the serial-to-parallel conversion circuit 26α reaches a total of 8 bits, including the last 4 bits of the leap field and the first 4 bits of the next field, the load clock 126 is generated at t, and the RA
One 8-bit word written to M is established. At the same time, the address counter clock 134 is generated and the address "
A2340'' is output. After this, the load clock 126 and the counter clock 133 are generated every 8 bits. The last signal of the field shown in FIG. 6(B) is shown in FIG. 7(,1). As shown in 124C, this field contains data numbers 16853 to 16856.
The same CB whose 4 bits are a 4-bit fraction due to the word structure
>As shown in the figure, together with data numbers 1 to 4 of the next field, one word is formed. This word structure spanning fields continues until the next leap field.

Then, in the next leap field, as shown in the 8th (Al), the data number ends at 16852 (even field), so it is completed with 1 word of 8 bits.Here, it returns to the normal form.Therefore, the next At the beginning of the field (FIG. 8(B)), data is written in the form of one word starting from the first eight bits.

As described above, although the write word structure of the audio/list signal differs depending on the field, it can be sequentially written into the RAM without any gaps, and the embroidery can be used efficiently. And on the read side, the read address time W
By simply counting up the counter 811 one after another without determining the leap field, data can be read and the data can be expanded correctly.

The ninth factor is an example of the internal circuit of the clock generation circuit 3 in FIG. 4, and shows a generation circuit for the load clock 126 and the counter clock 133. Moreover, FIG. 10 is an operation time chart. A is a counter that counts up at the rising edge of the shift clock 125, 37.
39 is an inverter, 38.40 is an ANI) gate, 41
．． 42 is an SR latch composed of a NOR gate. The load clock 126 is the output of the counter qA, Qs,
An ANDNO gate with QC and inverter 37 as inputs is obtained. Signal 43 is 4 to load clock 126.
A counter clock 133 (rl'(1)), which is a signal with a bit phase difference, is obtained from the SR latch (41, 42) which receives the load clock 126 and the signal 4 as input.

The above is an example of a leap field in which a 4-bit fraction occurs, but other numbers of bits can be generated by changing the number of bits in the counter and the decoded value.

〔Effect of the invention〕

According to the present invention, even if the fraction of data resulting from non-uniformity of burst data due to leap fields etc. is less than the number of 1 word pits of the RAId for burst data expansion, burst data can be processed by write data processing and write address processing. Can be correctly expanded into continuous data.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIGS. 2 and 3 are time chart diagrams showing the operation of the circuit of FIG. 1, and FIG. 4 is a circuit diagram of another embodiment of the present invention. Figures 5 to 8 are the 4th
FIG. 9 is an internal configuration diagram of the clock generation circuit 3 of FIG. 4, and FIG. 10 is a time chart showing the circuit operation of FIG. 9. l... Data amount determination circuit 3... Clock generation circuit 8... Parallel register 9... Shift register 1
0...Write address circuit 11...Read address circuit 13...RAM 17a, b, 29.30-...Audio burst signal 1
05, 126...Load clock 104, 125
...Shift clocks 106, 133...Counter clocks 26α, b...Serial to parallel conversion circuit 1
24α...IDATA 124b...QDATA ゛,,,,'

Claims (1)

[Claims] 1. In a transmission rate conversion circuit that writes data to a buffer RAM in synchronization with the input transmission rate of burst serial data and reads data from the buffer RAM in synchronization with the transmission rate of output data, the burst serial input data is buffered. A serial register and a parallel register that convert into word-by-word parallel data for storage in RAM, a RAM write address circuit, a serial clock that drives the serial register, a parallel load clock that drives the parallel register, and a RAM write address clock. An output clock generation circuit, a burst data amount determination circuit, a read address circuit for the RAM, and a parallel-to-serial conversion register that converts RAM output data into serial data are provided, and the output of the data amount determination circuit corresponds to the input amount of data. A data control circuit characterized in that the serial clock, parallel clock, and address clock of the clock generation circuit are outputted intermittently to continuously write data to the RAM regardless of the amount of individual burst data.