JPS62215968A - Copying device - Google Patents

Abstract

PURPOSE:To operate in an optional mode by a small storage capacity, by providing an interface which can input a program prepared in advance, from the outside, and storing the inputted program in a nonvolatile memory. CONSTITUTION:A CPU 1 and a CPU 2 use a data bus 5, and execute mutual communication by executing a serial transfer. To the master CPU 1, for instance, a CPU 3 using mu PD 8041A is connected by a bus, and also, to its CPU 3, connectors RXDI, II, TXDI, II of full duplex 2 channels selected by a dip switch DIPSW are connected, and they are connected to a computer of the outside. In such a way, information such as a program and a data, etc. can be loaded to a memory in a short time, and by a small memory capacity, a copying device can be operated in an optional mode requested by a user.

Description

[Detailed description of the invention] 〔Technical field] The present invention relates to a copying apparatus.

[Prior Art] It has become necessary to prepare a plurality of operation programs for recent copying apparatuses due to the fact that it has become easier to realize multiple functions through the use of microcomputers, and the functions requested by users have become more diverse. In particular, when exporting to a foreign country, a set of operating programs tailored to the export destination is required, such as matching the characters displayed on the character display to the language of the export destination.

Conventionally, this problem has been dealt with by storing multiple operating programs in memory in advance, and selecting each program using a dip switch, or by inputting and storing the required operating program using manual keys from the operation panel. was.

However, the former has the problem that the amount of data and programs that can be stored is limited by the memory capacity and the number of dip switches, and cannot meet a wide range of requests.On the other hand, the latter has the problem that input operations are complicated and require a lot of time and effort. was there.

[Objective] The object of the present invention is to provide a programmable copying apparatus that can freely select a copying operation program and easily set it in a short time, and that can provide functions that meet the user's requirements with a small memory capacity. do.

[Configuration] Therefore, the present invention is characterized in that an interface means consisting of a microcomputer, a connector, etc., which can input a pre-prepared program from the outside is provided, and the input program is stored in a non-volatile memory.

The present invention will be explained in detail below.

FIG. 1 shows a configuration diagram of a control device of a copying apparatus according to the present invention, in which a microprocessor (hereinafter abbreviated as cPU) 1
controls the copying apparatus according to key information from the cPU2, peripheral information or program information from the CPU3, and input information from the input/output (Ilo) device 114 connected to the CPUI. The CPU 2 implements communication between the CPU 2 and the CPU through serial transfer.

CPU I and CPU 2 communicate with each other using data bus 5. CPU2 is CPU
It is a slave cPU with the master CPU as the master CPU.

The power supply voltage monitoring circuit 6 is I! ! Generates a reset signal for a fixed time when the main input is turned on. Also, the 5v voltage is 4.5v
This circuit generates a reset signal m for a certain period of time when the time is below. This reset signal ffl is used by CPUI, CPU2
．． CPU3. It is connected to the input/output device 4 and the battery backup circuit 7.

In the battery backup circuit 7, immediately after the power is turned on,
Since the reset signal m becomes LOW level, transistor Tr+ becomes OFF state, and transistor Tr2 also becomes OFF state.
It becomes FF state. Therefore, the control voltage Vcc of RAM8
becomes the voltage of the backup battery ([1T1) 3V.

Also, the chip select signal U also indicates that the transistor Tr+ is O.
Since it is FF, it will be 3v. Therefore, RAM8 cannot be written to or read from, and even when the power is turned off, the transistors Tr1. Since Tr 2 is in the OFF state, RA
M8 is in the above state. At this time, RAM8 is connected to the battery BT.
Memory data is held by I, but areas other than the RAM area that needs to be backed up are cleared when the power is turned on. When the reset signal RESET becomes H level after a certain period of time, the base current flows to the transistor Tr+ through the Zener diode ZDI, so Tr+ turns on and the Tr
z is also turned on. When transistor Trz turns on, RAM
The control voltage Vcc of No. 8 becomes 5V. Transistor Tr2
When it turns on, the terminal becomes LOV and the RAM 8 becomes readable and writable.

Since the power supply voltage monitoring circuit 6 does not operate normally unless the power supply voltage Vcc becomes 3V or more, the Zener diode zD1 is used to cut off the transistor Trx so that it does not turn ONL if it is less than 4V. The CPU 1 monitors the voltage of the battery BTI using the A/D input terminal AND, and when the voltage reaches 2.8V, the CPU 1 determines that the voltage has dropped and outputs the LE signal through the input/output device 4.
Turn on D1.

RAM8, when the a terminal becomes LOII, cpui
The chip is selected by , and reading and writing are performed using the RD and VR times signals of the CPUI.

The CPU 3 uses an internal timer counter to create a serial clock and performs serial transmission and reception using an internal program. Full duplex 2 channel RXD I.

Processes TXD I, RXD II, and TXD■.

When the CPU 2 receives the display data from the CPU that controls the operation unit, it scans the driver 9 and at the same time drives the driver 10 based on the data, selectively lights up the LED of the matrix and reads the address ADDRESS.
and data DATA on the display 11.1 on the operation panel.
Display on 2. Further, the pressed state of the key KEY is scanned by the driver 9, input via the buffer 13, and transferred to the CPUI as key data.

The CPUI is connected to the decoder 15 . via the address bus 14 . R
Specify the addresses of OM16 and RAM8 to input and output data.

FIG. 2 shows a part of the panel of the operation section. On the operation panel 17, there are 1 displays 11, 12, address set L.
E018, address set key 19, program set LED 20. Program key 21. recall key 22,
A write key 23 and a numeric keypad 24 are arranged, and using these, it is possible to change or modify a part of already stored programs and data.

That is, press the program key 21 and select program set L.
Check that the HD20 is lit and press the address set key 19. Next, check that the address set LE018 is lit and operate the numeric keypad 24 to set the address.
The address is displayed on the display 11.

Furthermore, when you press the recall key 22, the contents of that address will be displayed on the display 12, so if you change the displayed contents by operating the numeric keypad 24 and then press the light key 23, the contents of that address will be displayed. The changes and corrections are completed.

Figure 3 shows the overall flow of processing performed by the CPU 2, which consists of multiple subroutines, and the subroutine 30 initializes each boat, sets the interrupt mode, clears the RAM, initializes the RAM, etc. In the subroutine 31, the generation process of the scan signal to be output to the driver 9 is performed.In the subroutine 32, the signal corresponding to the scan signal is checked and the specified key human power signal is checked, and the specified key human power is detected. Subroutine 3 writing to signal RAM
In step 3, the contents of the designated display RAM are output in response to the scan signal. The other subroutines will be explained sequentially with reference to the drawings.

FIG. 4 shows the processing of the program key 21 check routine in the CPU 2.

The CPU 1 checks whether the program key is pressed before the numeric keypad 24 is pressed. If the program key is pressed, check whether the program mode is canceled. To cancel program mode, program L
ED OFF, address set LED OFF.

Reset flags related to program mode and initialize RAM.

If the program mode is set, check whether the program mode can be accepted. If it can be accepted, turn on the program LED, set the program mode flag,
Use the numeric keypad to set the flags in the 1st, 2nd, 3rd, and 4th digits of the address to "0".Then, set the program display RAM to "0".
0".

FIG. 5 shows an address set key check routine, in which it is checked whether the address set key 19 has been pressed in the program mode.

If key 19 is pressed, address set LED1
Turn on 8. On the other hand, address set L [DlB is ON]
L.

If key 17 is pressed while the
D Turn off 1g.

FIG. 6 shows a program address and data setting routine using the numeric keypad 24, checking the numeric keypad data store RAM.

Check whether the numeric keypad 24 is in the ON state. Numeric keypad 24
If it is in the ON state, check whether it is in program mode. If not in program mode.

Jump to the copy number setting routine. If you are in program mode, check whether you are inputting an address or data. When inputting an address, set the 4-digit address in the address display RAM.

Set the address set flag to "1"; if it is not an address input, set 2 digits of data in the data set RAM and set the data set flag to "1".

FIG. 7 shows the routine of the program write key 24. When the write key is pressed with an address set in the program mode, the data to be sent and its address are stored in the RAM to be sent to the CPU 1. Set program write status.

Set the send request flag to be sent to cpu t.

FIG. 8 shows the routine of the program recall key 22, when the address set flag is "1" in the program mode and the recall key 22 is pressed.

Set the program recall status in the RAM to be sent to CPt1l, write the address ', and set the transmission request flag to "1".

FIG. 9 shows the address and data display routine of the program, which causes the 4-digit display RAM to display addresses or magnification ratios. If you are in program mode, check whether the recall key is in the ON state and press O.
In the case of N state, recall data is displayed in the second digit. If it is OFF, the written data is displayed.

FIG. 10(a) shows the select routine of CPU2, in which CPU2 sets the reception register RXB, which is input to the interrupt routine, to "0" by the CPUI select signal.

Clear transmit/receive interrupts. Initialize the transmission RAM address counter. RA sent to C register
Set the number of bytes in M. If the flag selected by CPUI is 1, RA is output at the cycle of timer N.
Send N bytes of M. Send request flag is “0”
In this case, exit from the interrupt routine.

FIG. 10(b) shows the receiving interrupt routine of the CPU 2, which is selected by cput, and when the receiving interrupt is canceled in the select routine of FIG. 10(a) and the CPU transmits, the CPU 2 enters the receiving interrupt. Write the contents of the receive buffer to the receive RAM, then increment the receive RAM address by 1. Set the receive flag.

FIG. 10(c) shows a select check routine, in which it is checked whether the select flag set in the select routine of FIG. 10(a) is "1".

If it is "1", check port C to see if the select bit is rlJ. If it is "1", return; if it is "4", it means that the CPUI has released the selection of CPU2, so the select flag is set to rOJ.

It is checked whether the reception flag is rlJ, and if it is "1", the command reception flag is set to mask transmission/reception interrupts. If it is "0", transmission/reception interrupts are masked.

FIG. 11 shows the command processing routine of the CPU 2, in which it is checked whether the command reception flag is "1".

If it is "1", the reception RAM address is set.

When the program recall key is ON, it is checked whether the RAM contents at the address specified by the 11 register are call status. In the case of call status, recall address data is set in the recall data set RAM.

If the key is not ON or the call status is not, check the command from CP Okara, and after checking the command to process it, set the command reception flag to "0" and clear all the reception RAM.

The processing of the CPU 2 has been described above, but the processing of the CPU 1 will now be briefly described with reference to the drawings.

Figure 12 shows the routine for sending data from the CPUI to the CPU 2. It sets RAM address 1 to send to registers H and L, and sets RAM address 1 to receive to registers B and C (41.42). . A read/write timer time N is set to select the CPU 2 and generate a certain period of transmission/reception time (43).

Executes data transfer between CPU2 and CPUI within NT time (44), sets the number of bytes N to be transferred to the C register (45), cancels transmission/reception interrupts (4)
5).

The read/write timer is decremented by 1 (47), and if it is not rOJ (48), the ride request flag is set to “1”.
” (49) (set if there is data or command to be sent to CPU2 in Figure 14),
In the case of rlJ, check whether the transfer is completed (S
O).

If C=0, the transfer is completed; if the transfer is not completed, the read/write timer is incremented by 1 (51), and the CPUI transfers data to the CPU 2 every read/write timer time N (52 to 54).

)1. L+1 +1 (55) to the address of the sending RA,
When the next RAM address to be transmitted is reached, the transfer ends with C=rOJ transfer (50) and when the read/write timer reaches "0" (48), the transmission/reception interrupt is masked (57). C.P.
The selection of U2 is reset (58), the ride request flag is set to rQJ, and all RAMs to be transferred next are set to "0" (60).

FIG. 13 shows the reception interrupt routine of CPU 1, in which the reception data generated when transmitted from CP[I2 is stored in an accumulator, and the reception RAM address where the contents of the accumulator are stored in the reception RAM is incremented by 1.

When the reception of the number of bytes preset by the reception address 2N is completed, the flag received from the CPU 2 is set to "1". 6Next, the reception interrupt is masked.

Return from interrupt routine with R[ETI.

Figure 14 shows the status processing routine.
When the PU2 reception flag is "1", the program recall status that processes the status of CPU12 is "1".
”, and if it is “1”, set the RAM address to be recalled in the B and C registers.0 Next, B,
Send RAM data specified by C to RAM address 2
Set the program call status in the send RAM address 1. Set the ride request flag to "1" to send to the CPU 2.

Next 11. Add +1 to the L register to check program write status. In the case of write status, set write to the n and C registers, read the write data into accumulator 800, and write accumulator ACC to the RAM address specified by the B and C registers.

H register +1, check the status of the next RAM address, and when the check is finished, set the CPU2 reception flag to "0" and clear all the reception RAM.

Figure 15 shows the RAM map sent from the CPU 2 to the CPUI. take. Also, FIG. 16 shows the RAM map sent from cput to CPU2, where CPUI is the program call status.

Send information such as data and display information.

FIG. 17 shows a receiving processing routine with CPU 3 performed by CPU I, in which CPU i reads out the status of CPU 3 (61) and checks whether the Fl flag is "O" (62).

If it is "0", it is RET; if the CPU 3 is executing a write routine or a redundant routine, it is "1"; when the execution is finished, it is set to rOJ. Initialize OBF! (63), , :: (7) OBF is CPU
3 is a flag that is set when the DBBOUT data is set. Read the status of CPU13 (64
). It is checked whether the FO flag is "1" (65). This FO flag is a flag set by the CPLI3 in order to write data to DIlBOUT.

If it is "1" then 11. Set RAM address 1 to write the data of CPU2 to the register B (66), set the number of data to be read minus 1 to the B register (67), and set the timer to exit from the subroutine if the CPU3 does not output data for a certain period of time. is set in the C register (6
8), Read the status of CPU2 (69), 0
Check if BF=1 (70), if "rl", C
Pt13 sets data in DBBOUT and reads the data (71), at which time the OBF flag is reset. CPU3
Write the data to the RAM address specified by the H and L registers (72), ) Add 1 to the L and L registers (72)
3), -1 from the B register (74).

If a borrow occurs, it means that 4 bytes of data have been read (75); if there is no borrow, the process returns to step 68. If OBF = 0, add 1 to the C register (
76), if a carry occurs, output "0" to CPU3 and set the Fl flag to "0" (77.78)
, If no carry occurs, read the status of CPU3 (79) and check whether Fl is "0" (80).
), if Fl is "0", the write routine of CPU 3 is not being executed, so RET is performed as an abnormality. "1"
In this case, the process returns to step 69. If a borrow occurs,
Set data RAM address 1 in the H register. Read the data output from the CPU 3 from the read RAM address (82), check whether the program status bit is 1 (83), and in the case of rQJ, write the data to the RAM that stores peripheral commands (84).
), In the case of rlJ, write the contents of data read RAM 4 to the RAM address specified by data read RAM 2.3 (85), set data read RAM 1 to 4 to "0".
FIG. 17(b) shows a routine for outputting data (86), but since this process is performed in the same manner as described above, its explanation will be omitted.

The above is a description of the CPUI processing. below.

The processing of the CPU 3 will be explained.

Figure 18 shows the main routine of CPU3.
The CPU 3 starts the program from "0" after a certain period of time after the source is turned on (after the 1st completion is canceled). CPIJ3
initializes each port (91). Next, clear the internal RAM (92), set 80)1 in the data manual buffer of channel 1 (93), (set 808 in the serial receive buffer (RAM)).
80) Set 1 in the data input buffer of channel 2 (94). (Set 801 in the serial reception buffer 1 (RAM).) Initialize the buffer address counter output to the CPUI (95), set FFII in the buffer output to the boat 2 (95).
6), (Set all ports to “1”) CPt13
Set N to the timer counter inside (97)
, (The CPU3 counts the externally generated clock and generates an interrupt when the above N count is reached. The count that generates this interrupt becomes the clock for serial transmission/reception.) Starts the internal interrupt timer (98 ), read boat 1 and check whether the program switch is turned on (99).

(When DIPSWI in FIG. 1 is ONL) If it is ON, then it is checked whether the program read flag is "1" (100).

When the read flag receives the program information, the 25th read flag will be activated.
It is set according to the flow shown in the figure. For VES, set the program read flag to "0" (101), CPU1
Set the flag "O" to output to (102)
, if this flag is set to "l", data is output to the CPUI in the subroutine shown in FIG. CPU
Set the program status bit "1" to output buffer 1 (103), call the subroutine shown in FIG. 19 that outputs data to CPU1 or reads data from CPU1 (104), then process 99
Return to

In process 99, if the program switch is not ON, the reception flag is checked to see if channel 1 has received data (105), and the channel 1 data reception flag is set to "O".
” (106), and set the output request flag FO for output to CPU1 to “1” (107)
.

Set the channel 1 reception flag in output buffer 1 (20H) to output to CPIJI (108), (set BitO of address 20) 1 to "1") Output data to CPU 1 or input data from CPU t 19th
Call the subroutine shown in the figure (109), check whether the transmission request for channel 1 is "0" (110)
, In the case of rOJ, it is possible to send, so check the bit of the buffer to see if there is data to be sent from the channel (111), in the case of rlJ, set the channel l valid data flag to "0" (112), and send to channel 1. Buffer 2 read from CPUI to buffer
Write the contents of (113).

Set the transmission request flag of channel 1 to rlJ (114), check whether data of channel 2 has been received in the same way as channel l, and output the received data to the CPUI (115 to 118), do the same as channel 1. and transmits it to channel 2 (119-124).

FIG. 19 shows a routine for processing transmission and reception with the CPUI, and returns if CPU1 has not selected CPU3. CPU3 sets the F1 flag to "0" when exiting the ride read routine, and resets the flag IBF, which is set when the CPU writes data to DBBIN (buffer where the CPUI writes data) to set Fl. (132), (DBBIN
It is reset by reading 7 cumulators.
) Check whether the flag set in the main routine is "1" when you want to output data to CPtJl (13
3) In the case of "rl", there is data that you want to output to the CPUI, so set the buffer address 1 to be output to the CPUI as RO.
(134), set 4 to R2 (135)
), set the timer counter to "0" (136), CP
If the CPU UI does not read even after a certain period of time has elapsed after outputting to the UI, the subroutine is exited, so check whether the OBF flag is rlJ. (: The flag that is set when Pu2 writes data to the data output cover sofa DBBOUT is O when the main unit reads data from DBBOUT.
BF is reset (137). If OBF is "0", the CPUI is in a state where data can be read, so the DB
Writes the contents of the address specified by RO to BOUT (
138), becomes the address of output buffer 2 which increases RO by 1 (139), subtracts -l from R2 (140)
, Check whether R2 is rQJ (141), rO
In the case of J, set output buffer 1 to "0" (142),
If it is not rOJ, the process returns to step 136. FO as “0”
” (143). If OBF is "1" (when old CP does not read data), increment the timer counter by 1 (144), and check whether the timer counter = 128 (
145), if n3=128, CPU3 is considered abnormal.
The select flag F1 is set to "0" and the subroutine is exited (146). If R3=128, Fl is “
1" (147). If Fl is "1", the CPU sets the flag written in DBBIN to rOJ and performs RET (return) (148).

FIG. 20 shows the CP old data read processing routine in the CPU 3. Set the read buffer address in RO (151), check whether bit 0 and bit l of read buffer 1 are "0" (152)
゜153), if either is "1", it has not been sent yet, so set the F1 flag to "
0" and return (154). Set R2 to "3" (155). Set R3 to "0" (156).
), checks whether the flag IBF, which is set when the CPUI writes data to DIlBIN, is "1" (157
), if IBF is rQJ, set timer counter R3 to +
1 (158). If n3=128, the F1 flag is set to "0" and the process returns (159, 154).

If R3≠128, it is checked whether the F1 flag is "1" (160). If Fl is "1", the process returns to step 157. If the F1 flag is rOJ, set the IIIT flag to “
0'' and return (161), IBF is rOJ
In this case, it is checked whether CPII3 is selected (162). If not selected and F1=0, set IBF to 0 and return (163), TBF
If the flag is "1", cp old outputs data (164
) L, so write it to the DBBIN content read buffer (165) and add 1 to RQ (166).
), (becomes the next read buffer) performs R2-1 (167). As a result, if "O", read buffer 3
This means that data has been written to the byte. If it is not "0", the process returns to step 156.

FIG. 21 shows a timer interrupt processing routine in the CPU 3, in which transmission and reception processing is performed by interrupts. The interrupt occurs every 560 μsec.

Output R6 to boat 2 (171). Set the count to the timer counter (172), (560μsec
Creation counter,) Check whether the interrupt count counter is "2" (173), If r2J, set the counter to "0" (174), N.

If so, increment the counter by 1 (175) and input vote 1 to the vote buffer (176).

Thereafter, the channel 1 transmission routine begins. It is checked whether the counter is "0" (177), and if it is not rQJ, it jumps to the channel 2 transmission routine TXD2 in FIG. Channel l transmission request flag is “1”
” (178). If the flag set when data to be transmitted to channel 1 is input from the CPUI is rQJ, jump to TXD2. Check whether the start bit flag of channel 1 is “1” (1
79), R6 if the start bit flag is “0”
Mask the 0 bit of the register (180), (rO
Make it J. ) Set the channel 1 transmission bit flag to rlJ and move to TXD2 (181), check whether the channel 1 transmission bit counter is 8 (182),
If NO, add 1 to the channel 1 transmission bit counter.
(183), (Counter to check whether 8 bits have been transmitted), Channel 1 transmission buffer (2B) is placed in the accumulator (184), Shift write is performed in the accumulator including the carry (185). Put the contents of the accumulator into the channel 1 transmission buffer (2B) (186), check whether a carry has occurred (187)
), and if No, bit O of the R6 register is set to "0" (188).

If YES, set bit 0 of the R6 register to "1" (189). In the case of channel 1 transmission bit counter 8, transmission of 8 bits has been completed, so the channel 1 transmission request flag, channel 1 start bit flag,
Set the channel 1 transmission bit counter to “0” (19
0), set bit rOJ of R6 register to “1” (
191). (Stop bit set.) Move to TXD2.

FIG. 22 shows a transmission routine for channel 2, but since this routine is almost the same as the transmission routine for channel 1, a description thereof will be omitted.

FIG. 23 shows the reception routine RXDI for channel 1, in which boat 1 is input and a check is made to see if the program read switch is ON (201). If it is ON, the program jumps to the program information input flow RXD3 (FIG. 25). If it is OFF, it is checked whether the channel 1 read start bit 2 flag is "1" (202).

If it is "1", it means that the start bit has been read.

If the indication is "0", input port 1 (203), and check whether the "4" bit of port 1 is "0" (204).

(Check whether the start bit is rOJ.) If it is rlJ, there is no reception signal on channel 1, so channel 1
Set the read start bit, 1 and 2 flags, channel 1 read end flag, and channel l read counter to ``0''.
” (205), move to RXD2. boat 2
If the θ bit is "0", check whether the channel 1 read start bit 1 flag is rOJ and move to RXD2 (206). If it is rOJ, set the channel 1 read start bit 1 flag to "1" and move to RXD2. (207). In the case of rlJ, set the channel 1 read start bit 2 flag to "1" and
Move to 2 (20g). If the channel 1 read start bit 2 flag is "1", it is checked whether the channel 1 read counter 2 is present (209). (In the case of 2, it is the timing to input the received bit.) Set the channel 1 read counter to "O" (210), channel 1
Check whether the read end flag is rQJ (211)
. This flag is set when 8 bits are input. "0
”, enter boat 1 in the accumulator (2
12).

Set the carry to "0" (213), check whether the θ bit of boat 1 is "1" (214), if it is "rl", combine the carry (215), channel 1
The data person's cover sofa is shifted and written including the carry (216).

Check whether the carry is 1 (217), and if the carry is 1, set the channel 1 read end flag to "1" (
218), this means that 8 bits have been read.

If the channel 1 read counter is not 2 in process 209, add 1 to the channel 1 read counter (219).
, in process 211, the channel 1 read end flag is set to “1”.
'', 8 bits were input, so write the channel 1 data input buffer to buffer 1 that is output to CPU 1 (220), and write 80 bits to the channel 1 data input buffer.
) (221), set the channel 1 data reception flag (for 8-bit read check) to "1" (222), set the channel 1 read start bit 1.2 flag, read end flag, and read counter to "1". 0” (223).

FIG. 24 shows the reception routine RχD2 for channel 2, which is the same as the reception routine for channel 1 in FIG. 23, so its explanation will be omitted.

FIG. 25 shows a program or data information reception processing routine. Blocks that are not labeled in the figure are the same as the reception routine for channel 1 in FIG. 23, so their explanation will be omitted. In the routine, after receiving a total of 3 bytes, 2 bytes of the write destination address and 1 byte of data to be written, to write program information, the program read flag is set to "1" and transferred to the CPU 1.

The channel l data input buffer is written to the address specified by the counter that counts the address of the buffer output to the CPUI (231). When this writing is counted three times, it is initialized. Channel 1 data Set 808 on the hippopotamus sofa (232),
Since 8 bits have been read, set the channel 1 read start bit 1.2 flag, channel read end flag, and channel 1 read counter to rQJ (233).
Buffer 7 address counter output to CPUI is 23
Check if it is 8 (234), if not 238, C
Count the address of the buffer output to PUI and add 1 to the counter (235), 23) If it is 1, CP
Initialize the buffer address counter to be output to Ul and set it to 21H (236). Since 3 bytes have been input, set the program read flag to 1 to output to the CPUI (237).

In this way, the master CPU t, for example, μPD804
Connect CPU3 that uses 1A to the bus, and
All 2 selected by dip switch ORPSW in 3
Heavy 2 channel Nerno connector RXD I, II, TX
Connect DI and II.

By connecting to an external computer, information such as programs and data can be easily loaded into memory in a short time, and the copying machine can be operated in any mode requested by the user with a small memory capacity. become.

[Effects] As described above, according to the present invention, it is possible to obtain a programmable copying apparatus that can easily obtain the functions required by each user with a small memory capacity.

[Brief explanation of drawings]

FIG. 1 is a control block diagram of a copying machine showing an embodiment of the present invention, FIG. 2 is a partial explanatory diagram of the operation panel of the copying machine, and FIGS. 3 to 11 are processing flows of the CPU 2 in FIG. 1. Figure 3 is an overall process flow diagram, Figure 4 is a flow diagram of the program key check routine, Figure 5 is a flow diagram of the address set key check routine, and Figure 6 is a flow diagram of the address and data set routine using the numeric keypad. FIG. 7 is a flow diagram of the program write key set routine, FIG. 8 is a flow diagram of the program recall key set routine, FIG. 9 is a flow diagram of the program address and data display routine, and FIG. 10 (a) 10(b) is a flowchart of the reception interrupt routine, FIG. 10(C) is a flowchart of the select check routine, FIG. 11 is a flowchart of the command processing routine, and FIG. 12 is a flowchart of the select routine. - Figure 17 is a processing flow diagram of the CPUI, Figure 12 is a flow diagram of a sending routine to the CPU 2, Figure 13 is a flow diagram of a reception interrupt routine, Figure 14 is a flow diagram of a status processing routine, and Figure 15 is a flow diagram of a status processing routine. The figure shows the CPU
FIG. 16 is a diagram of the RAM map sent from CPU 2 to CPU 2, and FIG.
Figures 7(a) and 7(b) are flow diagrams of the reception processing routine with the CPU 3, Figures 18 to 25 are processing flow diagrams of the CPU 3, Figure 18 is the flow diagram of the main routine, and Figure 19 is the flow diagram of the CPU 3. Flowchart of the transmission/reception processing routine with l, 2nd
Figure 0 is a flowchart of the CPUI data read processing routine, Figure 21 is a flowchart of the timer interrupt processing routine, and Figure 2 is a flowchart of the CPUI data read processing routine.
Figure 2 is a flow diagram of the transmission routine for channel 2.
The figure is a flow diagram of the reception routine for channel l. FIG. 24 is a flowchart of the channel 2 reception routine, and FIG. 25 is a flowchart of the program or data information processing routine. 1.2.3...CPU, 4...I/O device, 5...
・Data bus, 6...Power supply voltage monitoring circuit, 7...Battery bag backup circuit, 8...RAM, 9.10
... Driver. 11.12...Display device, 13...Buffer, 14.
...address bus, 15...decoder, 16...R
OM, 17...Operation panel, 18...Address set LED. 19... Address set key, 20... Program set LED, 21... Program key, 22...
Recall key, 23... Light key, 24...
Numeric keypad. Figure 2 Figure 3 Figure 5 Figure 9 Figure 10 (b) Figure 10 (c) Figure 11 Figure 13 Figure 15 Figure 16

Claims (1)

[Claims] A copying apparatus that controls various parts of the copying machine based on stored program information to perform a predetermined copying operation includes a writable nonvolatile memory that stores the program information, and a program necessary for the copying operation that is stored in the nonvolatile memory. A copying apparatus characterized in that it is provided with an interface means for inputting and storing data from the outside.