JPS62215874A - Logic scope - Google Patents

Abstract

PURPOSE:To enable accurate measurement by preventing the erroneous display of an intermediate voltage level incapable of judging logics 1, 0, by comparing input voltage with first and second reference voltages and displaying the same as either one of first - third states. CONSTITUTION:The wave form 11 of an input signal is inputted to the respective voltage comparators C1, C2 of a logic scope to be compared with respective reference voltages VH, VL. The reference voltage VH is set as voltage higher than the reference voltage VL and the output signals OH, OL of the comparators C1, C2 are set to wave forms 12, 13. These signals OH, OL are processed by a logic scope control part P to be displayed on a logic scope display part D as a wave form 14. At the time of signal OH=1, a high level of logic 1 is displayed and, at the time of signal OL=1, a low level of logic 0 is displayed and, at the time of signal OH=OL=0, an intermediate level of logic indefinite is displayed. By this method, the erroneous display of the intermediate level is prevented and accurate observation is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic scope for observing the logical state of digital equipment.

[Conventional technology]

Conventional logic scopes use a single voltage level to determine logical 1 and 0.

In other words, it was determined whether the signal was 1 or 0 based on whether the voltage of the signal was high or low. Since the judgment was made using two voltage levels, there were discrepancies with the judgment voltage level of the actual logic circuit element.
/< When using a floating level as in (7), the voltage may become close to the judgment level, and the logic value observed with the logic scope and the logic value passed through the actual logic circuit element may not match. [Means for solving the problem] The logic scope of the present invention has a disadvantage that accurate observation cannot be performed. The input signal is the first
A second state in which the reference voltage is lower than the second reference voltage and a third state in which the input signal is between the first and second reference voltages are displayed separately. [Example] Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart of signals in this embodiment, and FIG. 3 is an input/output voltage characteristic diagram of a logic element.

In FIG. 1, C1 and C2 are voltage comparators, P is a logic scope control section, and D is a display section. No. 16 ■ IN is the voltage comparator C1, C2, and the respective reference lumi voltages VH, Vt
, (/FL pressure VHu UL pressure Vt, L, jl) high), and the outputs OH, (JL are processed by the logic scope control section P and displayed on the display section.

In FIG. 2, when the input signal VIN has a voltage waveform 11 (voltages v, , vL are shown by broken lines), the voltage comparator C
The output signals OH and OL of 1 and 02 have waveforms 12.1 and 12.1, respectively.
It becomes 3. These outputs No. 16 OH and OL are processed by the logic scope P and displayed as waveform 14 on the display section, and the input signal VIN is 4 logic 11".

! ! Displays three states: IIO" or logic undefined. However, logic scope P has output 1g OH
, (Waveform 14 displayed on the display after receiving the JL signal)
When is 0H=1, logic 11″ (high level), Ot,=l
Logic "o" (low level).

When OH = Ot, = Q, control is performed so that the logic is undefined (intermediate level), and the input 1M number VI N t-"
This is to control the machine to display a waveform 14 that resembles the waveform 11 rather than using only t*, No".

FIG. 3(b) is a graph of a curve 17 showing the relationship between the input signal VIN of the logic element 16 and the output No. 7 VOUT shown in FIG. 3(a). As shown by curve 17, when the input signal VIN is low, the output signal vou'r becomes high level and becomes logic "1".
1 is shown. When the input signal VIN is high, the output signal '10U
T goes low and indicates logic "01".

However, when the input signal VrN is neither high nor low, as shown in curves 17' and 17'', the output signal VOUT is not determined to be either a high level or a low level, and the logic becomes undefined. If the values of the voltages VH and VL of the voltage comparators C, , C, shown in Fig. 1 are determined so that such a range of logic is indeterminate, there will be no error in the waveform on the display. The logic state of the output signal VOtTT of the logic element 16 is completely determined to be 0. For comparison, FIG. 2 shows an example of the waveform 15 of the input signal VIN displayed on the display section of a conventional logic scope. In this case, the actual output signal of the logic element to which the input signal vKN is input may be the waveform 18 shown by the broken line, and the display on the display section will not match the logic value of the actual logic element.

〔Effect of the invention〕

As described above, the present invention provides 1. This has the effect of preventing the t4-A indication at the intermediate 1 pressure level of the input signal from which the ethics "1"Io" cannot be determined.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart showing waveforms of a conventional logic scope for comparison of the signal waveforms of the embodiment shown in FIG. 1. FIGS. 83(a) and 83(b) are diagrams of a logic element and graphs showing an example of its human power/output direct pressure characteristics. C1, c2...Voltage comparator, P...Logic scope system (d1 section, D...Logic scope display section, VIN...Observation signal, VH・・・
...Logic "1" judgment minimum voltage, VL ...Logic "0" judgment moth high command pressure, OH, OL↓ Page 1, Figure 2 (ll) (b) Figure Mo3

Claims (1)

[Claims] a first state in which the input signal is higher than the first reference voltage; a second state in which the input signal is lower than the second reference voltage which is lower than the first reference voltage; and a second state in which the input signal is lower than the first reference voltage.
and a logic scope that distinguishes and displays each third state between the second reference voltage.