JPS62210537A - Device and method for search processing - Google Patents

Abstract

PURPOSE:To obtain a pertinent storage range with one search processing by obtaining a maximum address in an area where keywords smaller than or equal to a search key are stored. CONSTITUTION:Keywords '2'-'19' are stored in addresses 1-7 of a keyword array 60. If the search key is '10', procedures of tracing of a binary tree (BT) in the search processing are indicated by a solid line and a continuous line. A maximum address out of addresses where keywords smaller than the search key are stored is obtained along the continuous line, and that of addresses where keywords smaller than or equal to the search key is obtained along the broken line. The BT is traced left, right, and left along the continuous line, and '0' and '1' are allowed to correspond to left and right respectively to find that the keyword equal to the search key is stored in an address higher than address 0102=2. The BT is traced right, left, and left along the broken line, and '0' and '1' are allowed to correspond to left and right respectively to find that the keyword equal to the search key is stored address 100=4 or preceding addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a search processing method that is optimal for dedicated hardware such as database processing or file processing.

[Conventional technology]

Search processing is a basic operation in database processing or file processing. Since search processing is performed very frequently and has a relatively high processing load, it is important to speed up the search processing.

Search processing is realized by software.

Compared to those that support the processing with dedicated hardware, the efficiency of processing such as data comparison and data structure manipulation is degraded, and a general-purpose computer has no choice but to be inefficient.

Therefore, with the development of LSI technology, LSI technology has been developed at a relatively low cost.
Now that Si chips can be developed, methods have been proposed to develop hardware dedicated to search processing and speed up search processing using hardware. Tanaka et al.: Pipeline Search and Sorting Modules as Components of Data Flow Computer (Tanaka et al.
Y.

et, al,, Pipeline Searchin
g and SortingModules as
Components of a Dat,a
flowGo+mputer, I F I P
Congress 80'.

Pp, 427-432. oct, 1980, by Foster: Content Addressable Processors (F
oster, C,C,,Contant Addre
ssableParallel Processors
, Van No5trandReinhold,
1976 ) ) @ Also, regarding this, there is an earlier application by the same applicant, Japanese Patent Application No. 173310/1983.

[Problem that the invention seeks to solve]

In search processing for keyword strings, search techniques based on dichotomy have been well known. but,
The above search technique does not take into consideration the case where there is duplication in the keyword string. for example,
In set operation processing '-C,! ;t02, 7)*-
FFJ Ka,'is++=-1! When checking a partial match (so-called inclusion relationship) or checking the number of matching items in the set calculation process, it is considered that there is overlap in the keyword string. Furthermore, it is considered that join processing is often performed between overlapping key value sets. In these operations, search processing is a basic operation and is used frequently. Conventionally, search processing was executed twice to determine the storage range, or search processing was executed once and then the storage range was determined sequentially. I responded by doing this.

Therefore, an object of the present invention is to obtain the storage range in one search process. .

[Means for solving problems]

Keyword strings to be searched are arranged and stored in ascending or descending order. In the following discussion, it is assumed that the keyword strings are arranged and stored in ascending order. The keyword string is an implementation example of a memory structure in which linear addressing is performed, and for example, a special memory structure (memory bank structure) is not adopted. In order to find the storage range in one search process, address the area where the keyword string is stored using m bits, set 1 to the target bit in order from the high order of the m bits, and As a result of comparison processing between the keyword at the storage address of the specified keyword string and the search key, if the search key is larger, the target bit is set to 1.

Otherwise, set it to 0, obtain the largest address in the area that stores the keyword that satisfies the relationship that it is smaller than the search key, and set 1 to the target bits in order from the high order of the m bits. , "As a result of comparing the keyword at the storage address of the keyword string specified by the m bit with the search key, if the search key is equal to or greater than the search key, set it to O, and set it to O, and set it to O. This is a method that executes in parallel the process of obtaining the maximum address in the area that stores keywords that satisfy the following relationship.

[Effect]

In the search processing device, the process of finding the largest address in the area that stores keywords that satisfy the relationship of being less than or equal to the search key, and the process of finding the largest address in the area that stores keywords that satisfy the relationship of being less than or equal to the search key. By executing these processes in parallel, it is possible to obtain the storage range in one search process.

Also, in order to number keywords, keywords,
A simple mechanism is used to set the output flag of the comparison process between the search key and the search key by bit manipulation.

With the Solenoid, the search process can be accomplished using only two comparators, two address registers, and a bit manipulation circuit.

〔Example〕

An embodiment of the present invention will be described in detail below.

Figure 1 shows the interval search engine (hereinafter abbreviated as iS).
This is to show the configuration diagram of 6.1SE5 (written as E).
5 is most suitable for showing the features of the present invention, and will be described in detail later.

FIG. 2 shows an overview of an example of a database system to which the present invention is applied. 1 DBMS 2 manages the entire database such as alignment processing and resource management
1, and a database 22 that stores data to be processed by the database. The DBMS 21 includes a system control unit 23 that manages input and output in addition to managing and controlling the entire system, a timing analysis unit 241 that performs syntactic and semantic analysis of queries, and an optimization unit that generates appropriate internal processing procedures. 242 and a code generation logic processing execution unit 243 that generates internal code and interprets and executes the code; and buffer control that manages the database buffer 26 that stores data to be processed by the DBMS. 251 and a physical processing section 25 that executes physical processing of the database.

FIG. 3 shows a central processing unit I (hereinafter abbreviated as cpu) showing one form in which the DBMS 21 shown in FIG. 2 is realized.
30, an intelligent file control device (hereinafter abbreviated as iFC) 31, and a disk 32.
A DBMS 21 is set up to manage the . 1FC31 includes a shared buffer 34. A database 22 is stored on a disk (hereinafter abbreviated as DK) 32 .

In this form, all database processing is performed on the CPU30.
This shows that this method is different from the method used by the DBMS 21 implemented above. Namely.

Among database processing, relational algebraic operations (selection/constraints, projection, etc.) corresponding to internal processing codes generated by the code generation logic processing execution unit 243 of the DBMS 21 are performed.

Various operations such as combination) are shared among the 1Fc31. This configuration corresponds to what is called an input/output device that adds various arithmetic functions (for example, a filtering processing device), and is known as a conventional system. Its basic operation is shown below.

1) Analyze the query entered by the user with DBMS21,
Determine the calculation processing procedure.

2) Follow the steps to cut out the relational algebra operations i Fe21
Issue a processing request to.

3) Interpret the processing request and issue a physical I/O request to the disk 32. The database 22 is a base relation, and the page that is the management unit is the disk 32.
is read in synchronization with the rotation of and set in the shared buffer 34.

4) Selection/constraints on the data in the shared buffer 34;
Performs operations such as projection and combination, and performs filtering processing.

5) Set the processing result in the database buffer 26 of the DBMS 21.

6) The DBMS 21 processes the processing results and outputs the adjustment results to the user.

Of the above processes, 3), 4), and 5) are executed in an overlapping manner (so-called on-the-fly processing).

Methods for performing this and non-overlapping operations are well known in the art.

FIG. 4 shows a hardware configuration for realizing the present invention. Specifically, the CPU 30 holds a main memory (hereinafter abbreviated as MM) 44, the channel device (hereinafter abbreviated as CHu) 41 that performs input/output control, and the database processing includes selection/constraint, projection, Local memory (hereinafter abbreviated as LM) for setting data to be subjected to join operations
Consider a system consisting of an iFe 21 that holds a disk (hereinafter abbreviated as DK) 45 and a disk (hereinafter abbreviated as DK) 32. The relative block address and input/output data are transferred between the 1Fc31 and the DK32, and the path 49 is used. Filtering processing results and the like are transferred between the CHu 41 and the 1Fc 31, and the path 48 is used. Further, the path 47 is used for data transfer and control information exchange between the CPU 30 and the eHu 41. Sutra p1
47 and 48, a plurality of individual CHus and iFCs may be combined. For example, a configuration in which CHus and iFCs are integrated, or a modified system configuration does not lose generality. In the following, cpu, cHu, iFC
We will discuss a system in which DK and DK each consist of one unit.

FIG. 5 is for specifically showing the block configuration of 1Fc31. 1FC31 is route 4 with CHu41
8 through the DK32 pathway.

49. 1FC31 includes a projection processor (hereinafter abbreviated as PRP) 50 and CHu41.
A channel processor (hereinafter abbreviated as CHP) 51 that shares the interface with the 1Fc31, an LM52 that stores data to be processed by the 1Fc31, and a file control processor (hereinafter abbreviated as FCP) that shares the interface with the DK32. ) 53, 1 selection/control processor (hereinafter abbreviated as R8P) 54, an interval search engine (hereinafter abbreviated as isE) 55 which performs the join operation, and 1SE55's search target, ie, sorted keywords. Surge buffer (hereinafter abbreviated as SB) to store
and? <)56. Path 570 is CHP51.
PRP50. and FCP 53, and is a transfer route for data that is not subject to filtering processing. route 571
is PRP50. CHP51. LM52. FCP53°R5P54. and 1SE55, and is a transfer route for data to be subjected to filtering processing.

Next, details of the iSE that performs the join operation will be described.

iSE performs search processing at high speed, and keywords, which are data to be searched, are arranged in ascending order or descending order. Here, it is assumed that they are arranged in ascending order. Search processing means storing keywords in advance, performing comparison processing between the keywords and the search key, and finding a range of keyword storage addresses that match the search key.

FIG. 6 is for showing the search processing process. The keyword string 60 is stored in ascending order as shown in FIG. 6(a). In this example, the keywords are from address 1 to 7.
Up to the address, 2, 6, 10°, 10.11, 15.19 are stored. The search processing process will be explained below using FIG. 6(b).

The address where the keyword is stored is shown in parentheses, and (a
) and (b). The search method shown here is basically a dichotomy method. Therefore.

The best way to describe the search process is to use the term BT (hereinafter abbreviated as BT). In this example, the depth of the BT, the so-called level, is 3. Therefore, the number of search processing times is three. In addition, 6.15. 2.10 and 11.19 are stored in the third level.

Specifically, starting from the root node of BT, that is, the first rubel in FIG. 6(b), which shows the search process of iSH,
Proceed toward the leaf nodes and find the range of addresses that have the same keyword as the search key. Figure 6 (b
) is B in the search process when the search key is IO.
The procedure for tracing T is shown by solid and broken lines. The solid line shows the process of finding the largest address with a keyword that satisfies the relationship of being less than the search key, and the dashed line shows the process of finding the largest address that has a keyword that satisfies the relationship of being less than or equal to the search key. The process of finding the largest address with . In the solid line, as a result of the comparison process between the keyword 1o of the th label and the search key 10, it is the same as the search key, so the left side of BT is traced. next,
As a result of the comparison process between the second level keyword 6 and the search key 1o, the search key is larger, so the right side of BT is followed. Finally, as a result of the comparison process between the third level keyword 10 and the search key 10, since they are equal to the search key, the left side of BT is followed. As a result, by tracing BT left, right, left, and associating C9 with the left and 1 with the right, 0102
(=2) It can be seen that a keyword equal to the search key is stored at an address higher than the address. This address is called the left boundary.

Similarly, on the broken line, as a result of the comparison process between the keyword IO of the th level and the search key 10, it is equal to the search key, so the right side of BT is traced. next.

As a result of the comparison process between the second level keyword 15 and the search key 10, it is larger than the search key.

Follow the left side of BT. Finally, the third level keyword 1
1 and search key 10.

Since it is larger than the search key, follow the left side of BT.

As a result, BT is traced right, left, and left, and 0. By associating 1 to the right, it can be seen that keywords equal to the search key are stored up to address 1002 (=4). This address is called the right boundary.

The left boundary satisfies the property that it is less than or equal to the right boundary,
Although this search processing process has been shown for three-level BTs, it can be implemented similarly for n-level BTs.

According to the above search processing process, for example, 2-way combination T1 and T2 (however, T1.T2 and ration)
Regarding this, if we consider the result of extracting the combined column of T1 and sorting it in ascending order (however, duplication of key values is allowed) as the keyword string, and the result of sequentially cutting out the combined column of T2 as the search key.

Using the keyword storage address range that matches the search key, θ combination (θ= (=, hq, ≧, 〉).

≦, 〈)) can be realized (where Ma is an operator indicating a join operation, and if the join columns of relations T and T2 are cl and C2, respectively,
It represents a pair that satisfies 1θT, , C2. ) FIG. 7 is a flowchart of the process for determining the left boundary and right boundary. Figure 7(a) shows
FIG. 7(b) shows the entire left boundary determination 700, and FIG. 7(b) shows the entire right boundary determination 710. First, the notation used in flowcharts will be described. The search key is SK, the left boundary is LB, the right boundary is RB, and the number of bits making up LB and RB is n.

LB and RBJ are the 1st pJth bit from the higher order of LB and RB (however, 0≦ltJ≦n-1), C
Let (LB) and C(RB) be the contents of the keywords stored at addresses LB and R8, respectively. Left boundary determination 70
0 initializes i and LB with 0 and sets the first bit of LB to 1 (701→702). Compare the content of the keyword addressed by LB with SK703), S
If K is larger, the first bit of LB is set to 1 (704); otherwise, the i-th bit of LB is set to O (705). Then increment i by 1 to 7
06), compare i and n 707), and if n is smaller than i, go to 702, otherwise output LB and end (708→709). In addition, the right boundary determination 710 includes j
and RB is initialized to 0, and the j-th bit of -RB is set to 1 (711→712). Compare the contents of the keyword addressed by RB with SK (713), and if SK is equal or greater, set the j-th bit of RB to 1 (714), otherwise set the j-th bit of RB The #th bit is set to 0 (715).

Next, increment j by 1 716), compare j and n 717), if n is smaller than j, go to 712, otherwise output RB and end (718 → 719), The left boundary determination 700 and the right boundary determination 710 in the above search process can operate in parallel, and the actual fQ
i SE performs search processing in parallel.

Next, the configuration of 1SE55 will be described in detail.

1SE55, via R3P54 and route 58,
52 etc. and route 571, and 5B56 and route 59
are connected via. Route 58 is.

It is used to transfer the search key extracted from R3P54 and the range of addresses in which keywords equal to the search key are stored. The path 571 is used for data transfer to set keyword strings sorted in ascending order in advance in 5B56 before search processing. A search key buffer (hereinafter abbreviated as SKB and 8<) 10 latches the search key, and a left boundary output register (hereinafter abbreviated as LBOR) 110 and a right boundary output register (hereinafter abbreviated as RBOR). 111 indicates the range of addresses where keywords equivalent to the search key are stored in RSP54.
In order to output to the left boundary address register (abbreviated as LBAR below) 120 and right boundary address register (
Hereinafter, RBAR and 1J() 121 are for specifying the address of the keyword to be compared with the search key based on the search process, and the left boundary data register (hereinafter abbreviated as LBDR) 130 and the right Boundary data register (hereinafter abbreviated as RBDR) 131 is LB
It is used to hold data to be input/output to the addresses on the 5B56 specified by the AR120 and RBAR, and is used for the left arithmetic processing unit (hereinafter abbreviated as LALu) and the right arithmetic processing unit (hereinafter abbreviated as RALu). The decoder (hereinafter abbreviated as DEC) 150 is for comparing search keys and keywords.
interprets the control information specified from the RSP54 and
This is for setting the function codes of Lu 140 and RALu 141.

Next, a comprehensive explanation will be given using a specific example. As an example, the keyword string 60 shown in FIG. 6(a) is 5B5
6, and only 10 is extracted from the R3P54 as a search key.The explanation will be given with reference to FIG. 1, FIG. 6(a), and FIG. 7. However, the left boundary and the right boundary are determined in parallel, and the comparison process between the keyword and the search key is synchronized.

Step 0: As an initial state, the keyword string (2゜6.10,1
0, 11, 15.19) are set. Further, the number of times n of comparison between a keyword and a search key is 3 (where Q is 2°-1 and Q≦2°, where Q is the number of stored keywords).

The RSP 54 instructs the DEc 150 via a path 58 to start the search process. The DEC 150 interprets it and sends it to LALu 140 and RALu 1 via path 16.
Set the function code to 41. Also.

From R3P54 via route 58, search key 10 is
Set to KBLO. Next, LBAR120 and RB
ARI 21 is set to O (701 and 711).

It is assumed that i in the left boundary determination 700 and j in the right boundary determination 710 can be determined in increments of 9 by LALu 140 and RALu 141, respectively. Here, self information is indicated as 1+J.

In this step, l+J is 0.

Step 1: Set 1 to the 0th bit of LBAR120 (LBA
R=100□ (=4) address) (702). S.K.
Enter the search key 10 into the LALu 140 from BlO. LBARI 20 (=4th address) from 5B56
Read the contents 10 of LBDR130 to LBDR130
Input keyword 10 from LALu1408.

LALu 140 performs comparison processing (703), and since the search key and keyword are the same, flag O is LALu 140.
is set (LBAR=0002 (=O) address) to the 0th bit of LBAR 120 via path 190 (7
05), t is incremented (i=1), and since it is smaller than 3 (706→707), 1ti- is set to the 0th bit of RBARI 21 (RBAR=100□(=
4) Address) (712). Input SKB 10 and research key 10 to RALu 141.

Contents of RBARI21 (=address 4) from 5B56
Read O to RBDRI 31 and input keyword 10 from RBDRI 31 to RALu 141.

7 L 3) When RALu141 performs comparison processing, the search key and keyword are the same, so flag 1 is RALuL
41 to the 0th bit of RBARI 21 via path 191 (RBAR=1002 (=4) address) (714). Since j is incremented (j=1) and is less than 3 (716→717), go to 712.

Step 2: Set the first bit of LBAR120 to 1 (LBAR=0
10□ (=2) address) (702). Input search key 10 to LALu 140 from 5KBIO. 5B5
LB content 6 of Lf3AR12'O (=address 2) from 6
Read to DR130. Keyword 6 from LBDR130
is input to LALu140. LALu 140 performs comparison processing (703), and since the search key is greater than the keyword, flag 1 is set to the first bit of LBAR 120 from LALu 140 via path 190 (LBAR = 0).
102 (=2) address) (704), i is incremented (i=2), and since it is smaller than 3 (706→707
), set the first bit of RBARI21 to 1 (RBAR, = 11011 (=6) address) to 702 (7
12), RALu14 search key 10 from 5KBIO
Enter 1. RBARI21 from 5B56 (=6
Read the contents 15 of address) to RBDR131, RBDR
Input keyword 15 from I 31 to RALu 141.

When RALu141 performs comparison processing (713), the search key is smaller than the keyword, so flag 0 is RALu14
1 to the first bit of RBARI21 via path 191 (RBAR=100□ (=address 4))
15), j is incremented (j=2) and is less than 3 (716→717), so go to 712.

Step 3: Set 1 to the second bit of LBAR120 (LBAR=
0112 (=3) address) <702), 5KBIO
Yo'J? - input the key 10 into the LALu l 40; 5B56 Contents of LBAR120 (=address 3) lO
is read into the LBDR 130, and the keyword 10 is input from the LBDR 130 to the LALu 140.

LALu 140 performs comparison processing (703), and since the search key and keyword are the same, flag O is LALu 140.
The second bit of LBAR 120 is set (LBAR=010□ (=2) address) via path 190 from
705). Since i is incremented (i=3) and is equal to 3 (
706 → 707), set 1 in the second bit of RBAR to 708 (address 5) in RBAR=101□) (
712), RALu1 search key 10 from 5KBIO
41. RBARI21 from 5B56 (=
Read the contents 11 of address 5) to RBDRI 31, RB
Keyword 11 is input from DRI 31 to RALu 141.

When RALu141 performs comparison processing (713), the search key is smaller than the keyword, so flag O is set to RALu14.
1 to the second bit of RBARI 21 via path 191 (RBAR=lOO□(=4)#r) (715), j is incremented (j=3), and since it is equal to 3, →717), go to 718.

Step 4: Change the contents of LBARI 120 and RBARI 21 to each LBORI 10. Transfer to RBORI 11. R.S.
L, which is an address range of 5856 in which a keyword equal to the search key is stored, is sent to P54 via route 58.
Transfer the contents of BORI 10 and RBORlll.

The search process is completed according to the above steps.

The present invention is applicable to search processing, which is a basic operation in set operation processing and join processing. It is also possible to incorporate this search processing device into a dedicated processor and realize it with a plurality of processors.

Although the present invention has been described above using a dedicated hardware device, it goes without saying that the present invention can also be realized using software means with the same idea.

〔Effect of the invention〕

According to the present invention, since it is possible to obtain the storage range of the keyword string that is equal to the search key in one search process, the search process, which is the basic operation for realizing the set operation process and the join process, is possible. It is possible to achieve faster speeds.

In addition, the search processing device has a search buffer that stores the search key length of 8 by 1-2 and the keyword string of 4 bytes.
Assuming that a word (l word is 8 bytes) configuration is adopted for the data, m=12. Then, if the search processing device is made into an LSi, it can be realized in about 3 gates. The search processing device can be realized with a configuration of four 64Lb RAMs and one gate chip per about 300 liters, and is also fully achievable with the current LSi technology.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an interval search engine according to the present invention, FIG. 2 is a block diagram showing an example of a database system to which the present invention is applied, and FIG. 3 is a block diagram showing an example of a database management system according to the present invention. FIG. 4 is a block diagram showing a hardware configuration of the present invention, FIG. 5 is a block diagram of an intelligent file control device according to the present invention, and FIG. 6 is a block diagram showing a configuration of the present invention. FIG. 7 is an explanatory diagram of a flowchart showing the search processing process of the present invention. 30...Central processing unit, 41...Channel control device, 31...Intelligen file control device. 32... Disk device, 52... Interval search engine, 54... Selection/constraint processor, 56...
・Search buffer. To the 7th bad 5 F4
To βP to φ 2nd figure 3n 4th sunset to 32nd country Cυ

Claims (1)

[Claims] 1. Storing a keyword string to be searched, sequentially inputting a search key to perform a search, and outputting an area range storing keywords that match the search key. If the keyword string is arranged in ascending order, the step of finding the largest address in the area that stores keywords that satisfy the relationship of being less than or equal to the search key; A search processing method comprising the step of determining the largest address in an area storing keywords that satisfy the relationship. 2. If the above keyword string is arranged in descending order, the step of finding the largest address in the area for storing keywords that satisfy the relationship of being greater than or equal to the search key, and the step of finding the largest address in the area that stores keywords that satisfy the relationship of being greater than or equal to the search key. 2. The search processing method according to claim 1, further comprising the step of determining the largest address in the storage area. 3. In a system that searches for keyword strings using a search key, the area for storing keyword strings arranged in ascending order is addressed using m bits, and comparison processing is performed sequentially from the most significant bit to the least significant bit. , set 1 to the target bit in order from the high order of the m bits, and compare the keyword at the storage address of the keyword string specified by the m bits with the search key, and as a result, the search key is larger. If so, set the target bit to 1
means to set it to 0 in other cases, means to obtain the largest address in the area storing the keyword that satisfies the relationship that it is smaller than the search key, and a means to set the address to 0 in order from the high order of the m bits. 1, and as a result of comparing the keyword at the storage address of the keyword string specified by the m bit with the search key, if the search key is equal or greater, set the target bit to 1, otherwise A search processing device comprising: means for setting the address to 0 if the search key is smaller than or equal to the search key; and means for obtaining the largest address in an area for storing keywords that satisfy the relationship of being less than or equal to the search key. 4. The area for storing the keyword string arranged in descending order is m
The m
Set 1 to the target bit in order from the high-order bit,
Means for setting the target bit to 1 if the search key is smaller as a result of a comparison process between the keyword at the storage address of the keyword string specified by the m bit and the search, and 0 otherwise. , a means for obtaining the largest address in the area storing the keyword that satisfies the relationship that it is greater than the search key, and in order from the uppermost m bits,
Set the target bit to 1, and as a result of comparing the keyword at the storage address of the keyword string specified by the m bit with the search key, if the search key is equal or smaller, set the target bit to 1. 3, characterized in that it has means for setting it to 0 otherwise, and means for obtaining the largest address in the area storing keywords that satisfy the relationship of being greater than or equal to the search key. Search processing device.