JPS62207011A - Sinusoidal wave generating circuit - Google Patents

Abstract

PURPOSE:To obtain an excellent S/N even when less bit number of adopting a digital pattern by a digital pattern formed while being modulated by a noise shaping function. CONSTITUTION:An address decoder 2 is controlled by a clock 1 having a period of 1/T and an address line 3 is selected sequentially. A data representing the digital pattern in a binary number shown in figure 1 (a) written in a ROM 4 is read sequentially from the data line 5 and converted into an analog signal by a DA converter 6. An output 7 of the DA converter 6 is given to an analog filter 8 and a sinusoidal wave is outputted at an output terminal 9. Further, T is a sampling period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a sine wave generation circuit, and particularly to a sine wave generation circuit suitable for LSI implementation.

[Conventional technology]

The first example of the configuration of a conventional sine wave generation circuit is as shown in Japanese Patent Laid-Open No. 60-65604, which divides a clock pulse sufficiently higher than the target sine wave frequency, and then divides the frequency of the clock pulse, and then divides the frequency of the clock pulse, and then divides the frequency of the clock pulse, and then divides the frequency of the clock pulse, and then divides the frequency of the clock pulse, which is then divided by a smoothing filter configured with an analog circuit. There is a way to pass. As a second example, there is a method as disclosed in Japanese Patent Laid-Open No. 19907/1983, in which a digital pattern obtained by quantizing a sine wave of interest is stored in a memory circuit such as a ROM, and is sequentially read out for DA conversion. Furthermore, similar devices of this type include
19025.

57-89307, etc., but the method is essentially the same as the above example.

However, in the method of the first example, if the frequency of the target sine wave is not an integer fraction of the frequency of the clock used in the device, the frequency of the divided signal and the frequency of the target sine wave may be different. In the meantime, an excess or deficiency in the number of pulses occurs, and harmonic and subharmonic distortion components increase. Therefore, the signal-to-noise ratio of the output waveform is worse than when using clock pulses that are an integer multiple of the desired sine wave frequency.

Therefore, in order to implement this first example, suppress harmonic components, and improve the signal-to-noise ratio, a high-order filter with a large amount of bard is required for the subsequent analog filter. be.

- In the method of example 2, the target sine wave frequency is
If the clock pulse is not an integer multiple, the number of digital patterns will increase, but if the number of ROM addresses is four times the greatest common divisor of the clock pulse frequency and the desired sine wave frequency, By preparing filters up to the number divided by the pulse frequency, the deterioration of the signal-to-noise ratio as in the first example can be reduced even if the subsequent filter is used as is.

However, since the signal-to-noise ratio characteristic of the output waveform is mainly determined by the digital pattern and the number of bits constituting the DA converter, it is necessary to increase the number of bits in order to improve the signal-to-noise ratio.

There is a problem that the amount of hardware increases.

[Problems to be Solved by the Invention] In order to implement the above-mentioned conventional technology and improve the signal-to-noise ratio, it is necessary to increase the number of bits, but this increases the amount of memory required and makes implementation difficult. There was a problem that the area increased. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to realize a sine wave generating circuit that can obtain a good signal-to-noise ratio even when using a small number of bits.

[Means for solving problems]

Therefore, in the present invention, the basic configuration of the circuit includes the second
The conventional example is used, but the digital pattern stored in the ROM is a digital pattern modulated by noise shaping.

[Effect]

That is, when quantizing a digital pattern, quantization is performed using the following method.

If the sampled input sine wave is X (Z) and the noise generated by quantization is NQ, then the digitized output y
(z) is Y (Z) ”X, (Z) +Na
...It can be expressed as (1). Here, Z represents a mathematical two-transform expression, and the relationship is Z''''1=e-J''I. However, ω is the angular frequency and T is the sampling period.

Here, for quantization noise No. (1-Z-1) and (1
−Z″″1) When applying a filter with a transfer function G (Z) of magnitude 2, the output y (z) is Y (Z)=X (Z)+Na−G (Z) −
(2) becomes (1-Z″-1) or (1-Z-”)”
has the characteristic of attenuating in the low range, so the noise component No.
The distribution of can be biased toward the high frequency side. However,
If high-frequency noise is removed by a simple analog filter at the subsequent stage after DA conversion, a sine wave with a good signal-to-noise ratio can be output.

〔Example〕

The present invention will be explained in detail below with reference to Examples.

FIG. 1 shows a quantized digital pattern (a) with improved signal-to-noise ratio according to the present invention and a conventional quantized digital pattern (b).

In the quantized digital pattern shown in FIG. 1, when the sampling period is T, the 0.75 period is 32×T seconds. That is, ' is a sine wave whose three cycles are 128XT seconds, which is quantized with a sampling cycle T.

Here, the amplitude of the sine wave is expressed as (24-1), and 1 bit is used as the polarity bit, and the quantization is performed using 5 bits in total.

The digital pattern in FIG. 1(b) has n=o, 1.・
...32 ... is obtained by rounding off Sn obtained in (3) to an integer. Conventionally, this pattern (b) has been stored in a ROM or the like.

The quantized digital pattern according to the invention of FIG. 2(a) can be obtained by the following example method.

At time nT, the real value obtained by sampling the input sine wave with period T, that is, the integer value Ynp of the Sng output in equation (3)
B is the integral of the difference between input and output.

is a function that quantizes a real value by rounding it to an integer value.
(), and each relationship is expressed as Bn=Sll-Y, -1+Bn-z
...(4)Y,=Q (B,)
...(5), calculate equations (4) and (5) up to the number of times m that n×T becomes a digital pattern that is sufficiently longer than the period of the desired sine wave and starts from zero. Calculate repeatedly and get Y m-82+ Y m-3
1+"' Y m is obtained, the quantized digital pattern shown in FIG. 1(a) is obtained.

In equation (5), the amount rounded down or rounded up due to quantization is expressed as N.

Yn=B, +N ・(6)
Then, by Z-transforming the recurrence formulas of equations (6) and (4), Yn
= Y (Z), S, = -(1-Z″″1)
−(7) is obtained.

: Here, G (Z) = (1-Z-') has the frequency vs. gain characteristic as shown in Figure 2, so if the portion where the gain is greater than OdB is suppressed by the filter in the subsequent stage, equation (1) can be obtained. and(
As is clear from comparing Equations 7), the signal-to-noise ratio is higher than that of the quantized digital pattern in Fig. 1(b).
The quantized digital pattern in a) is better.

The sample frequency is 512KHz, the sine wave output is 12KHz, and the cutoff frequency is 45KHz in the second stage.
If the following filter is used, the signal-to-noise ratio is 45 dB for the quantized digital pattern of Figure 1(a).
, 39d in the quantized digital pattern of Fig. 1(b)
It is possible to achieve an improvement of about 6 dB.

FIG. 3 shows the configuration of a sine wave generating circuit according to the present invention and the waveforms of each part.An address decoder 2 is controlled by a clock 1 having a period of -, and address lines 3 are sequentially selected. It is written in ROM4 in advance. Data representing the digital pattern in FIG. 1(a) in binary numbers is sequentially read out from the data line 5 and converted into analog data by the DA converter 6. The output of the DA converter 6 passes through an analog filter 8 and is output as a sine wave to an output terminal 9.

The case where G (Z) is (1-Z-1) has been described above, but G (Z) is not limited to (1-Z-1), and can be anything that has the characteristic of attenuating in the low range. Anything is fine.

〔Effect of the invention〕

According to the present invention, the signal-to-noise ratio is improved for the same number of bits. A sine wave generation circuit can be constructed. Also, in order to realize a sine wave generation circuit with a specified signal-to-noise ratio,
Because the number of required bits can be reduced compared to conventional methods,
It becomes possible to reduce the number of elements in the ROM and DA converter.

[Brief explanation of drawings]

FIG. 1 is a quantized digital pattern according to an embodiment of the present invention, and FIG. 2 is a frequency-gain characteristic diagram of a noise shaping function used in an embodiment of the present invention. FIG. 3(A) is a configuration diagram of an embodiment of the present invention, FIG.
B) shows the signal waveform of the main part of FIG. 3(A). 1...Clock, 2...Address recorder, 3...
・Address line, 4...ROM, 5...data line, 6...OA modification 1. Abusive speech 2. Diagram

Claims (1)

[Claims] 1. A ROM section that stores a digital pattern obtained by quantizing a sine wave, a DA converter section that sequentially reads out the digital pattern and performs DA conversion to convert it into an analog signal, and smoothes the output of the DA converter section. 1. A sine wave generation circuit comprising a low-pass filter section, wherein the digital pattern is a digital pattern created by being modulated with a noise shaping function.