JPS62204637A - Data transmission equipment for mobile body - Google Patents

Abstract

PURPOSE:To obtain a transmission circuit strong in noise immunity with simple constitution by combining a synchronizing code and a serial data of a main body data in series and sending a ring data formed through the combination of a head and tail of the serial data at each input of a clock signal. CONSTITUTION:The titled equipment consists of a reception antenna 1, a high frequency amplifier circuit 2, a detection circuit 3, a circuit inputting/storing the transmission request comprising a clock control F/F 4, a clock generator 6 generating a clock signal CL 1 in sending the data, a storage device M storing a data being the serial combination of a synchronizing character and a main body data and a write/read changeover switch 8 of the device M or the like. Then the F/F 4 is set by the transmission request, a signal 4a is supplied to a clock application control circuit 7 to open the gate of the circuit 7, the signal CL 1 is converted into a signal CL 2, and the signal is outputted to a terminal CLK of a register M1 to be used as a drive clock DK via a switch 8A. The register M1 outputs a transmission data from a serial data output terminal DO synchronously with the clock DK.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a device for transmitting proprietary data (for example, an individual identification code) from a moving individual (for example, a livestock animal, a product on a conveyor, a vehicle, etc.) without using a transmission line. Note that in the description of each figure below, the same reference numerals indicate the same or corresponding parts. Also logic or level old gh, Lo-
are simply written as H and L.

[Prior art and its problems]

As this type of transmitting device, there are conventionally considered devices that output from a shift register and devices that output data stored in other data storage elements (memories). Generally, data of about 9 decimal digits (100 million types) is required as the individual identification code (ID code) to be transmitted. Converting this into binary code is 2 g? > 1
From 2009, approximately 27 bits of data will be required. Actually, this ID code is redundantly focused. By adding additional data etc., this number of bits can be reduced to 2.
It may be considered that approximately 3 times (for example, 64 bits) should be prepared. SI/So (serial in/serial out) type shift registers are often used for data storage and output of this level (100 bits or less). The reason for this is: ■ The method of extracting data by specifying the address of RAM etc. is more complex to control than the shift register method, and the amount of data is too small for RAM to store this amount of data. Bit efficiency is poor and it is not suitable in terms of price and shape. ■There is also a PI/So (parallel in, serial out) type shift register, but the parallel data input terminal requires human power signal bone (64 bits), while the register has a maximum of 8 human power in one package (16 pin CMO3). Therefore, in order to realize the above 64 bits, it is necessary to connect as many as 8 in series, and as in (2), it is not suitable for this purpose from the viewpoint of cost and space. In addition to these reasons, the Sl/So shift register is
Even with S logic elements, shift registers of about 64 bits x 2 are used because they are inexpensive and easily available, and can be controlled simply by inputting a clock signal, making them easy to use. FIG. 4 shows the main part configuration of this type of transmitting device using the Sl/So shift register M1, and FIG. 5 shows the main part configuration. The timing of the operation of the main parts in Fig. 4 is shown respectively. Furthermore, the fifth
Figure (B) is a partially enlarged view of Figure (A). In FIG. 4, once the Sl/So shift register M1 outputs stored data, it is a problem if the data is pushed out and disappears, so the data output terminal Do of this shift register M1 is connected to the data input terminal of the shift register. A method is used in which the data is output while being connected to the terminal DI while circulating the data. Next, the operation shown in FIG. 4 will be briefly described with reference to FIG. When this data transmitting device (also called a tag) receives a transmission request signal via means not shown, it turns on the power of a clock generator not shown, starts its oscillation, and outputs a clock signal CL.
I is output, and a clock control flip-flop (also abbreviated as F/F) 41 is set. This set F/F 41 opens the NAND gate 42 in response to the clock signal CLI, and the shift register M
The drive clock signal D is input to the clock signal input terminal CLK of No. 1.
K is applied, and register M1 outputs data from terminal Do. On the other hand, in order to determine the amount of data output from the shift register M1, the clock signal CLI is counted by a clock counter CT, and when the scheduled number of clocks is counted, the clock control F/F 41 is reset and the drive clock signal DK given to the shift register M1 is Cut off. As a result, the shift register M1 outputs all of the internal data (circulates it internally) and stores the same data again in its own memory (within the shift register system). The output timing of the transmission data signal TD outputted for transmission from the data output terminal Do in this way is shown in FIG.
A), and the data unit DU portion in the figure is the output data portion from the shift register M1. The data is transmitted by repeating the output of this data unit DU several times with a fixed pause period (one communication pause period) TP. The beginning of the DU (data output amount at this time) is determined by detecting the start bit SB (temporarily set to H level) as shown in FIG. 5, and the synchronization of data reading is ensured. However, In this data transmission method,
When the data unit DU is sent from the shift register M1, it is necessary to input the same number of clock signals CLI to the shift register system as the number of data bits (register bit length) that can be stored in the shift register M1, and this data unit DU In order to output multiple times in succession, a pause period TP is required each time a data unit is sent.
It is necessary to provide a receiver and ensure synchronization with the receiver, making the control complex and increasing the number of control components. For this reason, there is a problem in that it is difficult to downsize and reduce the cost of the transmitter.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned problems in a data transmitting device for a mobile individual, and to provide a data transmitting device that has a simple control circuit, is small in size, and has low power consumption.

[Key points of the invention]

The gist of the present invention is to provide a device provided in each moving individual that receives a transmission request and transmits data owned by the individual (hereinafter referred to as main data) without going through a transmission line, the main data and its head. (e.g. 4~
A storage means (shift register, RAM, etc.) that stores an 8-bit code (such as a synchronization character, hereinafter referred to as a synchronization code) written from the outside, a means for outputting a clock signal (a clock generator, etc.), and the synchronization The serial data of the code and the main data are combined in series, and the circular data formed by combining the head and tail parts of the serial data are sequentially output circularly each time the clock signal is input, and the circular data is used for the transmission. Based on the data output means (a shift register to which a serial data output terminal and a serial data output terminal are connected, a RAM addressed by each digit output of a clock counter, etc.) and the transmission request, the clock signal is transmitted for a predetermined number of clocks (e.g. Number of shift register bits or RAM
(4 to 8 times the overflow count value of the largest digit of the address of the clock counter addressing the clock counter) or means (such as a clock counter, a transmission timer, etc.) for continuously supplying the circular data to the circular data output means for a predetermined period of time (corresponding to the number of clocks) )
The purpose of this invention is to eliminate the circuit (function) that adjusts and controls the number of clock outputs and output timing in the conventional device, and to realize a simple data transmission circuit that is resistant to noise. At this time, the external receiving device that receives the circular transmission data is provided with a function that allows it to detect this synchronization character and receive the main data after this character.

[Embodiments of the invention]

Next, the present invention will be explained in detail based on FIGS. 1 to 3. FIGS. 1(A) to 1(D) are block diagrams showing the configuration of main parts as different embodiments of the apparatus of the present invention, respectively.
), (B) shows an example in which the aforementioned Sl/So (serial manual input/serial output) shift register M (Ml) is used as the storage device M for transmission data, and (C) shows an example in which a static RAM (also known as SRAM) is used. abbreviated) M (M
2), the same figure (D) shows the same < PI/So (parallel manual/serial output) shift register M (M3)
An example using each is shown below. Note that although the cost of the device is lowest when using the Sl/So shift register M1 as described above, the idea of the present invention is not limited to this, so embodiments using other storage devices are also possible. This is what is shown. 2 is a flowchart for explaining the operation of the main part of FIG. 1, and FIG. 3 is a block diagram showing an example of the structure of the main part of the receiving apparatus corresponding to FIG. 1. In FIGS. 1(A) to (C), 1 to 4 are circuits for inputting and storing transmission requests sent to this device from the outside, 1 is a receiving antenna, 2 is a high frequency amplification circuit, 3 is a detection circuit, 4 is a clock control flip-flop CF/F). Further, 6 is a clock generator, which is an oscillator that generates a clock signal CL1 when this device transmits data. This generator 6 may be oscillating all the time, or may be started to oscillate via means not shown prior to data transmission based on a received transmission request in order to suppress current consumption of a battery power source not shown. , the oscillation may be stopped again after data transmission. Reference numeral 7 denotes a clock application control circuit, which opens and closes the application output (clock signal CL2) of the input clock signal CLI to the storage device M side, depending on the presence or absence of the output signal 4a of the F/F 4 as a clock application control signal. do. In addition, 8 (8A, 8B) is a write/read switch (W
/R switching SW), depending on whether the input signal to the W/R switching signal input terminal 32 of this device is low or high (however, it is configured to be kept high at all times). Including (W
RI TE) mode, l1rj mode in which transmission data is written in advance to the storage device M from the outside, or one after another (READ)
Switch the internal circuit to mode, HI mode, in which this device sends data to the outside. That is, the W/R switch 5W8A cuts off the internal clock signal CL2 in the write mode and outputs the external clock signal applied to the terminal 31 as the drive clock signal DK to the storage device M side. On the other hand, in continuous mode, the external clock signal is cut off and the internal clock signal C
L2 is output as the driving clock signal DK. In the write mode, the W/R switch 5W8B (Fig. 1 (A), (B)) cuts off the input of the data signal from the serial data output terminal DO of the shift register M1, and inputs the data signal from the outside applied to the data signal input terminal 33. outputs the data signal to the serial data input terminal DI of the shift register. On the other hand, in the continuous output mode, the data signal from the outside is cut off, and the output data signal of the serial data output terminal DO of the shift register is outputted to the serial data input terminal DI. Therefore, the basic connection of the shift register M1 section in this successive mode is the same as that shown in FIG. As will be described later, TM in Figures 1 (A) and (C) is a transmission timer, CTI and C70 in Figures 1 (B) and (C) are clock counters, and Sl in Figure 1 (D) is a PI/So shift register. M3 is a load switch for instructing parallel data input, and <32 is a parallel data input switch for presetting parallel manual data as transmission data. Next, in FIG. 2, (A), (B), and (C) are drive clock signals D applied to the storage device M side, respectively.
K shows the input/output timing of the transmission data TD output from the storage device M and the valid reception data signal 22 received by the external reception device. As shown in FIG. 2(B), the transmission data signal TD has a configuration that is a planar expansion of a serial annular combination of several data units DU, and each data unit D
SC in U is a synchronization character consisting of several bits for notifying the transmission of main data ND, and ND is the main data. Further, in FIG. 3, reference numerals 17, 18, 19, and 20 are a receiving antenna, a high frequency amplification circuit, a demodulation circuit, and a synchronization signal detection circuit, respectively, which constitute a device for receiving transmission data from the data transmitting device of FIG. Next, the operation shown in FIG. 1 will be explained with reference to FIG. 2. First, referring to FIG. 1A, in a normal state, the level of the W/R switching signal input terminal 32 automatically becomes H, and the read mode is entered. In this case, the transmission request signal received from the receiving antenna 1 is sent to the high frequency amplification circuit 2.
The detection circuit 3 detects the presence or absence of a transmission request. If there is a request signal, the clock control F/F 4 is set and its output signal 4a is given to the clock application control circuit 7. As a result, the clock application control circuit 7 opens its gate, and the clock signal C generated by the clock generator 6
LI is output as a clock signal CL2 to the clock signal input terminal CLK of the shift register M1. At this time, the clock signal CL2 becomes the drive clock signal DK via the W/R switch 5W8A located between the shift register M1 and the clock application control circuit 7, and becomes the drive clock signal DK.
1 is input. Shift register M1 receiving this driving clock signal DK
outputs a transmission data signal TD from the serial data output terminal DO in synchronization with this clock signal DK. The output data signal TD is radiated into the air as a radio wave via a modulator, a high frequency amplification circuit, etc. (not shown) in the device. On the other hand, the transmission data TD is input to the serial data input terminal DI of the shift register M1 via the W/R switching SW8B. The output signal 4a of the F/F 4 is also given to the transmission timer TM to start this timer TM, and when a certain period of time (transmission period TI in FIG. 2) has elapsed, the timer TM resets the F/F 4. As a result, the supply of the clock signal CL 1 and therefore DK to the shift register M1 is cut off. In this way, one data transmission operation is completed. In this case, in order to simplify the data writing described later, the data bit length of the data unit (DU) shown in FIG. The times are chosen such that unit 1-DUs are transmitted in rotation. Next, when you want to change the data in the shift register Ml, use the following procedure to switch the W/R switches 5W8A and 8B to write mode, input the clock signal and data signal from the outside, and input the data into the shift register Ml. Write. (2) Change the W/R switching signal input terminal 32 from normal H to L. As a result, the clock signal input terminal CLK of the shift register M1 is switched to the external clock signal input terminal 31, and the serial data input terminal DI of the register M1 is switched to the external data input terminal 33 via the switches 5W8A and 8B. (2) In this state, a clock signal and a data signal are externally applied to the shift register M1 at the timing requested by the shift register M1. ■After inputting clock and data signals, W/R
The switching signal input terminal 32 is returned to L-H and data writing is completed. (2) Check whether the written data is correct by performing the read operation as described above. In order to simplify the data structure, the serial data written into the shift register M1 in this write operation is as shown in FIG.
The bit length of each data signal l-D U in B) is set as the register bit length of register M1, and synchronization character S
Data C and main data ND may be serially combined. However, it is not limited to this. By the way, FIG. 2(B) shows an example in which the synchronization character SC does not appear at the starting point of the transmission data signal TD. This is because when data is written as described above, the synchronization character SC appears at the transmission start point in the first transmission operation immediately after this writing. However, the transmission period TI (transmission timer T
If the set time of M) is not an integer multiple of the transmission time of the data unit DU, or if a bit shift occurs due to noise intrusion during the transmission operation, the transmission starting point will not necessarily be used for the second and subsequent transmission operations. It is not always possible to transmit the synchronization character SC from
). However, in the present invention, since there is no need to be aware of the starting point of data transmission, the circuit configuration can be simplified. Next, regarding Figure 1 (B), the differences from Figure 1 (A) are as follows:
In place of the transmission timer TM in FIG. 1A, a clock counter CT1 is connected to count the output clock signal CL2 of the clock application control circuit 7, but other than this, the circuit is the same as in FIG. 1A. be. The difference in function due to this change is that in FIG. 2A, the transmission period T1 is determined to be a fixed time, whereas the clock signal CL2. In other words, by counting the number of clocks for shifting register M1, a certain number of clocks (for example, each data signal)
The point is that the data output from the shift register M1 is stopped when the data bit length of the shift register M1 has been output several times (however, twice or more) the data bit length of the DU. Note that the control method shown in FIG. 1(B) can be similarly applied to the following FIG. 1(C). Next, FIG. 1(C) is an example in which an SRAMM2 is used in place of the shift register M1 of the storage devices shown in FIGS. 1(A) and 1(B). The operation from reception of a transmission request to clock control by the control circuit 7 is the same as in FIGS. 1(^) and (B). In this case, since the storage device M is a RAM, the drive clock signal DK obtained from the clock application control circuit 7 via the W/R switching 5W8A is applied to the clock counter CT2, and the output signal of each digit 20 to 2'' of the counter CT2 is is applied to the address signal input terminals A0 to A7 of RAMM2, and as the output of counter CT2 increases sequentially in binary in synchronization with the input of clock signal DK, the count of this counter CT2 in S RAMM Z increases. The data within the address specified by the numerical value is sequentially output from the data output terminal to the outside as the transmission data signal TD.Here, the bit length used by the address in counter CT2 corresponds to the bit range of the address in RAMM2. If this is done, the output from the address value "0" will be repeated again when the count value up to the maximum bit length used in the counter CT2 overflows.The count value up to this overflow is shown in Figure 2 (B ) is equal to the bit length of the data unit DU.Next, to write data to SRAMM2, set the W/R switching signal input terminal 32 to H-L.With this operation, the drive clock signal DK is input to the terminal 31. In this state, data is applied from the outside to the data signal input terminal 33 in synchronization with this clock input, and the write control signal WE applied to the terminal 34 is changed from H to L to H. By setting each bit of data to R
Can be written into AMMZ. Next, when writing is completed, the W/R switching signal input terminal 32 is returned to L-H, and normal transmission operation is resumed. Other control operations are the same as those described in FIG. In addition, FIG. 1(D) shows a PI/So shift register M that replaces the SI/So shift register M1 in FIG. 1(8) and (B).
This is an example of 3. The clock signal input terminal CLK of this shift register M3 is supplied with the drive clock signal DK as the output of the W/R switching 5W8A shown in FIGS. However, in this case, the W/R switching 5W8B, the external clock signal input terminal 31, and the data signal input terminal 33 are also unnecessary. In other words, to write data to shift register M3, write W.
After setting the /R switching signal input terminal 32 to L and setting the input data to the parallel data input terminals PDIO-PDIn of the same register M3 by a combination of ON and OFF (that is, H) of the parallel data manual switch S2, the load is performed. switch S
1 by operating 0FF-ON-OFF (H-L-H). Thereafter, by setting the level of the terminal 32 to H and applying the driving clock signal DK to the clock signal input terminal CLK of the shift register M3, the signals shown in FIGS. 1(A) and (B) are set.
A data transmission operation similar to that of the shift register M1 can be performed. The transmission data signal TD shown in FIG. 2(B) thus transmitted to the outside is received by the receiving device shown in FIG. 3. That is, the signal TD is transmitted to the antenna 17. The signal is input to the demodulation circuit 19 via the high frequency amplification circuit 18. The output signal of this demodulation circuit is further applied to a synchronization signal detection circuit 20 to detect a synchronization character SC, and based on this judgment result, a gate for the demodulation circuit output signal is opened via an AND gate 21, and as shown in FIG. ) is obtained. An effective received data signal 22 consisting only of main body data ND is obtained.

【Effect of the invention】

As is clear from the above description, according to the present invention, the structure of data transmitted from a moving object is such that each serial data of a synchronization character and main data is serially combined, and the head and tail of this serial data are The structure is such that the circular data consisting of the combination of the 2 and 3 is sequentially and sequentially output for a predetermined time or a predetermined number of bits for each clock signal, and for reception, only the main data is input after detecting this synchronization character. The data stored on the transmitting side can start from any data, which simplifies the control circuit. By simplifying the control method particularly on the data transmitting side in this way, there is an effect that a smaller and lighter data transmitting device can be realized.

[Brief explanation of drawings]

FIGS. 1(8) to (D) are block diagrams showing the configuration of main parts as different embodiments of the device of the present invention, and FIG.
A time chart explaining the operation of the main parts in the figure, Figure 3 is the first
FIG. 2 is a block diagram showing an example of a main part configuration of a receiving device corresponding to the figure. Furthermore, FIG. 4 is a block diagram showing an example of the configuration of the main parts of the conventional device and corresponds to FIG. 1, and FIG. 5 is a time chart explaining the operation of the main parts of FIG. 4 and corresponds to FIG. . -1: Receiving antenna, 2: High frequency amplification circuit, 3: Detection circuit, 4: Clock control flip-flop (F/F)
, TM: Transmission timer, CTI, C70: Clock counter, 6: Clock generator, 7: Cloth clock application control circuit, 8 (8A, 8B): Write/read changeover switch (W
/R switching SW), M: Storage device, M (ML): S
I/So shift register, M (M2): SRAM,
, M (M3): P I/SO shift register, DU
: Data unit, SC: Synchronization character, ND: Main body data, T1: Transmission time. Figure 1 (D) (A), to! ! jJ Clock A No. Koyuhi--One-time m222:22=:J and 22=Nini-22-LI[
[Concave m (C) Effective information 1 data i No. 22u animals Σ1m
f~: Junko ffiomi 1 tusk 2 figure 3 figure

Claims (1)

[Claims] 1) Provided within each moving individual, receiving a transmission request;
In a device that transmits proprietary data of the individual (hereinafter referred to as main data) without going through a transmission line, a memory that stores the main data and a code added to the head thereof (hereinafter referred to as synchronization code) written from outside. means for outputting a clock signal; and a means for outputting the clock signal by serially combining each of the serial data of the synchronization code and the main data, and further combining the head and tail parts of the serial data. a circular data output means for sequentially outputting the clock signal for a predetermined number of clocks or a predetermined time to the circular data output means based on the transmission request; What is claimed is: 1. A data transmitting device for a mobile individual, comprising: