JPS62204374A - Processing system for double arithmetic optimization - Google Patents

Abstract

PURPOSE:To improve the practical performance in terms of the compiling result by deciding the use of an addition pipeline or a multiplication pipeline in response to the using frequencies of both pipelines. CONSTITUTION:A using frequency checking part 25 checks the using frequencies of both addition and multiplication pipelines with a vector computer through recognition of the double arithmetic. Thus a using frequency counting part 26 counts previously the using frequencies of both pipelines in a so-called VL control range. A using pipeline deciding part 27 decides the use of the addition or multiplication pipeline with the double arithmetic, etc., in accordance with the checking result of the part 25. If the using frequency of the addition pipeline is low, an addition instruction generating part 28 in started. While a multiplication instruction generating part 29 is started if the using frequency of the multiplication pipeline is low respectively. Thus the using frequency is improved between both pipelines and the practical performance is improved with objects.

Description

[Detailed Description of the Invention] [Summary] Regarding the doubling operation of vector data appearing in intermediate code in automatic vectorization compilation processing or addition operation of the same vector data, depending on the usage frequency of addition pipeline and multiplication pipeline, Decide which pipeline to use and aim to improve execution performance regarding compilation results.

[Industrial application field]

The present invention relates to a processing method for compiling a program to be executed by a data processing device having a vector computer, and in particular to a processing method for optimizing double operations to generate efficient objects for double operations on vector data. be.

[Conventional technology]

For example, a FORTRAN compiler that performs automatic vectorization first expands the source program of a FORTRAN program into intermediate code, vectorizes the loops in the intermediate code, and creates addition pipelines, multiplication pipelines, etc. in a vector computer. Process large amounts of data in parallel by generating instructions that use .

Output objects that process quickly.

By the way, in programs that generally perform scientific and technical calculations, rA=B*2. Doubling operations of the form OJ often appear. In translating such statements into machine language instructions, conventional scalar computers, etc. + /Jl+ -
, '7i' 1 path is shorter than the instruction processing time by the multiplication circuit.

rA=B*2. An instruction was generated to process the multiplication form OJ in the form of addition rA=B+B, and optimization was performed using this instruction.

[Problem that the invention seeks to solve]

According to the conventional method, in a vector calculator.

Even if the addition pipeline is used frequently and the 1-multiply pipeline is used less frequently, "A=B*2.OJ
Because the compiler generates all instructions using the addition pipeline for the doubling operation of the form, an efficient object is not necessarily generated.

The present invention aims to solve the above-mentioned problems, and aims to improve execution performance regarding objects by efficiently using addition pipelines and multiplication pipelines according to the frequency of use.

[Means for solving problems]

FIG. 1 shows an example of the basic configuration of the present invention.

In FIG. 1, 11 to 13 are external storage devices such as magnetic disk devices, 14 is a source program written in the FORTRAN language TR, and 15 is a source program 1.
4 is an intermediate code converted into an internal code, 16 is an objective program consisting of machine language instructions/data, 17 is a processing device consisting of a CPU and memory, and 18 is a source program 1.
Represents a compiler that translates 4.

A source interpreter 19 in the compiler 18 receives the source program 14 from the external storage device 11.

It executes a process of interpreting a sentence and developing it into an intermediate code (text) 15. The storage allocation section 20 is
Executes the process of assigning addresses within the storage area to various data that appear in the program.

The vectorization unit 21 detects a loop structure in a program, recognizes a parallel executable portion, and changes the intermediate code of that portion into a vectorized intermediate code. The doubling operation detecting unit 22 detects a doubling operation of vector data or an addition operation of the same vector data, and performs a process of assigning a special operation code.

The intermediate code optimization unit 23 performs optimization processing at the level of the intermediate code 15 to effectively utilize the hardware of the vector computer.

In the intermediate code optimization unit 23, the double operation recognition unit 24
recognizes a doubling operation (including an addition operation of the same data, and the same applies hereinafter) in the intermediate code 15 using the special operation code set by the doubling operation detection unit 22. Usage frequency inspection section 25
The method checks the frequency of use of addition pipelines and multiplication pipelines in a vector computer by recognizing doubling operations. Therefore, the usage frequency counting section 26.

The frequency of use of the addition pipeline and the multiplication pipeline is counted in advance in a so-called VL control range.

The usage pipeline determination unit 27 determines whether to use an addition pipeline or a multiplication pipeline for doubling operations, etc., according to the inspection result by the usage frequency inspection unit 25. When the usage frequency of the addition pipeline is low, the addition instruction generation section 28 is activated, and when the usage frequency of the 1 multiplication instruction generation section 29 is low, the 1 multiplication instruction generation section 2 is activated.
9 is activated.

The addition instruction generation section 28 generates an instruction that uses an addition pipeline for a double operation, and the 1 multiplication instruction generation section 29 generates an instruction that uses a multiplication pipeline.

The register use determining unit 30 performs a process of allocating actual resources (registers) to data appearing in the intermediate code 15. The target program output unit 31 converts the intermediate code 15 into machine language.

Optimization is performed at the machine language level, and the target program 16 is output to the external storage device 13.

[Effect]

In a computer using a vector pipeline system, addition pipeline/multiplication pipeline can be executed in parallel. According to the present invention, when there is space in the addition pipeline in such a vector computer, an instruction to process the 2x operation using the addition pipeline is generated, and when there is space in the 1-multiplication pipeline, generates an instruction to process the double operation using the multiplication pipeline. Therefore, the addition pipeline/multiplication pipeline is used efficiently and the execution performance for the object is improved.

〔Example〕

FIG. 2 is an explanatory diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of execution results regarding objects generated according to the present invention.

The vectorization unit 21 shown in FIG. 1 is one example.

r Do 10 1-1.100c (1)
==D (1) +E (1)A (I) -B (1
) 12.0 10 C0NTTNUE Vectorize the loop J as follows.

r VLENG-100 C(*) -D (*) +E (*)A (*) =
B (*) *2. OJ Here, VLENG is the vector length register, and "*" in the array subscript expression is 1 to 1.
This indicates that vector data related to all arrays up to number 00 are to be processed. The vectorization control range corresponding to such a loop is called the VLti11 control range.

Like processing P1 and processing P2 shown in FIG.

The double operation detection unit 22 detects the VLIIJ? In the Il range.

rA (*) -B (*) *2. OJO type double operation or rA (*) -B (*) +B (*)
When an addition operation of the form J is detected, rA (*) −
Convert to an intermediate code of the form "B C *) #2". Here, "#" is an operator indicating that it can perform either addition or multiplication, and is a special operation code determined to be distinguishable from other operators.

In the intermediate code optimization process, the usage frequency counting unit 26 counts the usage frequency of the addition pipeline and the usage frequency of the multiplication pipeline in the VL control range, respectively, by the process P3 illustrated in FIG. 2.

The doubling operation recognition unit 24 performs intermediate code 1 by processing P4.
When the above-mentioned special operation code "#" is recognized in 5, the usage frequency checking section 25 is activated. The usage frequency inspection unit 25 obtains the usage frequency information of the addition pipeline and the multiplication pipeline through process P5 shown in FIG. 2, and compares the sizes thereof through process P6.

When the use frequency of the addition pipeline is low, the usage pipeline determination unit 27 calls the addition instruction generation unit 28,
By processing P8, rA (*) = B (*) 1 B (*)''
Select a vector addition instruction of the form. On the other hand, when the frequency of use of the 2 multiplication pipeline is low, the 1 multiplication instruction generation unit 29 is called, and by processing P9, rA (*) = B
('4') *2. Select a vector multiplication instruction of the form OJ.

For example, before and after the double operation vector instruction, add instruction Y
Assume that there is an addition instruction Z. Assuming that the execution speed of one vector operation is t, as shown in Figure 3(a), even though there is space in the 2x pipeline, the vector instruction for this 2x operation cannot be executed using the addition pipeline. and run it.

A computation time of 3t is required. In the case of the present invention, the frequency of use of the 9-multiply pipeline is low in the example shown in FIG.
An instruction is generated that uses a multiply by 1 pipeline for the double operation. Therefore, as shown in Figure 3(b),
The instruction Z that uses the addition pipeline and the instruction that performs the double operation are processed in parallel, and can be processed in an operation time of 2t.

It is possible to speed up execution.

〔Effect of the invention〕

As explained above, according to the present invention, a pipeline that is used less frequently is selectively used for the doubling operation, so that it is possible to improve the execution performance of the target program that is the translation result.

[Brief explanation of drawings]

FIG. 1 is an example of the basic configuration of the present invention, FIG. 2 is an explanatory diagram of processing in an embodiment of the present invention, and FIG. 3 is an explanatory diagram of execution results regarding objects generated according to the present invention. In the figure, 11 to 13 are external storage devices, 14 is a source program, 15 is an intermediate code, 16 is a target program, and 17
is a processing unit, and 18 is a compiler. 19 is a source interpretation section, 20 is a storage area allocation section, 21 is a vectorization section, 22 is a double operation detection section, 23 is an intermediate code optimization section, and 24 is a double operation recognition section. 25 is a usage frequency inspection section, and 26 is a usage frequency counting section. 27 is a usage pipeline determination unit, 28 is an addition instruction generation unit, 29 is a multiplication instruction generation unit, 30 is a register usage determination unit,
31 represents a target program output section. Patent applicant Hiroshi Mori (1 other person), agent patent attorney for Fujitsu Ltd. Figure 3

Claims (1)

[Claims] In a data processing system having a compile processing function that performs automatic vectorization and optimizes the vectorized target, a source program (14) is provided.
doubling operation detection means (22) for detecting a doubling operation of vector data or an addition operation of the same vector data with respect to the vectorized intermediate code in the compilation process;
a usage frequency counting means (26) for counting the usage frequency of an addition pipeline and a multiplication pipeline that process vector data in a vectorized intermediate code string; and when the above-mentioned doubling operation or the above-mentioned addition operation in the intermediate code string is recognized. , a usage frequency checking means (
25), and pipeline-to-be-used determining means (27) that determines the pipeline to be used based on the inspection result of the usage frequency and converts the intermediate code of the doubling operation or the addition operation into a vector addition instruction or a vector multiplication instruction. ) A double operation optimization processing method characterized by having