JPS62204341A - Data processor - Google Patents

Abstract

PURPOSE:To increase a processing speed of data having tags by storing these data in a register not in a RAM in case the number of arguments is small for reduction of the reference time and then storing said data in a main memory in case a number of arguments larger than the number of words that can be stored in the RAM are designated. CONSTITUTION:A data processor contains the data registers 12-15 that needs a large quantity of hardware and can have the quick reference, an internal memory part 16 that can store a comparatively large amount of data with tags with a comparatively small quantity of hardware and has the reference speed lower than that of those registers 12-15, and a main memory (corresponding to a memory part 10) that can store the largest amount of data and has the lowest reference speed as the internal registers that store the data having tags. The part 16 is used when the number of arguments described in a program is increased. Thus it is possible to operate a large amount of data with tags at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is a data processing system that can efficiently execute a program that processes tagged data, which is composed of a tag area for displaying attributes and an area for displaying the value itself. Regarding processing equipment,
In particular, the present invention relates to a data processing device that performs high-performance reference and interpretation of data expressed in tag format.

(Prior Art) An example of improving processing efficiency by introducing tagged data is prolog language processing. Let us take as an example the processing of prolog language to describe the technical environment of the present invention.

In prolog, the event to be expressed is expressed by a "predicate" consisting of a combination of a predicate name and its argument, and the relationship between the predicates is also described.For example, the event "fat people prefer numbers" is written as follows. can.

I like (2 bold characters) ← Number (real letters) In this example, "I like"
``The number J is the predicate name, the ``bold part'' and ``main character'' are the arguments, and the prison mark indicates that the argument is a variable. That is, the above example expresses ``liking'' the thing written as an argument of the predicate written with the predicate name ``fat part'' is 1 digit.'' Therefore, if the sentence ``Number (June)'' is written elsewhere, the conclusion that ``Fatbe prefers 6'' can be reached by reasoning by syllogism.

The execution of a prolog program is based on the process of comparing matches between predicates. For example, the basic process is to compare the above-mentioned "...←number (main character)." and "number (6)." to check for a match between the two predicates.Here, the former is the caller, the latter is the called party.

In this comparison processing, comparison processing between corresponding arguments of predicates is important in terms of processing efficiency, and high-speed comparison processing is required. In the example above, this corresponds to the matching comparison process between [real character 1 on the calling side and r6J on the called side. One of the comparison processing methods is H.

D. Warren [An Abstract Prologue Instruction Set] Technical Note 30
9, Artificial Intelligence Center, Nisrl.I. International, 1983
(D.

There is an argument match comparison processing method using registers described in SRI International, 1983). In this method, information about [main character] is stored once in an internal register, and later this internal register and [
6]. In this argument comparison process, "6" is bound to the variable "main character". Here, depending on how you write the prolog program, the "main character"
Instead, numbers such as rlJ, r2J, . . . "6" or other data types such as atoms and lists may be written. Add tag areas to data to identify data types such as variables, numbers, atoms, lists, etc. By examining this tag information, necessary processing can be carried out efficiently. For example, in the above example, if a variable is detected by the tag information [6]
Proceed with the merging process. Also, if there is a number instead of the "real character", it will detect that it is a tag indicating the same number as 61, and then proceed with the matching process and compare the values of the number.
Check whether they match. It is detected that rlJ and "2" are different values, and it is detected that r6J is a match. Further, when performing a minus number comparison process with another data type such as an atom or a list as "6" instead of "real character", a mismatch is detected because the respective tags are different. FIG. 2 shows an example of the matching comparison process regarding the above arguments.

(Problems to be Solved by the Invention) In the above example, the number of arguments in the predicate was 1, but a considerably larger number of arguments such as 10fM1100rM and 1ooo is allowed. For example, [number (1,
2゜3.4. ..., Jff arguments can be written like n months. At this time, in the method of the above-mentioned document, when the previous descriptor is the caller, the numbers 1, 2, 3.4..., n are stored in n internal registers, respectively, and the number of n is stored in the next caller. We need to move on to processing regarding arguments. Here, in order to realize a device that allows a large number of arguments of about 1000, the internal register can be realized by addressable random access memory (RAM).

In order to be able to process an even larger number of arguments, it is conceivable to implement more RAM in the processor, but in this case, the amount of RAM hardware in the processor will increase and the cost will increase. becomes higher.

The purpose of the present invention is to eliminate such conventional problems, and when the number of arguments is small, it is stored in a register instead of RAM, thereby shortening the reference time. The present invention provides a device that can increase the processing performance of a processing device that uses tagged data such as prologs that have a small number of cylinders.

Furthermore, the present invention provides a device that can store tagged data in main memory when more arguments than the number of words that can be stored in RAM are specified.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the data processing device provided by the present invention includes a storage section that stores data and an instruction sequence, and an instruction that stores instructions read from the storage section. register and
an instruction decoder that interprets the instructions stored in the instruction register; one or more data registers that store data to be processed; and an internal storage section that has a slower reference time than the data registers and is composed of a large number of words; a selector that decodes an operand syllable of an instruction stored in the instruction register and selects an output of data read from the data register, the internal storage section, and the storage section;
a delay control means for detecting that data specified by an operand syllable is stored in the internal storage unit or the storage unit and controlling a delay time required until the data is referenced when processing the instruction; , a memory control means that reads data from the storage section and inputs it to the selector according to the instruction; a tagged data operation section that operates the tagged data output from the selector; The present invention is characterized in that it includes a control section that controls the processing performed.

(Function) The present invention solves the problems of the prior art through the above-mentioned means.

As a program characteristic regarding the faulty arguments of a function or predicate, the frequency of occurrence is high even though the number of arguments is small, and the frequency of occurrence decreases as the number of arguments is large.

Taking advantage of this characteristic, when the number of arguments is small, the processor uses internal registers for arguments to enable high-speed processing, and when the number of arguments exceeds the RAM capacity, high-speed RAM
Although it takes longer to reference, it is stored in main memory, which can store a large number of arguments. In this way, by utilizing the program characteristics and arranging the storage locations of tagged data, which is the internal representation format of arguments, into three layers,
The effective tag analysis time for tagged data is increased to a level close to the analysis time when reading from internal registers.
Moreover, by using the main memory, it is possible to store a large amount of tagged data.

(Example) An embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the apparatus of the present invention. In the figure, 10 is a storage unit that stores tagged data and instruction sequences, 8 is an address register that holds an address for referencing the storage unit 10, and 9 is a working register that stores data read from the storage unit 10. A data register M, 11 used as an instruction register, stores instructions read from the storage unit 10, and 12.13, 14, and 15 store tagged data regarding arguments read from the storage unit 10, and realize high-speed reference. data register A
, B, C, D, 16 is an internal storage section that can store a large amount of tagged data by being configured with addressable high-speed random access memory, and has a capacity of 1024 words. , this internal storage section 16 is the instruction register 1
One word of tagged data is output by inputting as address information a field that is an operand syllable of an instruction stored in No. 1 and indicating an internal register.

Also, data register A12. B13. C14, D15
Read time is slower than . 17 analyzes the field information and stores the data register A12. B13. C14,
D15 and a selector that selects one of the outputs of the internal storage unit 16; 21 a control unit that controls the flow of processing in the data processing device under the control of a microprogram; 19 the field stored in the instruction register 11; Analyze and
If the data is referenced from the internal storage section 16 or the storage section 10, a signal for delaying the reference timing is sent to the control section 21, and the data register A12. B13. If the reference is to C14 or D15, the control unit 2 indicates that it can be referenced at high speed.
20 is a tag branch indicator that analyzes the information in the tag section output from the selector 17 and instructs the control unit 21 on the flow of processing; 22 is an instruction stored in the instruction register 11; The code is analyzed and the result is sent to the control unit 21.
An instruction decoder 23 sends the data value in the tagged data output from the selector 17 to the instruction register 11
The delay indicator 19 is a comparator that compares the value of data expressed in the instruction as an immediate value among the instructions stored in the instruction, and the delay indicator 19 is shown as an example of the delay control means. The tag branch indicator 20 and the comparison result are sent to the control unit 21. The comparator 23 is shown as an example of the tagged data manipulation unit 30, and the address register and data register 9 are shown as an example of the memory control means 31.

Next, the operation of one embodiment of the present invention will be described using one of the tagged data manipulation commands as an example. One of the proposed instructions for tagged data is an [integer comparison instruction] that performs a -number comparison process between the i-th tagged data (Ai) in the internal register and the immediate value (N) of the integer expressed within the instruction. Give an example. The format of this instruction is shown in FIG. This instruction consists of an instruction code field, an internal register field indicating the i-th internal register (A), and an integer immediate field indicating the integer immediate value (N).The internal register field consists of 16 bits (2161 ) internal registers can be specified.

The operation of this integer comparison instruction corresponds to the operation following the branch based on the argument tag of the caller in FIG. 2. This □ will be explained using the embodiment shown in FIG. This instruction is read from the storage unit 10 and stored in the instruction register 11. The instruction code field of the instruction register 11 is detected by the instruction decoder 22, and the control unit 21 starts processing the integer comparison instruction. First, the Ai register indicated by the internal register field of the instruction register 11 is referred to.

Selector 1 selects the internal register field of instruction register 11.
7, if it is detected that Ai is a value indicating the third internal register from O, the data register A12 . B13゜C14,D
15 is selected by the selector 17 and output. Also, A
When i indicates a number from 4 to 1023, the selector 17
Then, the output of the internal storage section 16 is selected. Furthermore, Ai is 1
When the number is 024 or more, the output of data register M9 is selected. Reading from the internal storage unit 16 is performed by inputting the value of the internal register field as an address, and the tagged data of the - word is read.

The tag branch indicator 20 detects the branch direction and sends it to the control section 21, and the control section 21 branches the microprogram according to the detected branch. This process is shown in FIG. 2 as a branch process based on the tag of the argument on the calling side. Here, Ai [
2], the data register C14 is selected as the output of the selector 17. Furthermore, if the data type indicated by the tag part as the contents of data register C14 is an integer and the value is "6", the tag branch indicator will move the tag of the caller's argument in the direction of the number in the microprogram. The information for branching is sent to the control unit 21. FIG. 4 shows an example of the contents of data stored in the data register C14.

Next, Ai in the internal register field is 4 or more and 1023
Indicates the following numbers. At this time, choose! 17
The output of the internal storage section 16 is selected as the output. The delay indicator 19 outputs a signal instructing a delay. FIG. 5 shows hardware for controlling delay, which exists as a part of the function of the control unit 21 in FIG. 1. 50 is a micromemory that stores a microprogram sequence; 51 is a microb that stores a microprogram read from the micromemory 50; f: a 1-gram register; 52 is a microprogram that is This is a return register that saves the contents of the galley method register 51. After completing the interrupt-related processing,
The contents of the return register 52 are returned to the microprogram register 51 in order to execute the microprogram at the time of the interrupt again. Reference numeral 53 denotes a microbranch control unit that controls branching of the microprogram, and controls the address of the microprogram at the time of interrupt and return. In addition, the signal from the delay indicator 19 indicates that the value of the internal register field of the instruction is 4 or more, and the delay end flag 54
In order to refer to the tagged data in the internal storage unit 16 or the storage unit 10 when the flag is O”, the micro branch control unit 53 performs a process of branching to a microprogram for interrupt processing.At this time, the delayed end flag is Set 54 to 1'.

When the value of the internal register field is 4 or more and 1023 or less and the delay end flag 54 is 0'', the internal storage unit 1
Refer to the tagged data stored in 6. Since a delay of one machine cycle is sufficient to refer to the data in the internal memory section 16, one machine cycle of interrupt processing is executed and processing of the original microprogram is started. This 5th to 11th processing includes:
The contents of the return register 52 are returned to the microprogram register 51.

When the value of the internal register field is 1024 or more, the tagged data stored in the storage unit 10 is referred to. The address for referencing the data in the storage unit 10 is determined by adding the value indicated in the internal register field to the base address of the storage unit 10 stored in the argument pace register 56 using an adder 57, thereby obtaining the address of the target data. is calculated and stored in the address register 8. The tagged data read from the storage unit 10 using this address is stored in the data register M9. At the end of this interrupt processing, the contents of the return register 52 are returned to the microprogram register 51, the delay end flag 54 is set to T, and the original microprogram processing is started. FIG. 6 shows the flow of processing related to these interrupt processing.

After processing these interrupts, tag branch processing is performed.

At this time, the tagged data to be branched is selected by the selector 17 according to the value of the internal register field of the instruction stored in the instruction register 11. That is, when the value of the internal register field is θ~3, data register A12. B13. The data of C14 and D15 are selected respectively, and when the value of the internal register field is 4 or more and 1023 or less, the output of the internal storage unit 16 is selected, and when the value of the internal register field is 1024 or more, the data read from the storage unit 10 is selected. The stored data in data register M9 is selected.

After finishing the branching process based on the caller's argument tag,
Check the type of the called argument. In the case of this integer comparison instruction, the control unit 21 has already detected from the instruction code that the type of the argument on the called side is a number.

As a result, the caller's arguments and the called's arguments match in data type. Next, it checks for a match, including the argument values. That is, the selector 17 as an argument on the caller side.
The value of the Ai-th data output from
The value indicated by the integer coronation field in is used as the other input of the comparator 23. Here, the output of the selector 17 is the number "6".
] in the format shown in FIG. Furthermore, even if the value of the integer immediate value is other than the number r6J, the method of advancing '■ is determined.

(Effects of the Invention) According to the present invention, a large amount of hardware is required as an internal register for storing tagged data in a data processing device, but it is relatively small with a small number of data registers that can be referenced at high speed. An internal memory that can store a relatively large amount of tagged data in hardware and has a reference speed that is slower than the data register, and a main memory that can store the most data and have the slowest reference speed (corresponding to the storage unit 10 of this embodiment). Realize it. As a result, operations on tagged data of predicates in prolog languages or functions in functional languages, which are mostly described with a small number of arguments, can be processed at high speed by using data registers. Furthermore, when the number of arguments in which a program is written increases, tagged data can be manipulated at relatively high speed by using the internal storage section. Furthermore, when the number of arguments increases, it is possible to process a large number of arguments by using the main memory. That is, taking into consideration the characteristics of the program, it is possible to effectively create high-speed tagged data. Figure 1 is a block diagram showing an embodiment of the present invention, and Figure 2 is an example of a processing procedure for creating tagged data. FIG. 3 is a diagram showing an integer comparison instruction format as an example of tag operation related instructions. FIG. 4 is a diagram showing an example of tagged data stored in an internal register. The figure is a block diagram of delay control hardware, and FIG. 6 is a diagram showing a necessary interrupt processing flow depending on the storage section in which tagged data is stored.

In the figure, 10 is a storage unit, 11 is an instruction register, 12
．． 13, 14.15 are data registers A, B, respectively.
C, D, 16 are addressable internal storage sections, 17 is a selector that selects one of the outputs of the data register and the internal storage section, and 19 is an output of the selector that is output when the internal storage section is selected. 20 is a tag branch indicator that analyzes the tag part being output from the selector to change the flow of processing and instruct the direction. , 21 is a control unit that controls the manipulation of tagged data and the processing of the present data processing device, 22 is an instruction decoder that interprets instructions in the instruction register, and 30 is a tagged unit that includes a tag branch indicator and a comparator as an example. The data manipulation section 31 is a memory control means whose configuration includes an address register and a data register M as an example.

Claims (1)

[Claims] In a data processing device in which each piece of data is expressed by a tag area indicating an attribute of the data and a value area, the storage unit stores the data and the instruction string, the instruction register stores the instruction read from the storage unit, and the an instruction decoder for interpreting instructions stored in the instruction register; one or more data registers for storing data to be processed; a selector that decodes an operand syllable of an instruction stored in an instruction register and selects an output of data read from the data register, the internal storage section, and the storage section; a delay control means for detecting that the data specified by the operand syllable is stored in the internal storage unit or the storage unit and controlling a delay time necessary until the data is referenced; a memory control unit that reads data from a storage unit and inputs it to the selector; a tagged data operation unit that operates the tagged data output from the selector; and a control unit that controls processing specified by the command. The delay control means and the memory data register determine when the control unit makes the output of the data register, the internal storage, and the storage unit a target for processing by the tagged data operation unit. A data processing device characterized by being able to manipulate data.