JPS62201086A - Pll drive control device of hall element motor - Google Patents

Abstract

PURPOSE:To obviate FG detector of a magnet, a coil etc., by a method wherein analog position detection signal of a rotor detected by a Hall element is converted into binary signal, and then inputted as feedback gain (FG) signal into PLL control circuit. CONSTITUTION:A Hall element motor has three-phase exciting coils 7a-7c, and pole number of its rotor is six. Among Hall elements 8a-8c to detect the rotational position of the rotor of the motor, analog position signal detected by one Hall element 8c is inputted to a wave shaping circuit 14 of open collector type and converted into binary signal. Output signal of the wave shaping circuit 14 is inputted as FG signal of rotational speed of the Hall element motor into PLL control circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to a PLL drive control circuit for a Hall element motor that controls the rotational speed of the Hall element motor using a PLL control circuit.

[Conventional technology] Hall element motors, which use semiconductor Hall elements to detect the rotational position of a rotor, are sometimes used as high-speed ultra-precision small motors built into loose beam printers and magnetic disk recording devices. In such a Hall element motor, when the rotor, which is made of permanent magnets, crosses near the location where the Hall element is installed, an electromotive force is generated in the Hall element due to the magnetic field, and this electromotive force is The rotational position of the rotor is detected by detecting the rotational position of the rotor.Furthermore, there is a motor drive control circuit using a PLL (phase-locked loop) sterilization circuit as a method for precisely controlling the rotational speed of the motor.

FIG. 3 shows a drive control circuit for a DC Hall element motor having a three-phase excitation coil using a PLL control circuit. In the PLL drive control circuit of this Hall element motor, the fourth
An FG multiplied signal detected by the FGG output 2 and amplified by the amplifier circuit 3 is input to the FG (feedback gain) signal input terminal ■ of the PLL control circuit 1 formed of a one-chip IC element shown in the figure. Ru. The FGG output device 3 is located close to the rotor 1 like the Hall element! It is made up of a magnet and a coil that is wound around the magnet and generates an induced voltage when the poles of the rotor cross it. Therefore, an FG with a frequency proportional to the rotation speed of the rotor
The signal is input to the FG signal input terminal of the double signal PLL control circuit 1.

In addition, between the terminals of the PLL control circuit 1, a crystal resonator 4 of a crystal oscillator that generates a reference frequency signal, which is built into the PLL control circuit 1, is connected, as shown in FIG. There is. Roughly speaking, a motor start/stop signal (S/P) is input to the input terminal O. Then, depending on the relationship between the reference signal obtained by frequency-dividing the reference frequency signal output from the crystal oscillator by the crystal reference frequency divider and the FG multiplied signal input to the input terminal (2), FIGS. 5(a) and (b) As shown in
The APC < phase system (company) signal is sent from the output terminal ■, the AFC (velocity side wJ) signal is sent from the output terminal ■,
Furthermore, RV (reverse rotation>i8q) is sent from the output terminal If the speed is low, the AFC signal goes to H level as it is in the insufficient speed range, and if it is higher than the lock range, it is considered to be overspeed and the AFC signal goes to L level.In addition, it takes an intermediate value within the lock range.The APC signal within the lock range is as follows: As shown in figure (b),
When the phase difference φ between the reference signal and the FG multiplied signal changes from O to 2π, it changes from L level to H level. Figure 6(a)
(b) is P L ill @ the above AFC in circuit 1
Signal and APC signal! ! 3 is a time chart showing a process in which a quasi-double signal and an FG-double signal are formed in stages.

P L L fltll ti11 circuit 1 output terminal■
The AFC signal outputted from the AFC signal is inputted to the base of a pnp type transistor 5 whose emitter is connected to the midpoint of a pair of voltage dividing resistors, and whose collector potential fluctuates depending on the RV multiplier signal and the APC signal. The emitter and collector of the transistor 5 are connected to control signal input terminals (2) and (0) of the motor drive circuit 6, respectively.

Each output terminal of the motor drive circuit 6 formed of a single-chip IC element is connected to each excitation coil 7a, 7b, 7 of the motor.
Hall elements Ba and Bb are connected to the input terminals ■■, ■■, and ■■, respectively.

A position detection signal from 8C is input. Each ball element 8
A voltage is applied to both ends of a, 8b, and 8c from a control voltage terminal of Vc via a resistor. As shown in FIG. 7, in this motor drive circuit 6, each excitation coil 7a, 7b is activated by the position detection signal from each Hall element 8a, sb, 8c.

The excitation phase of 7C is connected to transistors 9a, 9b, and 9c.

10a, 10b, and 10c are sequentially switched to rotate the rotor. When an H level control signal is input from the control signal input terminal @■, the differential amplifier 11 and transistor 12 cause the excitation coils 7a and 7b to rotate.
, 7c is increased to increase the rotational speed of the rotor. On the other hand, when the L level υill signal is input from the control signal input terminal ○○, each exciting coil 7a,
7b.

The excitation current flowing through 7C is reduced to reduce the rotation speed of the rotor.

Then, when the rotation speed changes and the frequency of the FG multiplied signal input to the PLLIIIt111 circuit 1 matches the frequency of the internally generated reference signal, the AFC signal output from the output terminal ■ of the PLLtlJI211 circuit 1 changes to゜L
The level becomes an intermediate value, and the value of the control signal input to the control signal input terminal ■[stock] of the motor drive circuit 6 also becomes an intermediate value, so that the rotational speed of the rotor also becomes a constant value.

Note that the control voltage of the DC Vc input to the input terminal θ of the motor drive circuit 6 is set to 10,7 by the voltage regulator 13.
The voltage is converted into a constant voltage of v, which is supplied to each component in the motor drive circuit 6 as a drive power source, and is also output from the output terminal @.

[Problems to be Solved by the Invention] However, even in the above-mentioned FG multiplied signal PLL control (PLL drive control device for a Hall cable motor in which input is made to the FGG power terminal of one circuit), the following problems occur. That is, in the drive control device 11 described above, the FGG output device 3 is a magnet.

Since it is composed of coils and the like, the detected signal is a very small signal and contains many noise components. On the other hand, in order to perform stable speed control, it is necessary to obtain an FG multiplied signal having a certain frequency or higher. Therefore, an amplifier and a noise removal circuit for amplifying the detected FG signal are separately required.

Therefore, a PC board (printed wiring board) incorporating these circuits is also required. A problem arises in which the bundling increases manufacturing costs.

The present invention has been made based on these circumstances, and its purpose is to eliminate the FG doubler signal amplifier, noise removal circuit, etc. by removing the FGG output, thereby simplifying the circuit configuration. It is an object of the present invention to provide a PLL drive control 6p device for a Hall element motor that can reduce manufacturing costs.

[Means for Solving the Problems] In the PLL drive control device E of the Hall element motor of the present invention, a waveform shaping circuit is provided to convert the rotor analog position detection signal detected by the Hall element into a 21c signal. ,
The output signal of this waveform shaping circuit is P L L III 6
0 circuit as an FG (feedback gain) signal of the rotation speed of the Hall element motor.

Further, in another invention, a frequency divider is provided that divides an index signal having one pulse per rotation of the rotor output from an index detector that detects the rotation speed of the rotor, and the frequency divider The output signal of P L L 1III 1
The rotational speed of the Hall element motor is input to the No. 11 circuit as an FG (feedback gain) signal.

[Function] With the PLL drive control &a device for the Hall element motor configured as described above, the analog position detection signal indicating the rotational position of the rotor detected by the Hall element is changed to H level or high level by the waveform shaping circuit. It is converted into an L level binary signal. Therefore, since this converted 21a signal includes a frequency proportional to the rotation speed of the rotor, this 2(a
The rotation speed of the motor can be controlled by inputting the signal FG times the rotation speed of the motor to the PLL control circuit.

In still another invention, an index signal having one pulse per revolution of the rotor is frequency-divided by a frequency divider, and this signal is multiplied by FG to generate P L L III 61
Since it is input to one circuit, the rotation speed of the motor can be controlled.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows PLL driving control 8 of the Hall element motor of the example.
FIG. 3 is a circuit diagram showing an i-position. Components that are the same as those of the conventional device shown in FIG. 3 are given the same reference numerals. Also, P L L Ill in the figure
1 circuit 1 and motor drive circuit 6 use the same IC elements as the PLL control circuit of FIG. 4 and the motor drive circuit of FIG. 7.

In this PLL drive #J control device, the Hall element motor has a three-phase excitation coil 7a as shown.

7b and 7c, and the number of rotor poles is six.

One Hall element 8C among the three Hall elements 8a, 8b, and 8c detects the rotational position of the rotor of the motor.
The analog position detection signal detected by is input to an open collector type waveform shaping circuit 14. The output terminal of this waveform shaping circuit 14 is connected to the control voltage terminal of Vc via a resistor 15 and also to the FG signal input terminal of the PLL control circuit 1.

The waveform shaping circuit 14 sets the output terminal to high impedance when the analog position detection signal input from the input terminal exceeds a certain threshold value, and makes the input position detection signal fall below this threshold value. When the output terminal is at approximately ground level. Then, adjust the resistance value of resistor 15,
When the input signal exceeds the threshold, the output signal of the waveform shaping circuit 14 is set to H level of approximately 5V, and when the input signal is below the threshold, the output signal is set to L level of approximately 0.4V. do. Therefore, if the motor is configured with 3 phases and 6 poles, when the rotor rotates once, the waveform shaping circuit 1
4 outputs 3 pulses. If the motor is rotating at, for example, 3600 rpm (>60 Hz), the FG multiplied signal frequency output from the waveform shaping circuit 14 will be 180 Hz. The rotation speed is 2500rpm
In many cases, the motor is driven at one specific rotation speed selected from among the rotation speeds from flll to 600 rpm. Therefore, in this rotational speed region, the frequency range of the FG multiplied signal output from the waveform shaping circuit 14 is 125Hz.
~300 Hz. This frequency range is P L L
1111 This is the frequency range in which the I11 circuit 1 operates sufficiently normally.

Therefore, the FGG output 2 and amplifier 3 used in the conventional device shown in FIG. 3 are not connected to the FG signal input terminal of the P L L il+' control circuit 1. In addition, the AFC (speed control t) output from the output terminal ■ of the PLL control circuit 1
iml) signal is input to the base of transistor 5 and the emitter of this transistor 5.

The control signal indicated by the voltage between the collectors of the motor drive circuit 6
is input to the control signal input terminal OO. In addition, each output terminal of the motor drive circuit 6 formed of one-chip IC element
The excitation filters 7a, 7b, and 7c of the motor are connected to the input terminals ■■.

■■ and ■[phase] have Hall elements Ba and Bb, respectively.

A position detection signal from 8C is input. Each hall element 8
A voltage is applied to both ends of a, 8b, and 8c from the 1tIIj plate voltage terminal of Vc via a resistor.

In the PLL drive control device for the Hall element motor configured as described above, when the motor rotation speed is significantly lower than the specified rotation speed, the FG multiplied signal frequency ' The AFC signal output from the P L L t11m circuit 1 becomes H level because the frequency of the AFC signal is lower than the lock range that includes the frequency of the internally generated reference signal.

Therefore, the control signal input to the input terminal @O of the motor drive circuit 6 becomes H level. As a result, the rotation speed of the motor increases as described above.

On the other hand, if the motor rotation speed is significantly lower than the specified rotation speed, P L L III m circuit 1 changes to L level AF.
A C signal is output. Therefore, the control signal input to the motor drive circuit 6 becomes L level, and the rotation speed of the motor decreases.

Then, when the motor rotation speed becomes close to the specified rotation speed, P
LL control circuits 1 to 11. An AFC signal with an intermediate value of L level is sent to the motor drive circuit 6.

The vertical movement of the rotation speed is controlled according to the intermediate value.

Then, when the rotation speed reaches a specified rotation speed, the rotation speed is controlled to be constant.

In this way, the analog position detection signal of the rotor detected by the Hall element 8c is converted into a binary signal by the waveform shaping circuit 14, and then the signal is multiplied by FG and P L L 1iI
By entering the II211 circuit 1, the rotation speed of the motor can be accurately controlled. Therefore, the FGG output device 2 in the conventional device. Since the amplifier 3.9u sound removal circuit, PC board, etc. can be removed, the circuit configuration can be simplified and the manufacturing cost of the entire device can be reduced.

FIG. 2 is a circuit diagram showing a PLL drive control device for a Hall element motor according to another embodiment of the present invention. In addition, the first
The same parts as in the illustrated embodiment are given the same reference numerals.

In this embodiment, a frequency divider 17 divides the index signal output from a Hall element 16 that detects a magnetic field generated by a magnet attached at one location on the circumference of the motor rotor. Then, the signal frequency-divided by the frequency divider 17 is converted into an FG multiplied signal and inputted to the FG signal input terminal of the PLL control circuit 1.

PLL drive of the Hall element motor configured in this way,
In the case of a tjl 1Ill device, for example, if the rotational speed of the motor is from 250 rpm to 3000 rpm, the frequency of the index signal detected by the Hall element 16 will be 42 Hz to 100 H2. The frequency range is sufficient to operate the PLLtilli11 circuit 1 with high accuracy even if the PLLtilli11 circuit 1 is

In the actual device, the frequency division ratio of frequency divider 17 and P
L L t, II 120 By adjusting the frequency division ratio of the crystal reference frequency divider that divides the oscillation frequency of the crystal oscillator in circuit 1, PLL control is activated when the motor rotation speed reaches the specified rotation speed. ) The frequency of the FG multiplied signal input to the circuit 1 is made to match the frequency of the reference signal generated within the PLL circuit 1.

Even with the PLI dynamic control design of the Hall element motor configured in this way, the FG detector 2. Since the amplifier 3, the noise removal circuit, the PC board, etc. can be removed, it is possible to obtain substantially the same effect as in the previous embodiment.

Note that the present invention is not limited to the embodiments described above. In the embodiment, the Intex detector that obtains the index signal is constructed using the Hall element 14, but a photoelectric conversion element may also be used.

[Effects of the Invention] As explained above, according to the present invention, by removing G detectors such as magnets and coils, FG doubler signal amplifiers, noise removal circuits, etc. can be removed, and the circuit configuration can be simplified. At the same time, the manufacturing cost of the entire device can be reduced.

[Brief explanation of drawings]

Figure 1 shows the P of a Hall element motor according to one embodiment of the present invention.
FIG. 2 is a circuit diagram showing a PLL drive control device for a Hall element motor according to another embodiment of the present invention, and FIG. 3 is a circuit diagram showing a PLL drive control device for a conventional Hall element motor.
A circuit diagram showing the L drive control 11\i position, Fig. 4 is a circuit diagram showing the PLL control circuit, and Fig. 5 is a circuit diagram showing the PLL control circuit.
6 is a time chart showing the operation of the PLL control circuit, and FIG. 7 is a circuit diagram showing the motor drive circuit. DESCRIPTION OF SYMBOLS 1... PLLllJtll circuit, 5... Transistor, 6... Motor drive circuit, 7a, 7b, 7c...
Excitation coil, 8a, 8b, 8c... Hall element, 14
... Waveform shaping circuit, 16... Hall element (index detector), 17... Frequency divider.

Claims (2)

[Claims] (1) In a PLL drive control device for a Hall element motor that uses a Hall element to detect the position of a rotor and controls the rotation speed of the Hall element motor using a speed control signal output from a PLL control circuit, the Hall element a waveform shaping circuit that converts the detected analog position detection signal of the rotor into a binary signal, and an output signal of this waveform shaping circuit that is converted to the PLL
FG signal input means for inputting the rotation speed of the Hall element motor as an FG (feedback gain) signal to a control circuit.
LL drive control device. (2) In a PLL drive control device for a Hall element motor that uses a Hall element to detect the position of the rotor and controls the rotation speed of the Hall element motor using a speed control signal output from a PLL control circuit, the rotation of the rotor is 1 per rotation of the rotor output from an index detector that detects the number
a frequency divider that divides the frequency of an index signal having pulses;
FG signal input means for inputting the output signal of the frequency divider to the PLL control circuit as an FG (feedback gain) signal of the rotational speed of the Hall element motor. Control device.