JPS62200423A - Signal collating device - Google Patents

Abstract

PURPOSE:To obtain a function equivalent to that of a conventional circuit, with a smaller number of hardwares, by using a first and a second signal holding means whose respective holding contents become a first and a second outputs, and a first and a second control means for responding to a variation in a second input signal. CONSTITUTION:When initial states of inputs C0, C1 are set to '1' and '0', in this case, outputs of EXCLUSIVE-OR logical elements 3, 4 are both '0', and in this state, the inputs C0, C1 are varied to '0' and '1' and become '1', and in response to it, flip-flops 1, 2 hold newly the contents which the other flip-flop has held before that time, respectively. As a result, outputs E0, E1 become '0', '1', and the outputs of the EXCLUSIVE-OR logical elements 3, 4 become both '0' again. Whenever the inputs C0, C1 are varied thereafter by the same operation, the flip-flops 1, 2 respond to a pulse applied to a CK input, respectively and hold newly the holding contents of the other flip-flop, therefore, the outputs E0, E1 always become '0', '1' or '1', '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a two-signal verification device, and particularly to a verification device suitable for use in a test circuit having self-testing properties.

[Conventional technology]

In computer systems and the like, a method is widely used in which output data from a functional circuit is encoded using an error detection code and monitored by a test circuit in order to detect a failure in a component. In this method, if a failure occurs in the test circuit itself, if it is left undetected, it may become impossible to detect a failure in the functional circuit. To prevent this, test circuits have been devised that have the ability to test the circuit itself (self-test ability) by inputs applied to the test circuit during normal operation. A test circuit with self-testing ability (hereinafter referred to as a self-testing test circuit) has a 2-bit output, and if one circuit is normal.

When the input data is normal, (Oll) or (1,
O), and if there is an error in the input data, output (0, 0
) or (1,1). In addition, if a failure occurs in the test circuit itself, or due to normal input (0,
O) or (1,1)'. This signal value assignment takes into account unidirectional multiple faults in the test circuit.

Self-testing circuits are usually combinational circuits.

Since error information appears in the output only during the period when an abnormality is being detected, it is necessary to retain the information once an error is detected in order to reliably detect the error and take appropriate action. If this retention function is achieved by adding a verification device that detects and retains a match in the output of a self-checking circuit, information indicating this will be retained even if this verification device itself fails. It is desirable to have a function, that is, a fail-safe property.

For circuits with the above functions, please refer to IE,
Transactions on Computers, VOL, C 34, No. 8 (1985), pp. 758-7.
Page 61 (IEEE Trans, Coaiput,
Vol, C-34, NO, 8 (1985) PP758
-761). The circuit shown here has a 2-bit input and a 2-bit output, and when the input is (0, 1) or (1, 0), the output is (0, 1) or (1, 0).
,1) or (1,0), and when the input becomes (0,O) or (1,1), the 2-bit output becomes (0°O) or (1,1), and this matched output is retained. Furthermore, for a unidirectional fixed fault in a combinational circuit in this circuit and a single fault in a flip-flop, the output will change to (0,0) after the input has changed by 4 degrees at the latest.
Or it becomes (1, 1), and this state is maintained thereafter.

[Is it an invention? Problems to be solved]

The above-mentioned conventional circuit has a problem in that it requires a large amount of hardware because no consideration is given to reducing the amount of hardware. In other words, the circuit of the above-mentioned prior art is used as a means to detect a failure in the system, and is a part unrelated to the original function of the system. Although it would be desirable to have a small probability of this happening, or in other words, a small amount of hardware, from the perspective of improving system availability, no consideration had been given.

An object of the present invention is to realize the same function as the above circuit using less hardware.

Means for Solving Problem c] The above object is to provide first and second signal holding means that output the respective held contents as first and second outputs, and to a first control means for setting the contents of the second signal holding means to the first signal holding means; and a first control means for setting the contents of the first signal holding means to the second signal holding means in response to a change in the second input signal. This is achieved by using two control means.

[For production]

First, the operation of detecting a match between two matching devices will be described.

It is assumed that in the initial state, the first and second signal holding means each hold the values "ljl, ItO".

Normally, the second inputs each indicate a different value, and the two inputs always change at the same time. Therefore, after the input changes for the first time, the two signal holding means mutually hold each other until the other signal holding means changes. Retain the previously retained content. Therefore, the first. The contents of the second signal holding means are respectively "Q 11 and Lt l It. Similarly, the contents of each signal holding means are inverted every time the input changes thereafter, and the two outputs always have different values. At the moment when the two input signal values match for the first time, only one of the input signals changes, so only the signal holding means controlled by the changed input signal updates the contents of the other signal holding means. As a result, the contents of the two signal holding means, namely 2
The values of the two outputs match. Once the contents of the two signal holding means match, the contents will not change no matter what input signal is applied thereafter, and the outputs will remain in the same state. In addition, if a failure occurs in a component of one of the signal holding means or control means and the contents of one signal holding means are fixed, the next time the input changes, the contents will not be fixed. Only the contents of the signal holding means are updated, and the contents of the two signal holding means match.

This state will be maintained from now on.

As is clear from the above description, the signal matching device according to the present invention normally determines whether the signal values of two inputs, each of which has a different signal value, match, rather than by directly comparing the signal values. Detection is based on the event that one of the signal values changes. The above event is
This also occurs when two signal values that normally match become different values, so generally the signal matching device according to the present invention can also be used for the purpose of detecting a mismatch between two input signal values. can be used. However, the first question is whether exactly the same device can be used for both the purpose of match detection and mismatch detection. It depends on how the second control means is implemented.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1,
2 each hold data. This is a flip-flop corresponding to the second signal holding means, and holds the input signal value at the output Q in response to the rising edge of the input CK. Further, in this flip-flop, by adding the signal value EI Ojj to the inputs S and H, respectively, the held contents can be set to '# l II , 11 Q It. However, in FIG. 1, inputs that are not used among these are not shown.

3.4 is EX corresponding to the first and second control means, respectively.
CLUS EVE-OR logic element, and 5°6 is a delay element. 7 is a reset switch for initializing the circuit.

The circuit is initialized by turning on the reset switch, and the outputs (EO, El) of flip-flops 1 and 2 become (1, 0). Input (co.

If the initial state of C1) is (1, O), then EX
The outputs of CLUSIVE-OR logic elements 3 and 4 are both “O”.
”, and in this state input (Co.

When C1) changes to (0,1), EXCLUSIVE
-The outputs 4 of the OR logic elements 3 and 4 both become "1", and in response, each of the flip-flops 1 and 2 newly stores the contents previously held by the other flip-flop. The outputs (EO, El) become (0, 1), which causes the outputs of the EXCLUS IVE-OR logic elements 3 and 4 to both become "0" again. Through a similar operation, each time the inputs (Go, CI) change thereafter, flip-flops 1 and 2 newly hold the contents held in the other flip-flop in response to the pulse applied to the GK input, so the output ( EO, El) is always (0, 1) or (1, O).

The delay elements 5 and 6 are for ensuring the setup time of the input to the rising edge of the pulse applied to the input GK of each flip-flop so that the above operation is performed reliably. It does not stipulate the Furthermore, by appropriately adjusting the delay times of these delay elements, it is possible to tolerate some variation in the timing at which the inputs CO and C1 change.

Input (Co, C1) 4:, (0, O) or (1°1)
If , only the signal value of either Go or C1 changes. Therefore, a pulse is applied to the large CK input of either one of flip-flops 1 and 2, and only that flip-flop retains the new Q value of the other flip-flop, and the output Q of the two flip-flops changes. Signal values match. Once the values of the outputs of both flip-flops match, from then on C09
No matter what input is applied to C1, its outputs, ie, the values of EO and El, remain unchanged.

The above is the operation when the circuit is normal.Next, we will explain the case where a failure occurs in the circuit itself.As is clear from the circuit configuration, only one flip-flop, for example flip-flop 1, is operated. If a fixed fault occurs, the output Q of flip-flop 1 will be transferred to flip-flop 2 the next time inputs CO and C1 change.
The value of Q is held, and the values of the outputs Q of both flip-flops match, and this state is held thereafter.

A fault corresponding to the above example is a single fixed fault in a signal line other than the reset circuit in the circuit of Figure 1 (the signal value is “
0” or 411 +7).

The operation of the circuit when a failure occurs inside the flip-flop differs depending on the internal configuration of the flip-flop. Figure 2 shows an example of the internal configuration of a flip-flop, which is made by Texas Instruments (7) TTL IC.
It is known as type 1 5N7474(7) equivalent circuit.

The circuit shown in Fig. 2 is used as the flip-flops 1 and 2 in Fig. 1, and the operation when a fault occurs inside the flip-flop will be explained.9For example, if a xi On fixed fault occurs in the output line of the AND logic gate 9 In this case, this fixes the output of the AND logic gate 12 to "1"', which is equivalent to a fault that fixes the output of the flip-flop. In addition, if a “1” fixed failure occurs in the output of the AND logic gate 13, this circuit will cause the input GK to be “1”.
0'', the output is Q+J10'', and CK is tt
At the moment when 1 u is reached, the output Q holds the value of the input at that time. Therefore, when the input D of the flip-flop that caused this failure, that is, the output Q of the other flip-flop becomes 0''.

The outputs of both flip-flops become 110'', and this state is maintained thereafter.

Regarding a single fixed fault in the input/output line of each other gate, by simulating the circuit operation when the fault occurs in the same way as above, the values of input CO and C1 will be reversed twice after the fault occurs at the latest. After that, be sure to output the output EO, E
It can be confirmed that the signal values of l match and that this state is maintained.

In addition, in the circuit of this embodiment, the first and second control means are realized using not only the first and second inputs, but also the first and second outputs, and as it is, the two inputs are Although it does not operate as a circuit that detects a mismatch in signal values, the input C
By inserting an inverting logic element into either O or C1.

It is possible to use a circuit that detects a mismatch.

〔Effect of the invention〕

According to the present invention, a verification device having fail-safe properties can be realized by a combination of a minimum unit of signal holding means and a control means such as an exclusive OR circuit. Therefore, the required amount of hardware can be reduced to 50% or less in terms of the number of gates compared to conventional circuits. Therefore, it is possible to reduce the failure rate and the number of manufacturing steps.

[Brief explanation of drawings]

FIG. 1 is a collation device for detecting coincidence of 2-bit data according to the present invention, and FIG. 2 is a connection diagram of the internal circuits of flip-flops 1 and 2 shown in FIG. 1.2...Flip-flop, 3,4...Exclusive OR element, 5,6 delay element, 7...Reset switch, 8-13...NAND logic element. Figure 1 Figure 2

Claims (1)

[Claims] (1) In a device for checking coincidence or mismatch between two signals, first and second signal holding means whose respective held contents are first and second outputs, and a change in the first input signal. a first control means for setting the contents of the second signal holding means in the first signal holding means in response to a change in the second input signal; and second control means for setting.