JPS62197995A - Memory writing and erasing device - Google Patents

Abstract

PURPOSE:To prevent an erroneous writing/erasing by performing the erasing/ writing when a coincident state with a specified code is obtained, in a data updating time. CONSTITUTION:At the time of data updating of an EEPROM, an address signal is supplied to an address bus 2, then an access is performed to a specified code storage area 6. The storage area 6 outputs the specified code information stored in advance to a comparator circuit 7. Next, the same data as the specified code is supplied to a data bus 3, and the contents of both data are compared at the comparator circuit 7, and in a state where a coincident detection is completed, a charge pump circuit 5 is set at an enable state, and a high voltage Vpp is generated, then being entered to a waiting state. After wards, the data bus 3 and the address bus 2 are set at requested values to perform the updating, and the data updating of the area 3 in the EEPROM is performed. In this way, the cases of the erroneous writing/erasing can be considerably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a memory writing/erasing device, and particularly to a memory IJ (E) that can electrically write and erase data.
The present invention relates to a device having a function of preventing erroneous erasure or erroneous writing when updating data in an EPROM.

<Prior Art> Since EEPROM allows data to be changed, it is used in electronic devices that require changes to programs, and semiconductor devices have also been developed in which a part of the memory area of a microprocessor is configured with EEFROM.

When updating the data stored in such an EEPROM, the address and data of the EEPROM are set up to desired values, the semiconductor chip is brought into write mode or erase mode, and the data is updated.

<Problems to be Solved by the Invention> However, in the above-mentioned conventional data update method in EEPROM, if the write or erase mode is set incorrectly, the given data will be updated or erased without any confirmation. A situation occurred, and the damage was particularly severe for OEEFROM, a type that erases the entire memory area at once.

<Means for Solving the Problems> The present invention provides a memory write/erase device that can eliminate the drawbacks of the conventional EEPROM data update method and prevent erroneous writing and erasing.

The present invention provides an EEPROM on the same semiconductor chip provided with an EEPROM.
A specific code for identifying the EPROM is stored in advance, and is compared with the specific code when updating data, and when a match is obtained, erasing/writing is executed.

<Operation> When updating the memory contents, simply transfer the data to EEFRO.
In addition to being applied to the data bus for Therefore, a confirmation step is required when executing an operation, and the degree of erroneous writing and erasing is significantly reduced.

<Embodiment> In FIG. 1, an EEPROM area 1 is provided within the same chip of a semiconductor chip configured as a microprocessor. The EEPROM area 1 is connected with an address bus 2 for specifying a memory area and a data bus 3 for inputting/outputting data, and also has an EEPROM area 1 connected thereto.
When M is in write or erase mode, a high voltage v of a predetermined level is applied.
A power line 4 for applying PP is connected.

The other end of the power supply line 4 is connected to a charge pump circuit 5 necessary to generate a voltage "PP" necessary for rewriting data in the memory cells of the memory area 1.

The semiconductor chip is provided with an area 6 in which a code for identifying the semiconductor chip, for example, a specific code indicating a mask name during the manufacturing process, is stored in advance, and the address signal applied to the address bus 2 is used to identify the semiconductor chip. Code storage area 6
The stored specific code is read out. The output signal of the specific code storage area 6 is applied to one input of a comparison circuit 7 provided on the same semiconductor chip. The data bus 3 is connected to the other input of the comparison circuit 7, and the output signal of the comparison result is given to the charge pump circuit 5 as an enable signal. A control signal line 8 for controlling writing and erasing is also connected to the comparison circuit 7.

In the semiconductor chip having the above configuration, EEPROM
When data is updated, the signal on the control signal line 8 at the mode switching terminal of the semiconductor chip itself is set from read mode to write mode or erase mode. In this state, an address signal is applied from the microprocessor (not shown) to the address buffer 2 to access the specific code storage area 6. The accessed storage area 6 outputs pre-stored specific code information to the comparison circuit 7.

Next, data identical to the specific code is applied to the data bus 3 by a key operation or the like, and the comparison circuit 7 compares the contents of both data. When the comparison circuit 7 detects a match, the charge pump circuit 5 is enabled, generates a high voltage vPP, and stands by. Thereafter, the data bus 3 and address bus 2 are set to desired values for updating, and the data in the EEPROM area 3 is updated.

FIG. 2 is a time chart showing the above update operation.

In the data update operation described above, if information different from the specific code is given to the data bus 3, the enable signal is not output from the comparator circuit 7, and therefore the high voltage vPP required for writing and erasing the memory cell is Therefore, even if data for updating is given to the data line 3 or the erase mode is set to the control signal 8, the EEPR
OMEPROM area 1 cannot be removed.

<Effects of the Invention> According to the present invention, when updating data in an EEPROM, the standby state for updating can be set when the specific code stored in advance and the information given to the data line match. By taking steps to check the information, the chances of erroneous entry or erasure can be significantly reduced.

[Brief explanation of drawings]

1 is a block diagram of an embodiment according to the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment. 1: EEPROM area 2: Adrenovus 3: Data storage area 5: Charge pump circuit 6: Specific code storage area 7: Comparison circuit 8: Control signal line agent Patent attorney Takeshi Sugiyama (and 1 other person) No. 1
Figure Whz Figure

Claims (1)

[Claims] 1. In the same semiconductor chip, a memory area in which data can be written and erased electrically, an area for storing a specific code, and data is input to the storage area for the specific code and the memory area. It is characterized by forming a comparison circuit connected to a bus and input with a write/erase control signal, and a charge pump circuit which is supplied with the output of the comparison circuit and outputs a write/erase signal to the memory area. Memory write/erase device.