JPS62193336U - - Google Patents

Info

Publication number
JPS62193336U
JPS62193336U JP8220186U JP8220186U JPS62193336U JP S62193336 U JPS62193336 U JP S62193336U JP 8220186 U JP8220186 U JP 8220186U JP 8220186 U JP8220186 U JP 8220186U JP S62193336 U JPS62193336 U JP S62193336U
Authority
JP
Japan
Prior art keywords
local oscillation
oscillation circuit
parallel
coil
switching means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8220186U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8220186U priority Critical patent/JPS62193336U/ja
Publication of JPS62193336U publication Critical patent/JPS62193336U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Superheterodyne Receivers (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案に係る局部発振回路の実施例
を示す回路図、第2図及び第3図は本考案に係る
局部発振回路の他の実施例を示す回路図、第4図
及び第5図は、本考案に係る局部発振回路のトラ
ツキングエラー曲線を示す図、第6図は、従来の
局部発振回路を示す回路図である。 1:アンテナ、2:高周波増幅段、3,4:ア
ンテナ同調回路、5:局部発振回路、6:半導体
集積回路、7:同調電圧発生源、8:端子、CS
〜CS:ストレー容量、D:可変容量ダイ
オード、Q〜Q:トランジスタ。
FIG. 1 is a circuit diagram showing an embodiment of the local oscillation circuit according to the present invention, FIGS. 2 and 3 are circuit diagrams showing other embodiments of the local oscillation circuit according to the present invention, and FIGS. FIG. 5 is a diagram showing a tracking error curve of the local oscillation circuit according to the present invention, and FIG. 6 is a circuit diagram showing a conventional local oscillation circuit. 1: Antenna, 2: High frequency amplification stage, 3, 4: Antenna tuning circuit, 5: Local oscillation circuit, 6: Semiconductor integrated circuit, 7: Tuning voltage source, 8: Terminal, CS
1 to CS3 : stray capacitance, D2 : variable capacitance diode, Q2 to Q4 : transistor.

Claims (1)

【実用新案登録請求の範囲】 (1) MW受信帯とLW受信帯との切換手段を具
えたAM受信機の局部発振回路に於いて、各受信
帯に対応する局部発振回路の発振用コイルとパデ
イングコンデンサと可変容量ダイオードを供用し
たことを特徴とする局部発振回路。 (2) 該局部発振回路が、発振用コイルと、該発
振用コイルに並列に接続された第1の並列容量素
子と、該第1の並列容量素子と該発振用コイルと
の接続点に接続されたパデイングコンデンサと、
該パデイングコンデンサの他端と該発振用コイル
の他端間に接続された可変容量ダイオードと、並
列容量素子を選択的に電気的に接続する切換手段
とを含み、該切換手段によつて、該局部発振回路
から異なつた局部発振周波数を得る実用新案登録
請求の範囲第1項記載の局部発振回路。 (3) 該パデイングコンデンサの他端に夫々第2
と第3の並列容量素子が接続され、前記切換手段
によつて、該第2と該第3の並列容量素子の何れ
かが電気的に接続されることにより、該局部発振
回路から異なつた局部発振周波数を得る実用新案
登録請求の範囲第2項記載の局部発振回路。 (4) 該パデイングコンデンサと該同調用コイル
との接続点に第2の並列容量素子が接続され、前
記切換手段によつて、該第2の並列容量素子の他
端を該同調用コイルの他端に電気的に接続するこ
とにより、該局部発振回路から異なつた局部発振
周波数を得る実用新案登録請求の範囲第2項記載
の局部発振回路。 (5) 該パデイングコンデンサと該可変容量ダイ
オードとの接続点に第3の並列容量素子が接続さ
れ、前記切換手段によつて、該第3の並列容量素
子を該可変容量ダイオードの他端に電気的に接続
することにより、該局部発振回路から異なつた局
部発振周波数を得る実用新案登録請求の範囲第2
項記載の局部発振回路。
[Claims for Utility Model Registration] (1) In a local oscillation circuit of an AM receiver equipped with means for switching between MW reception band and LW reception band, oscillation coils of the local oscillation circuit corresponding to each reception band and A local oscillation circuit characterized by using a padding capacitor and a variable capacitance diode. (2) The local oscillation circuit is connected to an oscillation coil, a first parallel capacitance element connected in parallel to the oscillation coil, and a connection point between the first parallel capacitance element and the oscillation coil. padding capacitor and
A variable capacitance diode connected between the other end of the padding capacitor and the other end of the oscillation coil, and switching means for selectively electrically connecting the parallel capacitance element, and the switching means: A local oscillation circuit according to claim 1, which obtains different local oscillation frequencies from the local oscillation circuit. (3) A second terminal is connected to the other end of the padding capacitor.
and a third parallel capacitive element are connected, and either the second or the third parallel capacitive element is electrically connected by the switching means, whereby a different local A local oscillation circuit according to claim 2 of the utility model registration claim for obtaining an oscillation frequency. (4) A second parallel capacitive element is connected to the connection point between the padding capacitor and the tuning coil, and the switching means connects the other end of the second parallel capacitive element to the tuning coil. 3. The local oscillation circuit according to claim 2, which obtains different local oscillation frequencies from the local oscillation circuit by electrically connecting the other end thereof. (5) A third parallel capacitance element is connected to the connection point between the padding capacitor and the variable capacitance diode, and the switching means connects the third parallel capacitance element to the other end of the variable capacitance diode. Utility model registration claim No. 2, which obtains different local oscillation frequencies from the local oscillation circuit by electrically connecting it.
Local oscillation circuit described in section.
JP8220186U 1986-05-30 1986-05-30 Pending JPS62193336U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8220186U JPS62193336U (en) 1986-05-30 1986-05-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8220186U JPS62193336U (en) 1986-05-30 1986-05-30

Publications (1)

Publication Number Publication Date
JPS62193336U true JPS62193336U (en) 1987-12-09

Family

ID=30934636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8220186U Pending JPS62193336U (en) 1986-05-30 1986-05-30

Country Status (1)

Country Link
JP (1) JPS62193336U (en)

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