JPS62191960A - Information processor - Google Patents

Abstract

PURPOSE:To optimize the processing speed of a computer as a whole by changing dynamically the speed of a CPU in accordance with the speed of a device connected to the CPU. CONSTITUTION:A memory 3 and an I/O 3 are arranged on the logical address space of a CPU 1, and by a control device 4 to decode and address bus 5 and a control signal 7, writing and reading are controlled. The control device 4 holds the information of the number of the weight and the clock speed in accordance with the speed of a memory 2 and an I/O 3. The CPU 1, each time the memory 2 and the I/O 3 are accessed, adjusts the number of the weight of the CPU 1 with a control line 10 and adjusts the clock speed with a control line 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to an information processing device that can optimize the access speed to memory and Ilo according to the speed of the memory connected to the CPU and the speed of (10). be.

[Prior Art] Generally, in order to change the processing speed of a CPU, a circuit for controlling the weight stay 1 of the CPU is provided on the side of a device connected to the CPU.

[Problems to be Solved by the Invention] In this method, if the speed of the memory or ■/○ differs, the circuit must be changed to generate the number of waits according to the speed.

Therefore, when using a mixture of memories with different speeds, the access speed to the memory must be adjusted to match the memory with the slowest speed.Also, when Iloes with different speeds are mixed, the memory As in the case of , the processing speed is adjusted to the slowest Ilo, or the wait state is not set for each individual Ilo, which causes the processing speed of the entire computer to be reduced.

Therefore, the present invention optimizes the processing speed of the entire computer by automatically generating clock speeds according to the speeds of memories and Ilo's that are located in different address areas. , which solves the above-mentioned problems.

[Means for Solving the Problems] The present invention provides a central processing unit, an input/output port, a memory, a means for instructing a clock speed according to an address area of the input/output port and the memory, and a system from the means. and means for controlling the clock of the solid device according to an instruction.

[Example] FIG. 1 shows an outline of the present invention. 1 is CPU
, 2 is memory, 3 is Ilo, 4 is a control device, 5 is an address bus, 6 is a data bus, 7 is a control I/roll bus, 8
9 is a memory control line, 9 is an I10 control line, 10 is a CPU wait number control line, 11 is a CPU clock speed control line, 12 is a clock generator, and 13 is a clock supply line to the CPU.

Memory No. 2 and Ilo No. 3 are arranged on the logical address space of CPU No. 1, and writing and reading are controlled by a control device 4 that decodes an address bus 5 and a control signal 7.

In addition, the control device 40 holds information on the number of waits and clock speed according to the speed of the memories 2 and 103, and uses the control line 10 every time the CPU 1 accesses the memories 2 and 103. A control line 11 is used to adjust the wait number of the CPUI, and a control line 11 is used to adjust the clock speed.

FIG. 2 shows one embodiment of the invention. 1
4 is the CPU, 15 is the memory, 16 is the engineering 10. 17 is the speed of the CPU, which is equipped with a register that stores information on the number of waits to be generated for each divided address area and clock speed, and a comparator that compares the addresses. 18 is a device that decodes the address and control I/roll signals and controls writing/reading of the memo IJ15 and l1016 and the control device 17; 20 is a control/roll bus; 21 is an address bus; 22 is a data bus, 2
3.24.25 is the line that controls writing/reading, 2
6 is a line for controlling the wait number of the CPU, 27 is a line for controlling the clock speed of the CPU, 19 is a clock generator, and 28 is a clock supply line to the CPU.

Here, the CPU sends WAY! to the 17 control devices for each divided address! - When the number and clock speed information is written, when 15 memories and 16 Ilo are accessed from the CPU, the 17 control devices change the CPU 14 so that the execution speed corresponds to the address placed in each device. Control execution speed.

FIGS. 3, 4, and 5 show other embodiments.

In Figure 3, 30 is CPU, 31 is memory, 32 is Ilo, 33 is FROM (programmable ROM)
, 34 is a device for controlling the wait number and clock speed of the CPU, 35 is an address decoder, 36 is a clock generator, 37 is an address bus, 38 is a data bus, 3
9 is a control bus, 40.41.4'6 is a read/write control line, 42 is a CPU wait number control line, 43 is a clock speed supply line, 44 is a clock supply line to the CPU, 45 is the data bus of PROM33.

The FROM 33 stores information on the number of waits and clock speed corresponding to each divided address, and a data pattern corresponding to the address area to be accessed is output to the data bus 45. Decode the pattern to control the execution speed of the CPU.

In FIG. 4, 50 is a CPU, 51 is a memory, 52 is an Ilo, 53 is a rewritable memory (hereinafter abbreviated as RAM), 54 is a device that controls the wait number and clock speed of the CPU, and 55 is a 1-bit 56 is a clock generator; 5 is an address decoder including a flip-flop;
7 is an address bus, 58 is a data bus, 59 is a control bus, 60.61.66 is a read/write control line, 62 is a CPU way I/number control line, 63 is a clock speed control line, □64 is to the CPU A clock supply line 65 is a data bus for the RAM 53.

53 RAM corresponds to each divided address.
CPU weight and clock speed information is stored, but this is only written by the program when the flip-flap in 55 is reset;
Flip-flops are set. After that, RAM5
3 has the same function as FROM33 in FIG.

In FIG. 5, 70 is a CPU, 71 is a memory, 72 is an engineering/○, and 73 is a programmable logic array (PLA).
), 74 is a clock generator, 75 is an address bus,
76 is a data bus, 77 is a control I/roll bus, 78.
79 is a read/write control line, 80 is a CPU clock control line, 81 is a CPU wait number control line, and 82 is a clock supply line to the CPU.

73 PLA corresponds to each divided address.
A circuit that controls the number of wait times and clock speed of the PU is electrically baked in, and the optimal CPU execution speed is selected for each accessed address.

[Effect of the invention] As described above, if the speed of the CPU is dynamically changed according to the speed of the devices connected to the CPU (memory, memory, etc.), the processing speed (throughput) of the entire computer can be increased.
Has increased significantly, and pay attention to the speed of memory and Ding 10, the speed of each device is different, way! - Eliminates the need to design control circuits.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the concept of the present invention. FIGS. 2, 3, 4, and 5 show embodiments in which the control device 4 in FIG. 1 is composed of discrete logic circuits, FROM, RAM, flip-flops, and PLA, respectively. The block diagram shown. 1.14,30,50.70...CPU 2.15,31,51.71...Memory 3.16,32. '52.72...l10 4.17,34,54.73...CPU execution speed control device. Applicants: Seiko Epson Co., Ltd. Agent, Patent Attorney Tsutomu Mogami, and others. 5ha Heguden 2 Figure 1 Figure 2 Figure 4v! J

Claims (1)

[Claims] A central processing unit, an input/output port, a memory, means for instructing a clock speed according to an address area of the input/output port and the memory, and means for controlling a clock of the central processing unit based on instructions from the means. An information processing device comprising: