JPS62191785A - Ship speed correction system of ship speed measuring apparatus - Google Patents

Abstract

PURPOSE:To enable adjustment within a short time, by providing a frequency dividing means for forming a ship speed signal by dividing the frequency of a clock pulse on the basis of a preset frequency dividing ratio and a frequency dividing ratio setting means for freely setting a frequency dividing ratio to said frequency dividing means. CONSTITUTION:When a ship goes astern, an increment/decrement change-over signal goes to L and is reversed by a reversal circuit 7 to become H and the gates of AND gate circuit 4b, 4a are respectively opened and closed. Because of this, the high frequency clock pulse outputted from a Doppler shift detection circuit is inputted to the decrement count terminal D of a presettable increment/decrement counter 1. In the counter 1, the increment/decrement change-over signal and the high frequency clock pulse are inputted to a NAND gate circuit 3b and a load signal is applied to a load terminal Ld to preset a frequency dividing ratio N set by a digital switch 6. The count 1 performs decrement counting from the frequency dividing ratio N each time a clock is inputted and, at the time of zero arrival, a borrow signal is outputted and, by the actions of an OR gate circuit 3a and the NAND gate circuit 3b, the frequency dividing ratio becomes N+1 when the next (N+1)-th clock is high. This remain the same when the ship makes headway.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention divides a clock pulse corresponding to the Doppler frequency sent from a Doppler shift detection circuit, converts it into a ship speed signal, and converts the ship speed signal into a ship speed signal. The present invention relates to a ship speed correction method in a ship speed J11 constant device of the display type.

[Prior art 1] A ship speed measurement device is installed on a ship, and then the ship is actually run in a certain test area to measure a certain distance #(1).
Measure the time required to travel between the (mile) posts and correct the ship speed display to match this.

Conventionally, this correction has generally been performed by changing the pulse repetition frequency of the clock pulse. That is, the oscillation frequency of the Glock pulse generator is changed by changing the impedance of the coil, capacitor, etc.

[Problems to be solved by the invention] However, since this conventional method changes the impedance of the coil, capacitor, etc.,
The analog value must be delicately adjusted, which takes time, and the adjustment may not be completed before the ship completes the distance post-to-post test. It was inconvenient.

In addition, although the ship speed display is generally located on the bridge, the clock pulse generator is located near the ultrasonic transducer located on the bottom of the ship or at a distance from the bridge, so it is not possible to adjust it manually. It was difficult, and we had to make adjustments while communicating. Furthermore, with conventional correction methods, it is difficult to grasp the relationship between the amount of adjustment and the amount of change in the displayed value.
There was a drawback that it took a lot of time to correct.

The present invention has been made to solve these problems.The amount of correction can be easily determined as a digital value from the difference between the actual measured value and the displayed value, and the optimum frequency division ratio can be calculated from this amount of correction as a digital value. A ship speed correction method for ship speed measurement devices that allows the displayed value to be corrected by setting the value in a short time, and allows for easy adjustment even if the clock pulse generator and display are located far apart. The purpose is to provide

[Means for Solving the Problems] The present invention provides a method for dividing a clock pulse corresponding to the Doppler frequency sent from a Doppler shift detection circuit, converting it into a ship speed signal, and displaying the ship speed signal. This is a ship speed correction method for a ship speed measurement device °δ, and as a means to solve the above problem, a variable division ratio type divider is used that divides the clock pulse according to a preset frequency division ratio to form a ship speed signal. The present invention is characterized by comprising: a frequency dividing means; and a frequency dividing ratio setting means for freely setting a frequency dividing ratio for the frequency dividing means.

As the frequency division means with variable frequency division ratio, a recenter pull counter can be used. On the other hand, the frequency division ratio setting means can use a digital switch that sets the frequency division ratio as a count target value in the presettable counter. In addition, when using a presettable up/down counter as a frequency dividing means, a comparator is attached to compare whether or not the count value reaches the count target value set in the digital switch when counting up.
This constitutes frequency dividing means.

[Operation] The present invention is configured to convert a high frequency clock pulse corresponding to the Doppler shift frequency into a ship speed signal by dividing it at a preset frequency division ratio, and by changing this frequency division ratio. By doing so, it is possible to change the ship speed signal corresponding to the same Doppler shift frequency.

The frequency division ratio can be set using digital values. Furthermore, the relationship between the frequency division ratio for dividing the Doppler shift frequency and the ship speed signal can be determined by calculation. Therefore, if there is a difference between the ship speed display value based on the ship speed signal and the actually measured ship speed value, the dividing ratio for dividing the Doppler shift frequency to match the actually measured ship speed value is calculated. You can ask for it. In practice, the calculations are made in advance and tabulated, and the optimum frequency division ratio is determined from the relationship between the difference between the ship speed signal and the actual measurement value and the Doppler shift frequency.

[Example] Embodiments of the present invention will be described with reference to the drawings.

<Configuration of the Embodiment> An embodiment of the ship speed correction method of the ship speed measurement device shown in Fig. 1 is capable of responding to both forward and astern ship speeds, and can also be used to adjust the ship speed when the ship is at rest or at slow speed. It is of a type that can also deal with fluctuations in the sign of the signal. This embodiment includes a presettable up/down counter l, which constitutes a frequency dividing means.
It is configured to include a comparator 2, a control gate group 3, an input gate group 4, an output gate group 5, and a digital switch 6 for setting a frequency division ratio.

A presettable up/down counter (hereinafter simply referred to as a counter) 1 counts up or down a high frequency clock corresponding to a Doppler shift frequency sent from a Doppler shift detection circuit (not shown). When counting down, this counter 1 is set to a count value corresponding to a preset frequency division ratio, and when the count value is down-counted to 0, it outputs a pollo signal. Note that the counter 1 may be either decimal or binary, but in this embodiment. The comparator 2, which uses a 3-digit binary coded decimal counter, compares whether or not the counted value has reached the measurement target value set in the digital switch 6, which will be described later, when the counter 1 is an amplifier count. A match signal is output when the target value is reached.

The control gate group 3 includes an OR gate circuit 3a, a Nant gate circuit 3b, an OR gate circuit 3C, and a Nant gate circuit 3d, and controls the resetting of the counter 1 and the loading of the measurement target value.

The input gate group 4 consists of AND gate circuits 4a and 4b, and the gates are selectively controlled to open and close by an up/down switching signal output from a forward/reverse discrimination circuit (not shown), and a high frequency signal corresponding to the Doppler shift frequency. A clock is selectively input to the up terminal U or down terminal of the counter 1.

The output gate group 5 is composed of AND gate circuits 5a, 5b and an OR gate circuit 5C, and gates of the AND gate circuits 5a and 5b are selectively controlled to open or close by the above-mentioned up-down switching signal, and output the above-mentioned pollo signal or coincidence signal. .

The digital switch 6 is configured to correspond to a 3-digit binary coded decimal system.
l Target values can be set. The set total ΔIII target value is sent to the counter 1 and comparator 2.

<Effect of the embodiment> Next, the operation of this embodiment will be explained.

To correct the ship speed, actually measure the ship speed by running the ship at various speeds over a predetermined distance in a test area, measuring the time, and then using this actual value and a preset frequency division ratio. This is done by detecting the error between the displayed value and the ship speed signal obtained by dividing the high frequency clock corresponding to the Doppler shift frequency. Here, a digital value is set in the digital switch 6 so that the frequency division ratio is N.

First, when the boat is moving backward, an up/down switching signal output from a forward/backward motion determination circuit (not shown) becomes low level, and a mode is entered for instructing a down count. This signal is inverted by the in/hater 7 and becomes high level, and the gate of the AND gate circuit 4b is opened, while the gate of the AND gate circuit 4a is closed. Therefore, a high frequency clock pulse output from a Doppler shift detection circuit (not shown) is input to the down count terminal of the counter 1. Further, the counter l is a Nant gate circuit 3a.
The up/down switching signal inverted to a high level and the high frequency clock are inputted to the load terminal Ld, and a load signal is applied to the load terminal Ld, so that N set in the digital switch 6 is freshened.

Counter 1 counts down from the value of this frequency division ratio N every time a clock is input, and when it reaches 0, a pollo signal is output when the input clock is low in the second half of the Nth input clock, and the OR gate Due to the action of the circuit 3a and the Nant gate circuit 3b, when the next N+1th clock is high,
A load signal is sent to the load terminal Ld of the counter 1, and N is preset to the counter 1 again. As a result, the frequency division ratio becomes N+1.

Next, in the case of the ship's 1st advance, the Gosa Sashi, which is not shown, issued from the forward and backward advance control 1.7 pdown 11 years old becomes a high level and becomes a mode for commanding an up count. . This signal opens the gate of the AND gate circuit 4a,
On the other hand, the gate of the AND gate circuit 4b is closed. Therefore, a high frequency clock pulse outputted from a Doppler shift detection circuit (not shown) is inputted to the up-count terminal U of the counter 1. Further, the above-mentioned high-level up-down signal and high-frequency clock are input to the Nant gate circuit 3d, and the counter 1 is connected to its reset terminal R.
A reset signal is input to and reset.

In the case of up-counting, the counter 1 starts counting from 0 in this way, and the count value is determined by the comparator 2 as the target count value N set in the digital switch 6.
compared to Both are equally powerful. This is caused by the action of the OR gate circuit 3C and the Nant gate circuit 3d.
When the +1st clock is high, a reset signal is sent to the reset terminal R of the counter 1, and the counter 1 is reset. As a result, the frequency division ratio becomes N+1 as in the case of down counting.

In this way, the OR gate circuit 5C of the output gate group 5
A frequency-divided output clock is output as a ship speed signal.

Next, we will explain the correction effect when the actually measured ship speed differs from the ship speed calculated from the Doppler shift frequency.

The relationship between the frequency division ratio set in the digital switch 6 and its speed display (knots) is shown in Table 1 above. here,
It is assumed that the frequency division ratio N of the digital switch 6 is set to "134". In this state, the speed is displayed as 14.8 knots).

Now, the ship speed is actually measured as described above, and the actual measured value is compared with the above-mentioned displayed value to find the error E ($) of the displayed value with respect to the actual measured value. If this error E is 10, the displayed value is larger than the actual measured value, while if it is -, the relationship is reversed. Therefore, search the error column in Table 1 above that includes the determined error E, and find the digital switch setting value in the SW setting value column at the corresponding position. For example, if the actual measured value is 14.4 knots, the displayed value is 14.8 knots, so the displayed value is -2
, contains an error of 78%. Looking at Table 1, the digital switch setting value in the error range that includes this error is "138". Therefore, this value is set in the digital switch 6.

When the above digital switch 6 is set to "13B",
The frequency division period becomes longer, and the displayed value that was excessively displayed becomes
As is clear from the table, it is 14.4 knots, and the actual Jll
matches the value.

Even if the actual value is larger than the displayed value, it can be corrected in the same way, just by changing the polarity from the above.

As described above, in this embodiment, the error between the displayed value and the actual measured value is determined, and the correction value can be easily determined by using Table 1 calculated in advance, and the display can be corrected quickly.

Other Examples> In the above example, the ship speed display for forward and backward movement of the ship is
Although this is done by using a recentable up-down counter as the frequency dividing means, it is also possible to count forward movement and backward movement using separate means.

[Effects of the Invention] As explained above, in the present invention, the amount of correction can be easily obtained as a digital value from the difference between the measured value and the displayed value, and the optimum frequency division ratio can be set as a digital value from this amount of correction. Since the displayed value can be corrected using the
This has the effect of allowing easy adjustment even if the clock pulse generator and the display section are located apart.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the ship speed correction method of the ship speed measuring device of the present invention. 1...Presettable up/down counter 2...
Comparator 3...Control gate group 3a, 3c...OR gate circuit 3b, 3d...Nant gate circuit 4...Input gate group 4a, 4b...AND gate circuit 5...Output gate group 5a, 5b...AND gate circuit 5c...OR gate circuit 6...Digital switch 7...Inverter

Claims (1)

[Claims] A ship speed correction method in a ship speed measuring device that divides a clock pulse corresponding to the Doppler frequency sent from a Doppler shift detection circuit, converts it into a ship speed signal, and displays the ship speed signal. a variable division ratio type frequency division means for dividing the frequency of the clock pulse according to a preset frequency division ratio to form a ship speed signal; and a frequency division ratio that can be freely set for the frequency division means. A ship speed correction method for a ship speed measurement device, characterized in that the ship speed correction method comprises a frequency division ratio setting means.