JPS62190952A - Transmission controller - Google Patents

Transmission controller

Info

Publication number
JPS62190952A
JPS62190952A JP61034391A JP3439186A JPS62190952A JP S62190952 A JPS62190952 A JP S62190952A JP 61034391 A JP61034391 A JP 61034391A JP 3439186 A JP3439186 A JP 3439186A JP S62190952 A JPS62190952 A JP S62190952A
Authority
JP
Japan
Prior art keywords
packet
logical
link
logical link
serial number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61034391A
Other languages
Japanese (ja)
Other versions
JPH0683254B2 (en
Inventor
Kazutomo Kobayashi
小林 和朝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61034391A priority Critical patent/JPH0683254B2/en
Publication of JPS62190952A publication Critical patent/JPS62190952A/en
Publication of JPH0683254B2 publication Critical patent/JPH0683254B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To improve throughput characteristics by forming a logical link for every partial circuit and performing error control corresponding to them. CONSTITUTION:Terminal interfaces 11 and 12 form a logical layer in a network layer and performs flow control and transmission confirmation corresponding to logical channels. Logical link control circuits 21-25 are connected corresponding to the logical channels of the terminal interface circuits 11 and 12 and perform transmission procedure, i.e., error control flow control, etc., among nodes. If the packet with a serial number B1 is sent to an opposite side by mistake, the opposite side sends back negative acknowledge(NAC) and packets of a logical link B are discarded thereafter until the packet with the serial number B1 is received. The transmission side when receiving the negative acknowledge(NAC) begins to resend packets from a packet with a serial number of the corresponding local link which is negated. Consequently, even a link which has a high transmission rate and is long in propagation delay like a satellite communication never causes the throughput and delay characteristics to deteriorate.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はパケット通信網で端末・ノード間およびノード
間の伝送手順を行なう伝送制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a transmission control device that performs transmission procedures between terminals and nodes and between nodes in a packet communication network.

(従来の技術) 従来のパケット通信における端末・ノードおよびノード
間伝送制御はネットワークレイヤでバーチャルサーキッ
トを張り、そのバーチャルサーキット対応にルーティン
グ、送達確認、フロー制御などを行ない、データリンク
レイヤでバーチャルサーキットを束にしてつまり多重化
して誤り制御およびフロー制御などを行なっていた。つ
まり、AとBとの2つのバーチャルサーキットがあった
とすると、データリンクレイヤでは2つのバーチャルサ
ーキットがあることを意識せず、新らたにパケットにシ
リアル番号を付加し、そのシリアル番号をもとに誤り再
送を行なっていた。
(Prior art) In conventional packet communications, terminal/node and inter-node transmission control involves setting up virtual circuits in the network layer, performing routing, delivery confirmation, flow control, etc. in response to the virtual circuits, and then controlling the virtual circuits in the data link layer. They were bundled or multiplexed to perform error control and flow control. In other words, if there are two virtual circuits A and B, the data link layer adds a new serial number to the packet without being aware that there are two virtual circuits, and uses that serial number as the base. erroneous retransmission.

(発明が解決しようとする問題点) 第2図に示すように従来方式では、シルアル番号2のパ
ケットが相手側に誤って届くと相手側は否定応答(NA
C)を返し、それ以降、シリアル番号2のパケラトが届
(まで、受信したパケットはすてられる。送り側では否
定応答(NAC)を受けとると、否定されたシリアル番
号のパケットから再度送り始める。これかられかるよう
に誤まるパケットを送信して、否定応答を受ける間に出
したパケットは無効となっている。したがって伝搬遅延
の長いリンクでは一担誤まると、捨てるべきパケットが
非常に多(なり、スルーブツト特性が非常に劣化すると
いう問題が生じる。
(Problems to be Solved by the Invention) As shown in FIG.
C), and from then on, received packets are discarded until a packet with serial number 2 is received ((). When the sending side receives a negative acknowledgment (NAC), it starts sending again from the packet with the rejected serial number. As we will see from now on, when a packet is sent with an error, the packet sent before receiving a negative response is invalidated.Therefore, on a link with a long propagation delay, if one error occurs, a large number of packets will have to be discarded ( Therefore, a problem arises in that the throughput characteristics are significantly deteriorated.

本発明の目的はバーチャルサーキット毎にロジカルリン
クを張り、ロジカルリンク対応に誤り制御、フロー制御
、送達確認などを行なうことにより、従来の欠点を除去
した伝送制御装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a transmission control device that eliminates the drawbacks of the conventional technology by establishing a logical link for each virtual circuit and performing error control, flow control, delivery confirmation, etc. corresponding to the logical link.

(問題点を解決するための手段) 本発明はパケット通信網の端末・ノード間およびノード
間で伝送手順を実行する伝送制御装置において、端末と
インタフェースをとるインタフェース回路と、端末と上
記インタフェース回路との間は張られている複数のロジ
カルチャネルに対応して各々が接続され、ノード間での
誤り制御およびフロー制御を行なう複数のロジカルリン
ク制御回路と、該ロジカルリンク制御回路の出力パケッ
トをパケット多重して送信する手段と、受信したパケッ
トをパケットヘッダを解読して対応する前記ロジカルリ
ンク制御回路へ分配する手段から構成されることを特徴
とする。
(Means for Solving the Problems) The present invention provides a transmission control device that executes transmission procedures between terminals and nodes of a packet communication network and between nodes, which includes an interface circuit that interfaces with the terminal, and an interface circuit that interfaces between the terminal and the above-mentioned interface circuit. A plurality of logical link control circuits each connected corresponding to a plurality of logical channels stretched between the nodes perform error control and flow control between the nodes, and output packets of the logical link control circuits are packet-multiplexed. and means for decoding the packet header of the received packet and distributing it to the corresponding logical link control circuit.

(作用) 一つのリンクにパーチャ′ルサーキットがAとB、2本
張られていたとする。本発明ではバーチャルサーキット
毎にロジカルリンクを張り、それ対応に誤り制御を行な
うので、シリアル番号はAとBに区別されて付加される
。第3図を参照して説明すると、ここで、シリアル番号
B1のパケットが誤まって、相手側に届くと、相手側は
否定応答(NAC)を返し、それ以降、シリアル番号B
1のパケットが受信されるまで、ロジカルリンクBのパ
ケットは捨てられる。送り側では否定応答(NAC)を
受けると、該当するロジカルリンクの否定されたシリア
ル番号のパケットから再度送り始める。ここで従来例と
異なるところはロジカルリンクAのパケットは捨られな
いで済むことがある。したがってスループット特性が改
善されることがわかる。
(Operation) Suppose that two virtual circuits, A and B, are connected to one link. In the present invention, a logical link is established for each virtual circuit and error control is performed accordingly, so serial numbers are added to A and B separately. To explain with reference to FIG. 3, when a packet with serial number B1 reaches the other party by mistake, the other party returns a negative acknowledgment (NAC), and from then on, the packet with serial number B1 reaches the other party.
Packets for logical link B are discarded until one packet is received. When the sending side receives a negative acknowledgment (NAC), it starts sending the packet again from the packet with the denied serial number of the corresponding logical link. Here, the difference from the conventional example is that the packets of logical link A may not be discarded. Therefore, it can be seen that the throughput characteristics are improved.

(実施例) 第1図は、本発明の一実施例を示すブロック図である。(Example) FIG. 1 is a block diagram showing one embodiment of the present invention.

端末インタフェース11.12は、端末とのインタフェ
ースをとるもので、例えばx、25端末を接続するなら
ばデータリンクレベルでHPLC手順を行ない、ネット
ワークレイヤでロジカルチャネルを張り、ロジカルチャ
ネル対応にフロー制御、送達確認を行なう。ロジカルリ
ンク制御回路21〜25は端末インタフェース回゛路1
1,12のロジカルチャネルに対応して接続され、ノー
ド間での伝送手順つまり誤り制御フロー制御などを行な
う。バッファー31ではロジカルリンク制御回路21〜
25の出力パケットをパケット多重して出力する。バッ
ファー32では受信したパケットを蓄え、スイッチ42
の接続されているロジカルリンク制御回路を送出する。
The terminal interfaces 11 and 12 are for interfacing with terminals. For example, if x25 terminals are connected, HPLC procedures are performed at the data link level, logical channels are set up at the network layer, and flow control is performed in response to the logical channels. Confirm delivery. Logical link control circuits 21 to 25 are terminal interface circuit 1
It is connected corresponding to logical channels 1 and 12, and performs transmission procedures between nodes, that is, error control flow control, etc. In the buffer 31, the logical link control circuit 21~
25 output packets are multiplexed and output. The buffer 32 stores the received packets and sends them to the switch 42.
The connected logical link control circuit is sent out.

切換制御器41ではパケットヘッダのロジカルリンク番
号を読みとり、ロジカルリンク番号に対応したスイッチ
を接続する。
The switching controller 41 reads the logical link number of the packet header and connects the switch corresponding to the logical link number.

(発明の効果) 以上説明したように、本発明によれば伝送レートが高(
、衛星通信のように伝搬遅延の長いリンクでもスループ
ットおよび遅延特性を劣化させず、しかも構成も簡単で
ある。
(Effects of the Invention) As explained above, according to the present invention, the transmission rate is high (
, it does not degrade throughput and delay characteristics even in links with long propagation delays, such as satellite communications, and has a simple configuration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す図、第2図は従来方式の
伝送手順を示す図、第3図は本発明の伝送手順を示す図
である。 図において、 11.12は端末インタフェース回路、21〜25はロ
ジカルリンク制御回路、31は送信バッファ、32は受
信バッファ、41は切換制御器、42はスイッチである
。 g         −R ヨ         ベ 第2図 端末へ 第3図 端末へ
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a conventional transmission procedure, and FIG. 3 is a diagram showing a transmission procedure of the present invention. In the figure, 11 and 12 are terminal interface circuits, 21 to 25 are logical link control circuits, 31 is a transmission buffer, 32 is a reception buffer, 41 is a switching controller, and 42 is a switch. g -R Yobe To the terminal in Figure 2 To the terminal in Figure 3

Claims (1)

【特許請求の範囲】[Claims] パケット通信網の端末・ノード間およびノード間で伝送
手順を実行する伝送制御装置において、端末とインタフ
ェースをとるインタフェース回路と、端末と上記インタ
フェース回路との間に張られている複数のロジカルチャ
ネルに対応して各々が接続され、ノード間での誤り制御
およびフロー制御を行なう複数のロジカルリンク制御回
路と、該ロジカルリンク制御回路の出力パケットをパケ
ット多重して送信する手段と、受信したパケットをパケ
ットヘッダを解読して対応する前記ロジカルリンク制御
回路へ分配する手段とから少なくとも構成される伝送制
御装置。
In a transmission control device that executes transmission procedures between terminals and nodes in a packet communication network and between nodes, it supports an interface circuit that interfaces with the terminal and multiple logical channels that are installed between the terminal and the above interface circuit. A plurality of logical link control circuits are connected to each other and perform error control and flow control between nodes, means for packet multiplexing and transmitting output packets of the logical link control circuits, and means for transmitting received packets by packet header. a transmission control device comprising at least means for decoding and distributing the decoded data to the corresponding logical link control circuits.
JP61034391A 1986-02-18 1986-02-18 Transmission control device Expired - Lifetime JPH0683254B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61034391A JPH0683254B2 (en) 1986-02-18 1986-02-18 Transmission control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61034391A JPH0683254B2 (en) 1986-02-18 1986-02-18 Transmission control device

Publications (2)

Publication Number Publication Date
JPS62190952A true JPS62190952A (en) 1987-08-21
JPH0683254B2 JPH0683254B2 (en) 1994-10-19

Family

ID=12412866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61034391A Expired - Lifetime JPH0683254B2 (en) 1986-02-18 1986-02-18 Transmission control device

Country Status (1)

Country Link
JP (1) JPH0683254B2 (en)

Also Published As

Publication number Publication date
JPH0683254B2 (en) 1994-10-19

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