JPS62189733A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62189733A
JPS62189733A JP61031731A JP3173186A JPS62189733A JP S62189733 A JPS62189733 A JP S62189733A JP 61031731 A JP61031731 A JP 61031731A JP 3173186 A JP3173186 A JP 3173186A JP S62189733 A JPS62189733 A JP S62189733A
Authority
JP
Japan
Prior art keywords
displacement
pattern
mask
light
reflected light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61031731A
Other languages
Japanese (ja)
Inventor
Tsuneaki Isozaki
磯崎 常明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61031731A priority Critical patent/JPS62189733A/en
Publication of JPS62189733A publication Critical patent/JPS62189733A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify an amendment of displacement of a mask by measuring a reflected light reflected from a semiconductor substrate through an optical discolored film between the substrate and the mask to detect the displacement of the mask, thereby eliminating a development. CONSTITUTION:When an i beam projected from a light source is emitted from X toward a direction X' and a reflected light is measured, the level of the reflected light is altered in a boundary of a pattern 7 formed in the previous step on a silicon substrate 1. The position where the level alteration crosses a slice level S is detected to measure the distance xa between points x1 and x2 and the distance xb between points x3 and x4. When it is designed that the center of an exposure portion 6 is superposed on the center of the pattern 7 already formed, the displacement DELTAx in x-axis direction can be calculated by xa-xb, and the displacement DELTAY in Y-axis direction can be similarly measured. When the displacements DELTAX, DELTAY of superposing photomasks are obtained, the displacement may be amended, and after the amendment, remaining shot is exposed on other positions 4a, 4b....

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に、光退色性
膜を透過した光の半導体装置からの反射光を測定するご
とによって露光用のマスクの位置合わせを簡単にできる
ようにした半導体装置の製造方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing an exposure mask by measuring the reflected light from a semiconductor device of light transmitted through a photobleaching film. The present invention relates to a method for manufacturing a semiconductor device that allows easy alignment.

〔従来の技術〕[Conventional technology]

従来の半導体装置の製造方法におけるマスク合わせの方
法として、例えば、マスクと半導体基板とを微小距離だ
&j離して平行にしてその拡大像を顕微鏡で見ながらX
軸、Y軸、および回転方向の位置合わせを行うようにす
るものがある。このマスク合わせによって半導体基板に
すでに形成されたパターンと次に形成されるパターンの
相対的位置にずれが生じないようにすることができ、所
定のパターンの半導体装置を製造することができる。
As a method for mask alignment in conventional semiconductor device manufacturing methods, for example, the mask and semiconductor substrate are placed parallel to each other by a minute distance, and the enlarged image is viewed with a microscope while being
There are some that perform alignment in the axis, Y axis, and rotational direction. By this mask alignment, it is possible to prevent the relative positions of the pattern already formed on the semiconductor substrate and the pattern to be formed next from being misaligned, and it is possible to manufacture a semiconductor device with a predetermined pattern.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、従来の半導体装置の製造方法におけるマスクを
合わせ方法によれば、ある要因(例えば、半導体基板上
のパターンの変形、マスクやレンズ系のゆがみ、光軸の
ずれ、半導体基板!!装ステージのずれ等)によって半
導体基板上のパターンと露光パターンの間にずれが生じ
ることがあり、このずれは露光後現像しなければ検出で
きないという不都合がある(この検出によってずれが補
正される)。
However, according to the mask alignment method in the conventional semiconductor device manufacturing method, certain factors (for example, deformation of the pattern on the semiconductor substrate, distortion of the mask or lens system, misalignment of the optical axis, A misalignment may occur between the pattern on the semiconductor substrate and the exposed pattern due to misalignment, etc., and this misalignment cannot be detected unless it is developed after exposure (this detection corrects the misalignment).

〔発明が解決しよとする問題点〕[Problem that the invention seeks to solve]

本発明は上記に鑑みてなされたものであり、現像する前
にずれを検出してその補正を簡単に行えるようにするた
め、半導体基板とマスクの間に設けられた光退色性膜を
透過して半導体基板から反射した反射光を測定するよう
にした半導体装置の製造方法を提供するものである。
The present invention has been made in view of the above, and in order to detect misalignment before development and easily correct it, a photobleachable film provided between a semiconductor substrate and a mask is provided. The present invention provides a method for manufacturing a semiconductor device in which reflected light reflected from a semiconductor substrate is measured.

〔実施例〕〔Example〕

以下本発明による半導体装置の製造方法を詳細に説明す
る。
The method for manufacturing a semiconductor device according to the present invention will be explained in detail below.

第1図は縮小投影露光系を示し、例えば、i線(波長3
65m+)を投射する光源11と、投射光を集光する集
光レンズ12と、所定の露光パターンとこの露光パター
ンから微小距離だけずれた位置にずれを補正する補正パ
ターンを有したフォトマスク13と、フォトマスク13
を透過したパターン光を所定の縮倍率に縮小してステー
ジ14上に置かれたウェハー15の所定の位置4に結像
させる縮小レンズ系16を有する。
Figure 1 shows a reduction projection exposure system, for example, i-line (wavelength 3
65m+), a condensing lens 12 that condenses the projected light, and a photomask 13 having a predetermined exposure pattern and a correction pattern at a position shifted by a minute distance from this exposure pattern to correct the shift. , photomask 13
The wafer 15 has a reduction lens system 16 that reduces the pattern light transmitted through the wafer 15 to a predetermined magnification and forms an image on a predetermined position 4 of a wafer 15 placed on a stage 14.

第2図(a)はステージ14に置かれたウェハー15を
示し、前の工程で形成されたパターンを有するシリコン
基板1と、その上に塗布されたポジ形フォトレジスト2
と、このフォトレジスト2の上に塗布された光退色性膜
3より成っている。この光退色性膜3は光を照射すると
i線の透過率が約2%から85%に変化するもので、C
EL−388(SST日本版の1985年/7月号の5
8ページ参照)が適当である。
FIG. 2(a) shows a wafer 15 placed on a stage 14, with a silicon substrate 1 having a pattern formed in the previous step and a positive photoresist 2 coated thereon.
and a photobleaching film 3 coated on this photoresist 2. When this photobleaching film 3 is irradiated with light, the i-line transmittance changes from about 2% to 85%, and C
EL-388 (SST Japanese version 1985/July issue 5
(see page 8) is appropriate.

また、フォトマスク13は第2図(b)に示すウェハー
15の中央位置4にショット露光を行うパターンが描か
れており、この中に所定の露光パターンから微小位置だ
けずれた位置に補正パターンが描かれている。この補正
パターンは、第2図(C)に示すように、未露光部5の
中に方形状の露光部6を有する。
Further, the photomask 13 has a pattern for performing shot exposure drawn at the center position 4 of the wafer 15 shown in FIG. It is depicted. This correction pattern has a rectangular exposed portion 6 within the unexposed portion 5, as shown in FIG. 2(C).

以上の構成において、ウェハー15をステージ14上に
配置してアライメントを行った後中央位置4に1シヨツ
ト露光を行う。このとき、補正パターンの露光部6を通
して光退色・性膜3が照射され、その部分に対応する領
域の光透過率が大になる。ここで、i線をXからX”の
方向に照射して反射光を測定する。
In the above configuration, after the wafer 15 is placed on the stage 14 and aligned, one shot exposure is performed at the center position 4. At this time, the photobleachable film 3 is irradiated through the exposed portion 6 of the correction pattern, and the light transmittance of the area corresponding to that portion increases. Here, the i-ray is irradiated in the direction from X to X'' and the reflected light is measured.

第2図(C1の下方の曲線Rは反射光のレベルを示し、
シリコン基板lに前工程で形成されたパターン7の境界
部で反射光のレベルが変化する。このレベル変化がスラ
スイレベルSと交差する位置を検出して点x1とx2の
距離x1および点X、とx4の距離xbを測定する。露
光部6の中心とすでに形成されているパターン7の中心
が重なるように設計しておくと、X軸方向のずれ量ΔX
はx、−Xbで算出することができる。同じようにして
、Y軸方向のずれ量ΔYも測定することができる。
Figure 2 (Curve R below C1 indicates the level of reflected light;
The level of reflected light changes at the boundary of the pattern 7 formed on the silicon substrate 1 in the previous step. The position where this level change crosses the slide level S is detected, and the distance x1 between points x1 and x2 and the distance xb between points X and x4 are measured. If the design is made so that the center of the exposure area 6 and the center of the pattern 7 that has already been formed overlap, the amount of deviation in the X-axis direction ΔX
can be calculated using x and -Xb. In the same way, the amount of deviation ΔY in the Y-axis direction can also be measured.

このようにして、フォトマスク13の重ね合わせのずれ
量ΔX、ΔYが求まると、そのずれを補正すれば良い。
Once the amounts of deviation ΔX and ΔY in the overlapping of the photomasks 13 are determined in this way, the deviation can be corrected.

この補正後、第2図(dlに示すように、ウェハーに1
5の他の位置4a、4b−・・−・・−・・・に残りの
ショットを露光する。
After this correction, as shown in FIG.
The remaining shots are exposed at other positions 4a, 4b of 5.

以上の実施例では、光退色性膜3を〕第1・レジスト2
上に塗布したが、これに限定するものではな(、第1図
において、フォトマスク13とウェハー15を結ぶ光路
上の任意の位置に変更しても良い。
In the above embodiments, the photobleachable film 3 is used as the first resist 2.
Although the coating is applied above, the present invention is not limited thereto (in FIG. 1, it may be applied to any position on the optical path connecting the photomask 13 and the wafer 15).

〔発明の効果〕〔Effect of the invention〕

以上説明した通り、本発明の半導体装置の製造方法によ
れば、半導体基板とマスクの間に設けられた光退色性膜
を透過して半導体基板から反射した反射光を測定してマ
スク合わせのずれを検出するようにしたため、現像を行
う必要性をなくしてその補正を簡単に行うことができる
As explained above, according to the method of manufacturing a semiconductor device of the present invention, the reflected light transmitted through the photobleachable film provided between the semiconductor substrate and the mask and reflected from the semiconductor substrate is measured to determine the misalignment of the mask alignment. Since this is detected, the need for development can be eliminated and the correction can be easily performed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は縮小投影露光系を示す説明図。第2図(al〜
(d+は本発明の一実施例を示す説明図。 符号の説明 1−・−一−−−−−−半4体基板   2−・−・−
−−−−フォトレジスト3−−一・−光退色性膜
FIG. 1 is an explanatory diagram showing a reduction projection exposure system. Figure 2 (al~
(d+ is an explanatory diagram showing one embodiment of the present invention. Explanation of symbols 1--1--Half quadrilateral board 2----
---Photoresist 3--1.-Photobleachable film

Claims (1)

【特許請求の範囲】 フォトマスク上に描かれたパターンに基づいて半導体基
板上のフォトレジストを露光する半導体装置の製造方法
において、 前記フォトマスクに所定の形状の露光部を有した補正用
マスクを形成し、 前記フォトマスクとフォトレジストの間に露光によって
光透過率が大になる光退色性膜を配置し、 前記フォトマスクの前記露光部を介して前記光退色性膜
を露光し、 前記光退色性膜の露光によって光透過率が大になった部
分を透過した光を先にパターンが形成されている前記半
導体基板によって反射させ、この反射光によってマスク
合わせのずれを検出することを特徴とする半導体装置の
製造方法。
[Claims] A method for manufacturing a semiconductor device in which a photoresist on a semiconductor substrate is exposed to light based on a pattern drawn on a photomask, the photomask including a correction mask having an exposure portion of a predetermined shape. forming a photobleachable film that increases light transmittance upon exposure between the photomask and the photoresist; exposing the photobleachable film to light through the exposed portion of the photomask; The method is characterized in that the light transmitted through a portion of the fading film whose light transmittance is increased by exposure to light is first reflected by the semiconductor substrate on which a pattern is formed, and the misalignment of the mask alignment is detected by this reflected light. A method for manufacturing a semiconductor device.
JP61031731A 1986-02-14 1986-02-14 Manufacture of semiconductor device Pending JPS62189733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61031731A JPS62189733A (en) 1986-02-14 1986-02-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61031731A JPS62189733A (en) 1986-02-14 1986-02-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62189733A true JPS62189733A (en) 1987-08-19

Family

ID=12339184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61031731A Pending JPS62189733A (en) 1986-02-14 1986-02-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62189733A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6433314A (en) * 1987-07-29 1989-02-03 Giken Seisakusho Kk Method and apparatus for constructing steel tubular pile

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6433314A (en) * 1987-07-29 1989-02-03 Giken Seisakusho Kk Method and apparatus for constructing steel tubular pile

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