JPS6218938B2 - - Google Patents
Info
- Publication number
- JPS6218938B2 JPS6218938B2 JP52158731A JP15873177A JPS6218938B2 JP S6218938 B2 JPS6218938 B2 JP S6218938B2 JP 52158731 A JP52158731 A JP 52158731A JP 15873177 A JP15873177 A JP 15873177A JP S6218938 B2 JPS6218938 B2 JP S6218938B2
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- register
- branch
- gate
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Executing Machine-Instructions (AREA)
- Calculators And Similar Devices (AREA)
- Microcomputers (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US75779176A | 1976-12-27 | 1976-12-27 | |
| US76699877A | 1977-02-09 | 1977-02-09 | |
| US05/767,084 US4112495A (en) | 1977-02-09 | 1977-02-09 | Electronic calculator or microprocessor having a selectively loadable instruction register |
| US05/767,086 US4100606A (en) | 1977-02-09 | 1977-02-09 | Key debounce system for electronic calculator or microprocessor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5383544A JPS5383544A (en) | 1978-07-24 |
| JPS6218938B2 true JPS6218938B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1987-04-25 |
Family
ID=27505681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15873177A Granted JPS5383544A (en) | 1976-12-27 | 1977-12-27 | Electronic microprocessor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5383544A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
| DE (2) | DE2760415C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5024770A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1973-07-05 | 1975-03-17 | ||
| US3919532A (en) | 1973-09-13 | 1975-11-11 | Texas Instruments Inc | Calculator system having an exchange data memory register |
| US3934233A (en) | 1973-09-24 | 1976-01-20 | Texas Instruments Incorporated | Read-only-memory for electronic calculator |
| US3988604A (en) | 1974-11-19 | 1976-10-26 | Raymond Jr Joseph H | Electronic calculator or digital processor chip having multiple function arithmetic unit output |
| US3931507A (en) | 1974-11-26 | 1976-01-06 | Texas Instruments Incorporated | Power-up clear in an electronic digital calculator |
| DE2516370C3 (de) * | 1975-04-15 | 1983-01-05 | Nixdorf Computer Ag, 4790 Paderborn | Verfahren und Schaltungsanordnung zur Ermittelung der Betätigung der Tasten eines Tastenfeldes |
-
1977
- 1977-12-27 DE DE2760415A patent/DE2760415C2/de not_active Expired - Lifetime
- 1977-12-27 JP JP15873177A patent/JPS5383544A/ja active Granted
- 1977-12-27 DE DE19772758160 patent/DE2758160A1/de active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE2760415C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1991-10-17 |
| JPS5383544A (en) | 1978-07-24 |
| DE2758160A1 (de) | 1978-07-20 |
| DE2758160C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1987-08-13 |
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