JPS62188872A - Communication control system for fluid control valve - Google Patents

Abstract

PURPOSE:To simplify a control processing by setting plural self addresses in accordance with control equipment and providing a multiple address judging means which outputs a control signal in accordance with the control command bit of received data when the self address has been judged from the received data. CONSTITUTION:A central unit is receiving plural control signals from external control device and the signal from a light receiving circuit 19 is output into a control circuit 21. When normal data receiving is confirmed by parity check, an operation signal 24 is output to a multiple address judging circuit 22. Then self addresses are compared, and control signal in accordance with the control command bit of received data is output. In this way the control processing of transmission and reception in the central unit can be simplified.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to communication of a fluid control valve in which a control signal is transmitted from a central unit to a plurality of terminal units via an optical fiber link to remotely control a fluid control valve. Regarding control systems.

(Prior Art) Conventionally, as a system for remotely controlling a plurality of fluid control valves provided on a terminal side using a sequence controller or the like, for example, the system shown in FIG. 7 is known.

In FIG. 7, 100 is a control device using a programmable sequencer or the like, and from the control device 100 to the terminal 10.
Control signals are supplied by connecting signal lines to the solenoid valves V of the solenoid valves 2a, 102b, . A limit switch LS for detecting the operating state is provided, and each terminal 1 is provided with a limit switch LS for detecting the operating state.
Control device for limit switches LS of 02a to 102n
The signal line is connected to 100.

Further, the terminals 102b to 102n are equipped with one solenoid valve V and a limit switch LS, but the terminal 102a is equipped with two solenoid valves V and a limit switch LS, and therefore the terminal 102 and Four signal lines are required to be connected to the control device 100, and the number of signal lines increases depending on the number of solenoid valves and limit switches provided at one terminal.

(Problems to be Solved by the Invention) However, in such a conventional remote control system, signal lines are connected between the control device 100 and the solenoid valves and limit switches LS of the terminals 102a to 102n, respectively. For example, since a sequence controller can usually connect 50 to 100 terminals, the number of signal lines increases when the signal line connection with the limit switch LS is included, and the signal line facility work when installing the system becomes difficult. This was difficult and caused an increase in costs.

In order to solve this problem, the inventors connected a plurality of terminal units to the central unit in a loop via optical fiber lines, and transmitted communication control data including terminal addresses and control commands from the central unit to the central unit via serial optical fibers. It converts it into a signal and transmits it, and when the terminal unit receives this transmission data and determines its own address, it outputs a control signal corresponding to the control command bit of the received data to a control device such as a solenoid valve. We are proposing a communication control system.

However, in the above communication control system, since communication control is planned between a terminal device equipped with one solenoid valve, one bit is assigned to the control command bit of the communication control data, and the start bit, The communication control data consisting of address bits, control command bits, parity bits, and end bits is suppressed to, for example, 10 bits, and by simplifying the bit configuration, a simple communication control CPU can be used in the center and terminals. There is.

However, depending on the terminal device, a single terminal device may be equipped with multiple solenoid valves to perform sequence control, or, for example, two electromagnetic solenoids may be turned on and off like a normal 3-position switching valve. For example, if one terminal device has two control devices, a control command of at least 2 bits is required. For this reason, as the number of control devices managed by one terminal unit increases, the number of control bits included in the communication control data must be increased, and it is necessary to secure the number of control bits for the maximum number of control devices. As the number of bits of communication control data increases, an expensive communication control CPU, such as a 16-bit CPU, must be prepared, resulting in a significant increase in system cost.

(Means for Solving the Problems) The present invention has been made in view of such conventional problems, and even if a plurality of control devices are provided in a terminal device controlled by one terminal unit, 1 from central unit
An object of the present invention is to provide a communication control system for a fluid control valve that is highly economical and is capable of controlling a plurality of control devices by transmitting communication control data having one control command bit to a terminal unit.

In order to achieve this object, the present invention connects a plurality of terminal units installed integrally with or near the fluid control valve to the central unit via an optical fiber line in a loop, and centrally connects the central unit with a single optical fiber line. Connect the unit and multiple terminal units.

A central unit that connects multiple terminal units with such a loop-shaped optical fiber link transmits communication control data including control commands (1 bit) and terminal addresses based on control output from a sequence controller etc. in a serial optical fiber link. converted into a signal and sent to the optical fiber line, while
The terminal unit converts the optical signal obtained through the optical fiber line into received light data, and in synchronization with the detection of the end of reception of the received light data, converts the received light data again into a serial optical signal and transmits it to the subsequent optical fiber. When it determines its own address from the received light data, it outputs a control signal according to the control command bit of the received light data to the control 11 equipment such as a fluid control valve.

Furthermore, in a terminal unit equipped with multiple control devices, multiple self-addresses are set according to the terminal devices, and when one of the self-addresses is determined from received data, the control device corresponding to the determined address is set. A multiple address determining means is provided for outputting a control signal according to the control command bit of the received data.

(Function) According to the fluid control valve communication control system of the present invention, the terminal unit that controls a plurality of control devices has a plurality of self-addresses set according to the terminal devices. By creating and transmitting address data for each control device without increasing the control command bits of the communication control data, the multiple address discrimination means in the terminal unit can discriminate the communication control data for each control device and use multiple control devices. Communication can be controlled.

(Example) FIG. 1 is an explanatory diagram showing the system configuration of the present invention.

First, the configuration will be described. Reference numeral 1 denotes a central unit, which receives a plurality of control signals from an external control device 2 such as a sequence controller.

FIG. 2 is a block diagram showing an embodiment of the central unit 1 shown in FIG. 1. First, a transmission control circuit 6. The clock generator includes a 7° parallel-to-serial converter 8 and a light emitting circuit 9.

A plurality of control signals 10a to 1on are supplied to the transmission control circuit 6 from an external control device 2 such as a sequence controller, and the transmission control circuit 6 is realized by program control of a microcomputer, for example, and a clock generator. Since the control signals 10a to 10n are sequentially read by timing control based on the clock pulse from 7, and a terminal address is determined in advance for each control signal 108 to 10n, the terminal address and control command corresponding to the control signal are included. For example, 10-bit communication control data is created and output to the parallel-to-serial converter 8. The communication control data generated by the transmission control circuit 6 has the bit configuration shown in FIG. 4, including a start bit S, 6-bit address bits AO-A5 . It has a 10-bit bit configuration consisting of a control bit C serving as a control command bit, a parity bit P for parity checking, and an end bit E indicating the end of data.

Here, since address bits AO-A5 are 6 bits, addresses can be specified for a maximum of 64 terminal devices. In addition, since the terminal device subject to communication control is an on/off control device such as a solenoid valve or electromagnetic solenoid, control bit C is set to “1” when the control device is operated.
”, which has bit content that becomes rOJ when the control device is inactive.

Referring to FIG. 2, the 10-bit communication control data given to the parallel to serial converter 8 from the transmission control circuit 6 is converted into serial data in synchronization with the transmission clock from the transmission control circuit 6. The light emitting circuit 9 drives the light emitting element to emit light with the data bit "1", and the data bit "1" drives the light emitting element to emit light.
At "O", the driving of the light emitting element is stopped, and an optical signal representing the bit state of the communication control data serially outputted from the parallel-to-serial converter 8 is sent to the optical fiber line 3.

On the other hand, as a data receiving means of the central unit 1, a light receiving circuit 11. A heavy duty converter 12 and a decoding circuit 13 are provided.

An optical signal of communication control data sent to the optical fiber line 3 is returned to the light receiving circuit 11 after a predetermined transmission time via a plurality of terminal units connected in a loop.
The returned light reception signal is converted into light reception data, and the data bits are sequentially input to the heavy-air converter 12.
When receiving communication control data for one terminal, it outputs 10-bit parallel received data consisting of start bit S to end bit E to decoding circuit 13.

In this example, as will be explained later,
When the terminal unit receives communication control data from the central unit 1 and determines its own address,
Because the control bit C of the communication control data is replaced with the data bit D indicating the operating state of the terminal device by the detection signal of the operating state by the control t1 device corresponding to address discrimination, and the data bit D is sent to the subsequent optical fiber line.
The bit corresponding to the control bit C of the parallel light reception data output from the parallel-to-serial converter 12 is received as the data bit D.

That is, as shown in FIG. 5, the received data at the central unit 1 has a start bit S and an address bit A.
O~A5. Parity bit P and end bit E are the same as the transmission data in Figure 4, but the bit following the address bit is rewritten to data bit D, which indicates the operating status of the terminal equipment, by the transmission operation in the terminal unit. .

The decoding circuit 13 that receives the received data from the heavy weight converter 12 determines the terminal device from the address bits Ao to A5, and the operating state of the terminal device from the data bit D. Detection signals '148 to 14n indicating the operating state of the terminal device are output to the output line, and based on the detection signal, the operating state of the terminal device can be displayed on the external control device 2 such as a sequence controller.

Referring again to FIG. 1, a plurality of terminal units 4 are connected to the central unit 1 via an optical fiber line 3.
a, 4b, . . . 4n are connected in a loop. Each of the terminal units 4a to 4n is provided with valve units 5a, 5b, ... 5n to be controlled, and the terminal units 4a to 4n are installed integrally with the valve units 5a to 5n or in the vicinity thereof. It becomes like this.

Note that power can be supplied to the terminal units 4a to 4n individually on the terminal side, but power can be supplied from the center unit 1 side by using a composite cable integrally equipped with a power supply line as the optical fiber line 3. You can do it.

The valve unit 5a provided corresponding to the terminal unit 4a has, for example, a three-position switching valve 15, and the hydraulic cylinder 17 can be driven back and forth by switching the hydraulic pressure by the three-position switching valve 15.

The three-position switching valve 15 has a pair of electromagnetic solenoids 16a and 16b for switching the spool, and when viewed from the terminal unit 4a, the electromagnetic solenoids 16a and 16b serve as control devices controlled by communication. Furthermore, limit switches 18a and 18b are provided at two locations on the piston rod of the hydraulic cylinder 17 to detect the operating position of the hydraulic cylinder 17.
The operating state of the hydraulic cylinder 17 is detected by turning on and off the limit switches 18a and 18b.

In addition, a valve unit 5b corresponding to the terminal unit 4b
- For example, two 3-position switching valves 15a, '15b
A three-position switching valve 15a is provided.

15b is a hydraulic cylinder 17a with position pressure switching.

17b is reciprocated, and the hydraulic cylinder 17a.

A pair of limit switches 18a are provided on the piston rod 17b for detecting the cylinder operating position.

18b, 18C, and 18d are provided, and each of the three-position switching valves 15a, 15b is also provided with a pair of electromagnetic solenoids 16a, 16b, 16c, '16 for switching the spool.
It is equipped with d. Therefore, when looking at the valve unit 5b from the terminal unit 4b side, the four electromagnetic solenoids 1
63 to 16d will be provided as control devices.

In this way, the valve units 5a to 5n controlled by the terminal units 4a to 4n are provided with a plurality of control devices such as electromagnetic solenoids. And the terminal unit 4a
~4n to multiple control devices of valve units 5a to 5n are given control signals to be received by communication control, and furthermore, the operating status of the devices in the valve units detected by limit switches etc. A detection signal indicating this is input to the terminal units 4a to 4n.

FIG. 3 is a circuit block diagram showing an embodiment of the terminal unit 4a in the embodiment of FIG. 1, and an electromagnetic solenoid 16a is provided on the valve unit 5a side.

A case is taken as an example in which two control devices consisting of 16b are provided.

In FIG. 3, 19 is a light receiving circuit, which receives an optical signal of communication control data transmitted from the central unit 1 via the optical fiber line 3 and converts it into received light data.
The received light data is serially input to the heavy-light converter 20 for each data bit. The parallel converter 20 converts 10-bit received data for one terminal into parallel data and outputs it to the control circuit 21.

The control circuit 21 is realized by program control of a microcomputer, and performs light reception control and transmission control by timing control based on clock pulses from a clock oscillator 29.

That is, the control circuit 21 receives the input of the first start bit S and performs the control operation, since the light receiving circuit 19 serially receives the communication control data and the light receiving data bit output is sequentially obtained from the heavy weight converter 20. When the address bit AO-A5 and the parity bit P following the control-C are input, a parity check is performed to see if the addition result of the received bits S-C is a predetermined odd or even number. When normal data reception is confirmed by this parity check, an operation signal 24 is output to the multiple address discrimination circuit 22 to start address discrimination. In addition, when the end bit E indicating the end of data reception is obtained, the control circuit 21 detects the end of data reception for one terminal, latches the parallel light reception data output of the serial to parallel converter 20, and converts the data from parallel to parallel. Output to converter 25. Further, the control circuit 21 sequentially outputs a transmission clock to the parallel-to-serial converter 25 at the same time as detecting the end of data reception based on the end bit E, and transmits the received light data input in parallel from the control circuit 21 to the parallel-to-serial converter 25. is converted into serial data and supplied to the light emitting circuit 26, which converts it again into an optical signal and sends it out to the optical fiber line 3 at the subsequent stage.

Note that at the same time as the transmission of the received light data starts based on the detection of the end of data reception for one terminal, the light receiving circuit 19 receives data for the next one terminal. 21 resets the parallel-to-serial converter 20 to prepare for the next data reception.

Two self-addresses corresponding to the two electromagnetic solenoids 16a and '16b provided in the valve unit 5a under the jurisdiction of the terminal unit 4a are preset in the multiple address discrimination circuit 22, and the control circuit is configured based on the parity check. When the operation signal 24 is received from the electromagnetic solenoid 16a, the address bits AO to A5 inputted from the heavy weight converter 20 are compared with two preset self-addresses, and, for example, the self-address corresponding to the electromagnetic solenoid 16a is received. When it discriminates, it outputs a discrimination signal 27a that becomes H level, and on the other hand, when it discriminates the self address corresponding to the electromagnetic solenoid 16b, it outputs a discrimination signal 27b that becomes H level. The H level state of this discrimination signal 27a or 27b is determined by the control circuit 21.
is held until it outputs the operation signal 24 in a parity check based on the next received light data.

The discrimination signal 27a from the multiple address discrimination circuit 22 is input to one of the AND gates 28a, and the discrimination signal 27a is input to one side of the AND gate 28a.
b is input to one side of the AND gate 28b. The latch circuit 2 is connected to the other input of the AND gates 28a and 28b.
The bit signal of the control bit C of the heavy-weight converter 20 latched at 9 is given, for example, the discrimination signal 27
When a becomes H level, the AND gate 28a is set to the allowable state, and the bit signal of the control bit C from the two latch circuits is output to the drive circuit 30a, and when the control bit C is "1", the electromagnetic solenoid 16a is turned on, and At rOJ, the electromagnetic solenoid 16a is turned off.

Similarly, for the AND gate 28b, the discrimination signal 27b
becomes the H level, it enters the permissible state, and the latch circuit 2
The bit signal of the control bit C latched at 9 is output to the drive circuit 30b, and the electromagnetic solenoid 16b is turned on and off based on the control bit C.

Furthermore, in the embodiment of the terminal unit 4a shown in FIG. 3, when transmitting the received light data to the optical fiber line 3 at the subsequent stage, the multiplex address discrimination circuit 22 converts the control bit C of the received light data into two self-addresses. limit switch 18a or 18 on the condition that either of the
It has the ability to rewrite and transmit the control bit C indicating the operating state of the terminal device detected in step b, that is, the hydraulic cylinder.

That is, the ON/OFF detection signals of the limit switches 18a and 18b provided on the valve unit 5a side are transmitted by the detection circuit 31a.
, 3'lb. For example, when the limit switches 18a, 18b are turned on, the detection circuits 31a, 3'lb go high.
It produces a level output, and produces an L level output when it is off. The detection outputs of the detection circuits 31a and 31b are the AND gates 32a,
32b, a discrimination signal 27a from the multiple address discrimination circuit 22 is supplied to the other of the AND gate 32a, and a discrimination signal 27b is supplied to the other input of the AND gate 32b.

That is, the limit switch 18a is the electromagnetic solenoid 16a.
Detects the operating state by turning on the limit switch 18.
b has a correspondence relationship that detects the operating state when the electromagnetic solenoid 16b is turned on, so when the address discrimination signal 27a corresponding to the electromagnetic solenoid 16a becomes H level, the AND gate 32a allows the detection signal of the detection circuit 31a to pass. Also, when the address discrimination signal 27b corresponding to the electromagnetic solenoid 16b becomes H level, the AND gate 3 is activated.
2b allows the detection signal of the detection circuit 31b to pass through. The outputs of the AND gates 32a and 32b are combined by an OR gate 33 and supplied to a data rewriting circuit 34.

The data rewriting circuit 34 has AND gates 35 and 36 and an OR gate 37, and inputs the bit signal of the control bit C of the light reception data latched by the control circuit 21 into one of the AND gates 35 and into one of the AND gates 36. is given the detection signal of the detection circuit 31a or 31b collected by the OR gate 33. The other input of the AND gate 35 is an inverted input, and receives the output of the OR gate 38 which compiles the address discrimination signals 27a and 27b, and the AND gate 36 similarly receives the output of the OR gate 38.

Therefore, the AND gate 35 is connected to the multiple address discrimination circuit 22.
When neither of the two light-receiving addresses set in is identified, the inverted input of the L level output of the OR gate 38 enters the allowable state, and the bit signal of the control bit C from the control circuit 21 is passed through the OR gate 37. The received control bit C bit signal is supplied to the parallel-to-serial converter 25 as it is. On the other hand, when the multiple address discrimination circuit 22 discriminates one of the two self-addresses, the output of the OR gate 38 becomes H level, so the AND gate 35 becomes prohibited, and conversely, the AND gate 36 becomes enabled. The detection signal of the limit switch 18a or 18b obtained from the OR games 1 to 33 is supplied to the parallel-to-serial converter 25 via the OR gate 37, and the control bit C of the received data is converted to the data bit D indicating the operating state of the terminal device. It will now be sent instead.

Incidentally, the multiple address discrimination circuit 22 in the embodiment of FIG.
, a circuit unit for driving an electromagnetic solenoid based on address discrimination, and a circuit for rewriting control bit C to data bit D when the self address is discriminated are similar to the control circuit 21, regardless of the logic circuit shown in the figure. It may also be realized by program control by a microcomputer.

Next, the operation of the above embodiment will be explained.

First, data transmission control in the central unit 1 shown in FIG. 2 is performed by transmitting electromagnetic solenoids in the valve units 5a to 5n shown in FIG. 1 from an external control device 2 such as a sequence controller to the transmission control circuit 6. Control signals 10a to 10n in one-to-one correspondence are input as a control device, and the control signals 10a to 10n are sequentially read at a predetermined transmission timing based on the clock pulse from the clock oscillator 7, as shown in FIG. The bit contents of address bits AO-A5 and control bit C in the 10-bit communication control data are determined and converted into serial data by supplying a transmission clock to the parallel-to-serial converter 8, and the light emitting circuit 9
The signal is then sent to the 1IIJj optical fiber line 3 as an optical signal.

On the other hand, in the case of the terminal unit 4a shown in FIG. 3, the terminal unit that receives the communication control data in the form of an optical signal from the central unit 1 receives the optical signal serially transmitted by the light receiving circuit 19. The data bits are sequentially converted into light reception data and supplied to the heavy-light converter 20. When the first start bit S bit signal is obtained from the heavy-weight converter 20, the control circuit 21 starts the control operation and converts the 9-bit data into light reception data. A parity check is performed at the timing when the second parity bit P is obtained, and if there is no error in the received data, an operation signal 24 is output to the multiple address discrimination circuit 22, and at this time, the received address input from the multi-layer converter 20 is Bit AO
-A5 and two preset light reception addresses are compared and determined.

At this time, the terminal address of the received light data is the valve unit 5.
If it is the address of the electromagnetic solenoid 16a at point a, the multiple address discrimination circuit 22 outputs an address discrimination signal 27a that becomes H level by discrimination of the light receiving address set in advance corresponding to the electromagnetic solenoid 16a, and the AND gate 28a By setting the bit signal to the allowable state, the bit signal of the control bit C which is 1q is supplied from the two latch circuits to the drive circuit 30a, and if the control bit C is, for example, "1", the electromagnetic solenoid 16a is turned on. .

On the other hand, the control circuit 21 controls the end bit E of the heavy duty converter 20.
Detects the end of data reception from the bit output of Start converting to serial data. For this reason, the light emitting circuit 26 converts the data bits sequentially outputted from the parallel-to-serial converter 25 in synchronization with the transmission clock into an optical signal in synchronization with the detection of the end of data reception by the control circuit 21, and transmits the data bits to the optical fiber line 3 in the subsequent stage. It will start sending.

On the other hand, in response to the address discrimination signal 27a which has become H level due to the self-address discrimination by the multiple address discrimination circuit 22, the AND gate 32a enters the allowable state, and the detection circuit 31
A detection signal from limit switch 18a is output to data rewriting circuit 34 via OR gate 33. The AND gate 36 in the data rewriting circuit 34 is in the permissible state due to the address discrimination signal 27a which is at the H level obtained via the OR gates 1 to 38, and therefore the detection signal of the limit switch 18a from the OR gate 33 is transmitted to the AND gate 36. The control bit C of the received data turns on the limit switch 18a, and is further supplied to the parallel to serial converter 25 via the OR gate 37.
The data bit D is rewritten to indicate the operating state of the terminal device due to the off state, and is converted into an optical signal by the light emitting circuit 26 and sent to the optical fiber line 3 at the subsequent stage.

Next, even when received data having an address bit corresponding to the electromagnetic solenoid 16b is received, the electromagnetic solenoid 16b is controlled on and off according to the control bit of the received data, and the limit corresponding to the electromagnetic solenoid 16b is The control bits of the received data are rewritten into data bits by the on/off detection signal from the switch 18b, and then sent out to the first optical fiber line 3.

Furthermore, when received data having address bits other than the two self-addresses set in the multiple address discrimination circuit 22 is received, both the address discrimination signals 27a and 27b are at the L level, so that the electromagnetic solenoids 16a,' 1
6b is not controlled, and the AND gate 35 of the data rewrite circuit 34 is in an allowable state at the inverted input of the L level output of the OR gate 38, and the bit signal of the control bit C latched by the control circuit 21 is converted directly from parallel to serial. The received data that is not subjected to address discrimination is converted into a serial optical signal again by the light emitting circuit 26 without any modification, and is then sent to the optical fiber line 3 at the subsequent stage.

FIG. 6 shows a timing chart of data transmission and reception in the central unit and terminal units in the above embodiment.
An example will be shown in which 4d are connected in a loop. Further, as shown in FIG. 1, the terminal unit 4a has two electromagnetic solenoids 16a and 16b as control devices, and the terminal unit 4b has four electromagnetic solenoids 16a to 16b.
6d as a control device, and the terminal units 4c and 4d are each provided with a single control device such as a solenoid valve.

Communication control between the central unit 1 and the four terminal units 4a to 4d is performed by the central unit 1.
two electromagnetic solenoids 16a of the terminal unit 4a,
Communication control data a'l, a specifying the address of 16b
2 sequentially, and then communication control data b specifying the four electromagnetic solenoids 16a to 16d of the terminal unit 4b.
1 to b4 are sequentially transmitted, and since the terminal units 4C and 4d have one control device, communication control data c and d specifying each address are sequentially transmitted. The communication control data a1 to d constitute one transmission cycle. Thereafter, the central unit 1 repeats this transmission cycle.

On the other hand, in the terminal units 4a to 4d, the terminal unit 4a first receives the first data a1 in accordance with the transmission timing of the central unit 1, and when the reception of the data a1 is completed, the received data a1 is transferred to the next stage terminal. unit 4
b, and at the same time starts receiving the next data a2.

In this way, data transmission to the terminal units 4a to 4d is carried out by 1
Data is relayed and transmitted from the central unit 1 one after another with a time delay of one data. Of course, when the own address is determined from the received data, the control bit C of the received data is rewritten to the data bit D indicating the operating state of the terminal device and then sent out. The data relayed sequentially from the terminal units 4a to 4d in this way is received again by the central unit 1 after a data transmission time corresponding to the number of terminals has elapsed, and the data bits of the received data are decoded in the central unit 1. The operating status of the terminal device will be displayed.

Next, error checking of transmission data will be explained as follows.

The control circuit 21 provided in the terminal unit shown in FIG. 3 performs a parity check at the timing when the parity bit P of the received data is obtained, and if a data error is determined as a result of this parity check, multiple address determination is performed. The received data is transmitted as it is to the subsequent optical fiber line in synchronization with the detection of the end of reception without outputting the operation signal 24 to the circuit 22. Therefore, data in which an error has occurred is sent back to the central unit without being used by any of the terminal units to control the terminal equipment.

In the central unit 1, as shown in FIG. 2, data errors can be detected by checking the parity of the parallel light reception data obtained from the heavy-light converter 12.
When this data error continues for a predetermined period of time,
Assuming that normal communication control is not possible, an alarm or fail-safe operation will be performed.

In addition, as another data error detection method, as shown in FIG. 6, the central unit 1 receives data sequentially in the order of the sending addresses after a certain delay time after transmitting the data. Check and
An error is detected when addresses are received in an order different from the order in which they were sent, and when this error detection is repeated for a certain period of time, it is determined that it is a data error and an alarm or fail-safe operation can be performed.

Note that the terminal unit in Figure 3 was taken as an example where two control devices are controlled by one terminal unit.
The present invention is not limited to this, and by setting self-addresses corresponding to the number of control devices managed by the terminal unit in the multiple address discrimination circuit 22 and outputting a discrimination output for each self-address, an arbitrary number of control devices can be controlled. The device can be operated by communication control to one terminal unit. The same applies to the circuit section that rewrites the control bit C of the light reception data into the data bit D indicating the operating state of the terminal device when the light reception address is determined.

(Effects of the Invention) As described above, according to the present invention, a plurality of terminal units are connected to the central unit in a loop via an optical fiber line, and in a terminal unit equipped with a plurality of control devices, Multiple self-addresses are set according to the control device, and when one of the self-addresses is determined from the received data, a multiplex control signal is output to the control device corresponding to this determined address in accordance with the control command bit of the received data. Since we have provided a means of identifying addresses,
The number of control devices controlled by one terminal unit can be increased arbitrarily without increasing the number of control command bits in the communication control data sent from the central unit, and communication control by loop connection of optical fiber lines is possible. By minimizing the number of bits of transmission data used for transmission, the control processing of transmission and reception in the central unit and terminal units is simplified. For example, when a microcomputer is used for transmission and reception control, it is possible to reduce the number of data bits. Therefore, inexpensive elements can be used, and even if the number of control devices controlled by one terminal unit increases, a highly economical communication control system can be implemented.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of the system configuration of the present invention, FIG. 2 is a block diagram showing an embodiment of the center 1 to central unit in FIG. 1, and FIG. 3 is a terminal diagram of the terminal in FIG. 1. A circuit block diagram showing one embodiment of the unit, Fig. 4 is an explanatory diagram of the communication data from the central unit to the bit configuration, Fig. 5 is an explanatory diagram of the bit configuration of terminal return data, and Fig. 6 is an explanatory diagram of the bit configuration of communication data by the central unit. FIG. 7 is a timing chart of communication control between the unit and the terminal units 1 to 1, and is a block diagram showing a conventional example. 1: Central unit 2: External control device 3: Optical fiber lines 4a to 4n: Terminal units 5a to 50: Valve unit 6: Transmission control circuit 7.29: Clock oscillator 8.25: Parallel to serial converter 9.26: Light emitting circuit 11.'19: Light receiving circuit 12.25: Heavy duty converter 13: Decoding circuit 15: 3-position switching valves 16a to 16d: Electromagnetic solenoid 17: Hydraulic cylinders 188 to 18d: Limit switch 21: Control circuit 22: Multiplexing Address discrimination circuit 24: Operation signal 27a, 27b Near address discrimination signal 28a, 28b, 32a, 32b, 35.36: AND gate, 30a, 30b: Drive circuit 31a, 31b: Detection circuit 33.37, 38 near gate

Claims (1)

[Claims] (1) A plurality of terminal units installed integrally with or near the fluid control valve are connected in a loop to the central unit via an optical fiber line, and the central unit is given control commands based on control output from a sequence controller, etc. and a data transmitting means for converting control data including a terminal address into a serial optical signal and repeatedly transmitting the serial optical signal to the optical fiber line; At the same time, in synchronization with the detection of the end of reception of the received light data, the received light data is converted into a serial optical signal and outputted to the subsequent optical fiber line, and furthermore, the self address is determined from the received light data. In a communication control system for a fluid control valve, which is provided with a control means that outputs a control signal corresponding to the control command bit of the received light data to the fluid control valve side when it is determined, a different control unit is provided integrally with or in the vicinity of the terminal unit. A plurality of control devices operated by a signal are provided, a plurality of self-addresses corresponding to the control devices are set in the terminal unit, and when one of the self-addresses is determined from received light data, control corresponding to the determined address is provided. 1. A communication control system for a fluid control valve, characterized in that a device is provided with multiple address discrimination means for outputting a control signal according to a control command bit of received data.