JPS62187487U - - Google Patents
Info
- Publication number
- JPS62187487U JPS62187487U JP7554786U JP7554786U JPS62187487U JP S62187487 U JPS62187487 U JP S62187487U JP 7554786 U JP7554786 U JP 7554786U JP 7554786 U JP7554786 U JP 7554786U JP S62187487 U JPS62187487 U JP S62187487U
- Authority
- JP
- Japan
- Prior art keywords
- address
- address signal
- omission
- detection circuit
- detecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
Description
第１図は本考案の実施例に用いられるデイスク
のアドレス信号を示す図、第２図は同じく本実施
例の回路構成を示す図である。
１……デイスク、２……アドレス信号、３及び
４……アドレスデコーダ及びタイマー（アドレス
欠落検出回路）、５……カウンタ（疑似アドレス
信号発生回路）、６……スイツチ装置。
FIG. 1 is a diagram showing a disk address signal used in an embodiment of the present invention, and FIG. 2 is a diagram showing a circuit configuration of the same embodiment. 1...Disk, 2...Address signal, 3 and 4...Address decoder and timer (address loss detection circuit), 5...Counter (pseudo address signal generation circuit), 6...Switch device.
Claims (1)
なう装置であつて、 前記アドレス信号の欠落を検出するアドレス欠
落検出回路と、該アドレス欠落検出回路によつて
前記アドレス信号の欠落が検出された時、対応す
る疑似アドレス信号を出力する疑似アドレス信号
発生回路とを有することを特徴とするデイスク再
生装置。[Claims for Utility Model Registration] An apparatus for reproducing a disc on which address signals are recorded, comprising: an address omission detection circuit for detecting omission of the address signal; and an address omission detection circuit for detecting omission of the address signal. 1. A disc playback device comprising: a pseudo address signal generation circuit that outputs a corresponding pseudo address signal when a loss is detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7554786U JPS62187487U (en) | 1986-05-20 | 1986-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7554786U JPS62187487U (en) | 1986-05-20 | 1986-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62187487U true JPS62187487U (en) | 1987-11-28 |
Family
ID=30921789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7554786U Pending JPS62187487U (en) | 1986-05-20 | 1986-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62187487U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58137175A (en) * | 1982-02-10 | 1983-08-15 | Hitachi Ltd | Recognizing system of address information |
-
1986
- 1986-05-20 JP JP7554786U patent/JPS62187487U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58137175A (en) * | 1982-02-10 | 1983-08-15 | Hitachi Ltd | Recognizing system of address information |
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