JPS6218730U - - Google Patents
Info
- Publication number
- JPS6218730U JPS6218730U JP10687985U JP10687985U JPS6218730U JP S6218730 U JPS6218730 U JP S6218730U JP 10687985 U JP10687985 U JP 10687985U JP 10687985 U JP10687985 U JP 10687985U JP S6218730 U JPS6218730 U JP S6218730U
- Authority
- JP
- Japan
- Prior art keywords
- memory backup
- memory
- terminals
- circuit
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Power Sources (AREA)
Description
第１図は本考案に係るメモリーバツクアツプ回
路の実施例を示すブロツク図、第２図及び第３図
は従来のメモリーバツクアツプ回路を示すブロツ
ク図である。
１：パーソナル無線機本体、２：ＲＯＭカート
リツジ、１ａ，２ａ：結合部、４：端子、５：電
源端子、６：短絡線、Ｍ：メモリー回路。
FIG. 1 is a block diagram showing an embodiment of a memory backup circuit according to the present invention, and FIGS. 2 and 3 are block diagrams showing conventional memory backup circuits. 1: Personal radio main body, 2: ROM cartridge, 1a, 2a: coupling part, 4: terminal, 5: power supply terminal, 6: shorting line, M: memory circuit.
Claims (1)
より動作可能な状態となると共にメモリーバツク
アツプ用の電池を備えている電子機器のメモリー
バツクアツプ回路において、 上記電子機器における結合部の一方には短絡接
続されている複数の端子が設けられていると共に
他方の結合部には上記端子が圧接することにより
メモリー回路への電源供給路が接続されるように
配置された電源端子を備えていることを特徴とす
るメモリーバツクアツプ回路。[Scope of Claim for Utility Model Registration] A memory backup circuit for an electronic device which becomes operable by integrally combining a plurality of components and is equipped with a battery for memory backup; A power source arranged such that one of the coupling parts is provided with a plurality of short-circuited terminals, and the other coupling part is connected to a power supply path to the memory circuit by press-contacting the terminals. A memory backup circuit characterized by having a terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10687985U JPS6218730U (en) | 1985-07-15 | 1985-07-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10687985U JPS6218730U (en) | 1985-07-15 | 1985-07-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6218730U true JPS6218730U (en) | 1987-02-04 |
Family
ID=30982640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10687985U Pending JPS6218730U (en) | 1985-07-15 | 1985-07-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6218730U (en) |
-
1985
- 1985-07-15 JP JP10687985U patent/JPS6218730U/ja active Pending
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