JPS62186390A - Character recognizing method - Google Patents

Abstract

PURPOSE:To improve the recognition rate by coding a character pattern based on a so-called peripheral feature so as to recognize the pattern thereby precluding the possibility of the effect of the recognition by the fluctuation of an input pattern and applying the method for a rough classification in the recognition through the division of plural layers. CONSTITUTION:The code based on the peripheral feature is formed as to all characters of recognition object and the dictionary classified by the codes is provided. On the other hand, a document read by, e.g., an image reader is segmented one by one character by inter-line and intercharacter detection and the peripheral feature is detected as to the segmented character to form a code. Then the code from the segmented character is compared with a code provided to a dictionary and a character whose code is coincident is recognized. Thus, the recognition of rough classification is executed and the medium and small classifications are progressed, and the recognition is executed while the character pattern is coded, then the recognition is not affected by the fluctuation of input pattern and the recognition rate is improved remarkably.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Outline of the invention C. Prior art D. Problems to be solved by the invention E. Means for solving the problems (Figures 1 to 3) F
Effect G Example G, Description of the method (Figs. 1 to 3) G2 Description of the device (Figs. 4 to 6) relates to a method for identifying characters from documents printed in type.

B. Summary of the Invention The present invention relates to a character identification method, and is capable of accurate identification with a simple configuration by encoding and identifying the shape of the part of the input character that touches the circumscribed frame of the 4th turn. .

C. Prior Art Various so-called printed character identification methods have been proposed [(
Yasuda et al. 1 “Kanji recognition using hierarchical pattern matching method in the frequency domain” IEICE Vol. 58-D, A 2.19
75) (Iijima 1 Identification theory based on mixed similarity (generalization of the compound similarity method)” IEICE Research Fund PRL 74-24, 1
974)).

Regarding such an identification method, the inventor of the present application first focused on the fact that in character identification, there are major characteristics on the outer periphery, and divided the character into multiple layers at predetermined distances from the outer periphery, and for each layer, proposed a method for identifying characters by comparing them (Japanese Patent Application No. 147003/1982). According to this, first, the characters are roughly classified based on the characteristics of the outer periphery, and then the characters in the classified range are sequentially identified, so that the identification can be easily and quickly performed.

By the way, all of these identification methods generally use so-called statistical processing in which the input character pattern to be identified is compared with a preset pattern of all characters to be identified to determine its degree of success. Met.

However, in devices implementing the above-described method, input of the character pattern to be identified is usually performed through reading means such as an image reader. In that case, variations in the input cover pattern such as line width variation, tilt variation, and phase variation may occur due to variations in the slicer level within the image league, residual errors from rotation correction in preprocessing, and distortions in the optical system. It is customary to be included.

However, with the conventional techniques, it is difficult to sufficiently compensate for these fluctuations, which is also a factor in lowering the identification rate.

D. Problems to be Solved by the Invention Since the conventional technology performs identification through statistical processing, it often suffers from problems such as a significant drop in identification rate due to fluctuations in the input pattern.

E. Means for Solving the Problems The present invention provides for input character patterns cut out one character at a time, a circumscribing frame of nine turns of the input character (1st to (1d
) is detected (peripheral features),
This detected shape is coded (line segment; 1”, end point =
'0') L. This is a character identification method in which the input character pattern is identified based on this encoded data.

F Function According to this, the character /9 turn is the so-called perihuera /
Since identification is performed by coding based on I/features, there is little risk that identification will be affected by changes in input cut-turns, etc., and it is especially suitable for large classification when performing classification by dividing multiple strata. The identification rate can be significantly improved.

G Example G, Description of the Method FIG. 1 shows the character ``sea'' as an example of the 9th turn of the character. The circumscribing frame on the four sides (
1m) (Ib) (le) (ld) are set. Note that each side is named A side to D side, respectively, as shown in the figure.

For each side, the distance from its circumscribing frame (1m) to (ld) to the part constituting the character is measured, and so-called peripheral features are detected. FIG. 2 shows the peripheral characteristics on the A side described above.

The detected peripheral features are then encoded as follows.

That is, for each side, a portion where the peripheral feature is less than or equal to a predetermined distance δ is first detected. Next, it is determined whether there is a portion less than or equal to this distance δ in a predetermined area Cw at both ends of the side. Furthermore, the length W of the part less than the distance δ from one end of the side
t T W2 .

Note that the above-mentioned distance δ, area Cw, and threshold value Wo are selected as follows, for example, where W is the length of each side of the circumscribing frames (1a) to (1d).

Then, for each judgment and determined result, for each side,
First, the presence (1)/absence (0) of the character part in the upper end (left end) area
, then the presence/absence of the character part in the lower end (right end) area, followed by the line segment (1) of the character part from the upper end (left end) side and the end point (
0) are sequentially provided to form a code. Note that the code for line segments and endpoints has variable length, so a full stop (1
) is provided.

As a result, the above-mentioned co P of side A becomes W, , W2
<WTH1W3> WTH is as shown in FIG.

This application uses this code for identification.

That is, codes based on the above-mentioned peripheral characteristics are formed for all characters to be identified, and a dictionary classified using these codes is provided. On the other hand, for example, a document read by Image League is extracted character by character by line spacing and character amount detection, peripheral characteristics are detected for the extracted characters, and a code is formed. The code from this extracted character is then compared with the code provided in the dictionary mentioned above, and characters with matching codes are identified.

In this way, the major classification is identified, and then it is advanced to the medium classification or small classification. However, according to the method described above, since the character patterns are coded and identification is performed, the identification is performed based on the input pattern. There is little risk of being affected by fluctuations in the data, etc., and the identification rate can be greatly improved.

G2 Description of the Apparatus FIG. 4 shows a configuration for forming a code based on ferrule characteristics. In this figure, α℃ is a data bus, and a main memory (not shown) is connected to this path αυ via a CPU (not shown), which can be connected to the main memory by any method (for example, Patent application 1986-252173
For example, if δ=8, 1
An input character pattern of 28 x 128 pits is stored.

This main memory is then controlled by the CPU, and for each of the four circumscribing frames (1m) to (1d) for any one character/4' turn, each of the circumscribing frames (1&) to
The pattern is read out from (1d) at a depth of 16 pits,
It is supplied to the memory 4 through the data bus aη.

On the other hand, I am an address bus, and this path U has a CPU
If an arbitrary address is supplied from
) is supplied to memory (2) through (14m). As a result, the four turns of 16 bits on the four sides mentioned above are written to a predetermined address in the memory. Note that the capacity of memory 4 is 128 x 4 addresses, 16 bits per address.

Furthermore, the signal from the address bus (to) is sent to the decoder (to).
supplied to First, an arbitrary timing signal is decoded, and this signal is supplied to the latch circuit α'I)α peak, and the value of δ9wTH1Cw that is being supplied to the data bus α at that time is determined by each latch circuit α. It is latched by a camphor.

Further, the decoder 4 decodes a signal corresponding to the detection period of a pattern on one side as shown by A in the time chart of FIG. 5, and this signal is supplied to the control circuit α field. As shown in Figure B, this control circuit board includes a C8T pulse corresponding to the beginning of the A signal, an AST pulse generated after the clock pulse, and a CEN/# pulse corresponding to the end of the A signal. The AEN pulse generated two clocks later is formed.

These C8T/# pulses and CgN pulses are supplied to address counter 4. And at this counter (a).

At the time of the C8T pulse, an address corresponding to the start end of any one of sides A to D supplied to the data bus C11) is preset, and a predetermined clock signal is counted up thereafter until the CEN pulse is supplied. Furthermore, C8T
-CEN pulse corresponds to 128 clocks.

The address generated by this counter (e) is then supplied to the memory @ through data (14b). As a result, the previously written signals are sequentially read out from the memory (6) by one address at each internal clock between C8T and CEN/# as shown in C of the time chart.

After the timing of this read signal is adjusted by a latch circuit (c), it is supplied to a priority encoder (c) for detecting peripheral characteristics.

In this encoder 4, when the distance between the circumscribing frame and the character part is O, the maximum value is "15#", and a detected value is formed that decreases as the distance increases.

This detected value and the value of δ that has been checked by the latch circuit α1 are supplied to the comparator (A), and when the detected value is large, '1''
A comparison value is extracted. Furthermore, this comparison value is supplied to the flip-flop (c), and the timed comparison value X (see D in the time chart) is taken out to the Q output, and its inverted value is taken out. Note that the flip-flop (c) is cleared by the OR signal of the C8T14 pulse and the AEN pulse.

This comparison value X is supplied to a counter), and when this value X is at a high potential, locks are counted as shown at F in the time chart, and when the value X is at a low potential, the count value is cleared. This count value and the value of "TH" latched in the latch circuit αη are supplied to the converter/4 converter (to), and a discrimination value is taken out which is 1# when the value X is large and O when it is small. Ru.

This discrimination value is supplied to the shift register register.

The AST pulse is supplied as a load pulse to Mayu's shift register, and a value of "100..." with only the pit at the input end set to 1" is supplied as a load value.
The inverted value X is supplied as a clock, and the above-mentioned discrimination value is taken in every 9 rises of this value X shown by G in the time chart. As a result, a signal is formed in the shift register in which the leading pit is set to "1" and thereafter the values of "1#" and "0" are sequentially provided to the end points of the line segment.

Furthermore, the inverted value or is supplied to the counter (c), and this value
When K is at a high potential, the above-mentioned clock is counted, and when the value K is at a low potential, the count value is cleared. This count value and the value of Cw latched in the latch circuit αυ are supplied to converter 4, and when the value is small, 1#
, a discrimination value of "O#" is taken out when the value is large.

This discrimination value is supplied to the D flip-flop (7) (3]). Also, AST II pulse D free lag flop 0
A comparison value This CKS no 9
A pulse is supplied to the clock terminal of the D flip-flop (7). Additionally, AEN/# is supplied to the clock terminal of the D-flop G.

As a result, in the D flip 70 (7), if the distance from the end of the point where the depth of the character part first becomes less than δ is smaller than Cw, it is '1'', and when it is greater than Cw, it is 0''. The value of is retained. In addition, the distance from the last point where the depth of the character part became less than δ to the end of the D flip-flop 0η is C.
When W is smaller, the value is 1", and when it is larger, the value is NO#.

The signals of these D flip-flops 0001) and shift registers are sequentially output to the data bus αυ under control from the CPU, thereby forming a code based on the above-mentioned irregular characteristics. Note that the shift register is read from the input end side. For this reason, the reading order of the memory 4 is adjusted so that each pit of the code is in a predetermined order. Further, the values of δ, Cw, and WTH can be changed arbitrarily by determining the state of the output code.

Further, FIG. 6 shows a configuration for identifying major classifications from the four-turn code of input characters formed as described above.

In this figure, the formed code on each side is connected to a code register [CR] through a data bus (not shown).
(41A) to (41D). Codes from these code registers (41A) to (41D) are supplied to address circuits (42A) to (42D), respectively.
As a result, respective predetermined addresses of ROMs (43A) to (43D) are read out. Here ROM (43
A) to (43D) are the ROMs (48A) to (4
8D) and the number M1 of characters included in that classification are stored.

The addresses of the first characters from this ROM (43A) to (43D) are stored in registers (44A) to (44D), respectively.
Address counter [AC] (45A) ~ (45
D) and ROM (43A) to (43
The number of characters M1 from D) is the member counter (MC) (
46A) to (46D). Then, the addresses from the address counters (45A) to (45D) are supplied to the address circuits (47A) to (47D), respectively, and thereby the first kanji of the characters classified by the code in the ROM (48A) to (48D), respectively. The code is read. Signals from these ROMs (48A) to (48C) are supplied to dart circuits (49A) to (49C), and signals from ROMs (48B) to (48D) are supplied to dart circuits (50B) to (50D). Supplied.

On the other hand, a signal indicating the identification mode, which will be described later, from the data path is supplied to the mode register (MRI051>), and a signal from this mode register (2) is supplied to the ROM (4).As a result, from the ROM 6, for example, QO ratio output A side, Q output, B side to output, 0 side to Q2 output, D side to Q3 output, end code signal to Q4 output.These codes are composed of 2 bits, of which Since the A-side code never appears in Q, to Q4, the A-side code and the end code are configured the same.

Q of this ROM (transformation). The output is fed to the selector acid,
Q, ~Q4 outputs are provided to a shift register.

Then, a timing signal ST, which will be described later, is supplied to the shift register ■ through an AND circuit, and the signals from the Q1 to Q4 outputs mentioned above are loaded, and at the same time, the output of the AND circuit is supplied to the selector Kasumi through an inverter So. , during which the QO output is selected.

The output of this selector and the first output of shift register (2) are supplied to the selector. The signal from the inverter is then supplied to the selector through the OR circuit.
Q from selector Q during this signal plane. Output is selected. The signal from this selector (b) is supplied to the D flip-flop (to) and delayed by one clock period.

The signal from this flip flora f(to) is fed back to the selector acid and is also supplied to the decoder/[1131],
Decoding is performed corresponding to the above-mentioned sides A to C, respectively. Also, the signal from the shift register (b) is sent to the decoder 6.
2 as K is supplied, and decoding corresponding to the above-mentioned sides B to D is performed. Then, the signal from the decoder O◇- is transmitted to the dart circuits (49A) to (49C) and (50
B) to (50D).

f-) circuits (49A) to (50
The signal from D) is supplied to the comparator, and when the kanji code from e-) circuits (49A) to (49C) is small, the comparison output passes through the OR circuit (to) to the selector (
goods).

Therefore, for example, from the ROM wire's Q output to the A side, Q, ~Q
When the end signal is output from the B-D side from the 3rd output and the □Q4 output, Q is first outputted from the timing signal ST.

The output is supplied to D flip flop ■ through selector e4@, and the next clock signal causes Q. The output is output from the D flip-flop (a), and the shift register (
Q, output is taken from (b). This signal is supplied to the decoder section η branch, thereby opening the dart circuits (49A) and (50B). And at this time, ROM (4
If the kanji code from 8A) is small, selector (goods)
The signal from the selector acid is selected at , and the signal from the D flip-flop is selected in this selector acid.
Also, when the kanji code from the ROM (48B) is small, the signal from the shift register is selected by the selector s'iI, so that the signal on the side with the small kanji code is always taken out from the selector Oka. be done. Then, with the next clock signal, the signal from the selector is output from the D-flip defroster ff4, and the Q2 output is taken out from the shift register (b).

Furthermore, the f-) circuit (49A) to (
A signal indicating that the kanji code from r-) is small is supplied to the decoder enable terminal through the Noah circuit -, and a signal indicating that the kanji code is small from r-) circuits (50B) to (50D) is supplied to the decoder enable terminal through the Noah circuit. A signal is supplied to the enable terminal of the decoder through the circuit (to), and a signal indicating that the Kanji codes are equal is supplied to the NOR circuit-1. The signal A corresponding to the A side of this decoder is the inverter (67A)
The signal B corresponding to the B side of the decoder ring is supplied to the OR circuit (68B) through the NAND circuit (67B), and the signal C corresponding to the 0 side of the decoder is supplied to the NAND circuit. (67C) to the OR circuit (68C), and the corresponding signal on the D side of the decoder Q passes through the inverter (67D) to the OR circuit (68C).
8D). This OR circuit (68A) ~ (68
A signal from D) is supplied to a latch circuit driven every clock. Furthermore, this latch output is supplied to AND circuits (70A) to (70D), and a signal from the comparator indicating that the kanji codes are equal is supplied to AND circuits (70A) to (70D). Signals from these AND circuits (70A) to (70D) are supplied to OR circuits (68A) to (68D).

Because of this, the latch circuit sets the bit on the smaller side of the Kanji code compared at every clock as 1'', and when the Kanji codes match, the bit on both sides becomes 1#, Further, the bits on the side that were 1'' in the previous clock are fed back through AND circuits (70A) to (70D), and the bits on all sides that matched the minimum Kanji code up to that point are set to 1''.

This operation is repeated for each clock for the outputs Q, -Q3 shifted by the shift register (b).

Then, when the end code signal appears at the output terminal one before the output terminal to the selector (goods), this signal is transmitted to the decoder (2
), and AND circuits (71A) to (710)
K is supplied. As a result, the OR circuit (68A) to (6
The signal corresponding to the side of the smallest kanji code from 8D) is taken out from the AND circuits (71A) to (71D), and this signal is sent to the address counter (45A) of the corresponding side.
~(45D) and member counter (46A) ~(46
D) is supplied to the enable terminal of D), and is advanced by '1' at the next clock.

In addition, the signal from the decoder is supplied to the D flip 70 block (c), and the signal taken out to the η output at the next clock is supplied to the AND circuit (to), and the signal from the ROM @ is sent to the shift register. , ~Q4 output is loaded and the selector branch is Q. It is switched to the output side and the above operation is repeated.

Further, when all the bits in the latch circuit become 1'', this is detected by the decoder Q4, and this detection signal is supplied to the D flip 70.
The Q output of (to) is delayed by one clock by the D flip-flop clock Q and supplied to the D flip-flop (75), and the signals from the D flip-flop gates 75 and 75 are supplied to the data bus.

In addition, signals from the dirt circuits (49A) to (49C) are supplied to the latch circuit (c), and this latch circuit (
5) is driven by the signal from the D flip 70f (c), and the signal from this latch circuit is supplied to the data bus.

As a result, when the signal of the D flip-flop (c) is 1', the kanji code that matches on all four sides is latched in the latch circuit n, and this kanji code is transferred to the CPU (not shown) through the data bus. can be included.

When the kanji codes on the four sides match, the OR circuit (6
The outputs of 8A) to (68D) are all 1#, and the address counters (45A) to (45D) and member counters (46A) to (46D) are all advanced by '1', and the above operation is repeated. This allows a plurality of broadly classified Kanji codes to be imported into CPH.

Further, the number of kanji codes that have been identified on each side is counted by member counters (46A) to (46D), and it is detected when this number reaches the number Ml from ROMs (43A) to (43D). This is for example a member counter (
46A) to (46D) are loaded with one's complement for Ml in advance, and the AND circuits (71A) to (71
By adding "1" for each enable signal from D), it is detected that the contents of the member counters (46A) to (46D) all become '1#'. This detection signal is supplied to D flip-flops (78A) to (78D), and their outputs are supplied to the 100 terminal of the SR flip-flop (2) through an AND circuit (7It).

As a result, when all the Kanji codes on any one side have been identified, the SR flip-flop feO is set, and the Q output of and is supplied to the data bus as an identification end signal.

The output from the fcSR71J block is supplied to the clear terminals of member counters (46A) to (46D).

Furthermore, the output of the AND circuit 17I is supplied to the terminal of the SR flip-flop 6p. Further, an identification operation start signal from a data bus or the like is supplied to the S terminal of the SR flip-flop 6η, and its Q output is supplied to the input terminal of the shift register (to). And this shift register (a)
By being driven by the clock, a signal that becomes 1" continuously from the next clock when the Q output of the SR fritz defrot f6υ becomes 1" is taken out from this output, and this signal is sent to the register (44A) ~ (44D).

In addition, the B output of the shift register (B) is supplied to the Inno Kai-Yu ■, and this inverted output and the human output are connected to the NAND circuit (B).
supplied to As a result, S from the Nando circuit (goods)
The next 1 when the Q output of R frig float de 6υ becomes 1'
A timing signal plane that becomes 'O' only during the clock period is taken out, and this signal plane is supplied to the above-mentioned AND circuit □□□, and the address counters (45A) to (45D),
It is supplied to the load terminals of member counters (46A) to (46D), and further supplied to the clear terminal of the latch circuit.

Furthermore, a clear signal from the data bus etc. is supplied to the i terminal of the SR flip-flop (2) and the clear terminal of the D flip-flop (to).

Therefore, in the above-mentioned device, the address counters (45A) to (45D), member counters (46A) to (46D), and shift registers (46D) and shift registers (45A) to (45D) and the shift register (46D) are ) is loaded with an arbitrary signal and the identification operation is started.

In this way, the kanji code common to the four sides is identified based on the code obtained from the peripheral features, and the kanji can then be identified and specified by medium classification or small classification using any method.

By the way, in the above-mentioned device, after the identification operation is completed, the SR
Even if the end signal is output from the 7 lip-flop ■, there may be a case where no kanji code has been identified in the operation up to that point. In that case, it is possible that one of the four detected codes is incorrect. In that case, the above-mentioned device can perform the identification operation while removing one of the four sides one by one.

That is, in the above-mentioned device, by setting a predetermined identification mode in the drain resistor, the ROM 6B outputs codes corresponding to the four sides as shown below.

As a result, it is possible to perform identification in which one side is removed one after another. At this time, the mode is switched so that all 1'' are decoded with the decoder ♦ except for that one side.

Furthermore, this identification can also be performed excluding any two sides.

In addition, it is possible that noise is mixed into the input character pattern, but in that case, ROM (
Effects of the OH invention that can be solved by including them in the kanji code of 48A) to (48D) , there is less risk that the classification will be affected by fluctuations in the input 14 turns, and the classification rate can be greatly improved, especially when applied to large classifications when performing classification by dividing into multiple layers. .

[Brief explanation of drawings]

Figures 1 to 3 are diagrams for detailed explanation of the present invention;
6 to 6 are diagrams for explaining a rounding device that implements the method. (1m) to (1d) are circumscribing frames.

Claims (1)

[Claims] For an input character pattern cut out one character at a time, the shape of a portion of the input character pattern that is in contact with a circumscribing frame is detected, the detected shape is encoded, and the encoded shape is A character identification method that identifies the input character pattern based on data.