JPS62185279A - Data recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain a recording and reproducing device of binary data that has optimum error-correcting function with shortest interleave by obtaining the interleave constitution of shortest interleave length by means of analytic method using a state-transition probability. CONSTITUTION:By using the state transition probability which is an output from a state transition probability calculating circuit with synthetic Gilbert model 1 inputted to itself, a frame error calculating circuit 2 obtains an Erdm at the time when symbol errors are at complete random. By using the same input, a circuit 3 obtains the occurrence-probability of a frame that includes one symbol error (Eint). In an interleaving efficiency calculating circuit 4, the interleave efficiency eta which is the value of Eint/Erdm is calculated. By using the interleave efficiency eta as an input, an optimum interleave length calculating circuit 5 calculates the smallest value of an interleave distance lopt that makes the eta come to be a prescribed value etamax, and outputs this lopt to an address generating circuit 6. As a result, the interleave can be applied with the shortest interleave length to obtain an optimum error correcting capability. Therefore, a recording and reproducing device excellent in cost-performance can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a binary data recording/reproducing device. More specifically, the present invention relates to a recording and reproducing apparatus that converts the order of an original information data string to the order of another recording data string and records the same.

[Conventional technology]

Conventionally, error correction codes (hereinafter abbreviated as FCC) have been used in magnetic recording devices such as magnetic disk devices and magnetic tape devices, or optical recording devices such as digital audio disks, to improve data reliability. . When using this FCC, it is known that addressing is performed with memory in an increment configuration for the purpose of improving error counting ability by avoiding bursty errors. The advantage of this interleaving is that long burst errors can also be effectively corrected by using a type of ECC that can effectively correct only random errors.

[Problem that the invention seeks to solve]

However, conventional interleaving configurations are not determined with sufficient consideration given to the bit error characteristics of the recording medium, but are simply determined by trial and error based mainly on the code word, sector or section capacity, etc. of the FCC being used. It was something that

Therefore, the interleave length is often too small or too long, resulting in a problem of a large amount of cost and time being spent until the desired characteristics are obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a binary data recording and reproducing apparatus having the shortest interleaving and maximum error correction capability using an interleaving configuration that has been analytically determined in advance in order to solve the above-mentioned conventional problems. be.

[Means and operations for solving the problem] The present invention calculates transition probabilities M (M≧4) between each state of an N-state (N22) model that expresses the bit error generation process from bit error characteristic data of a recording medium. ), means for calculating a frame rate (Erdm) in which a frame consisting of n symbols includes one or more error symbols when symbol errors are completely random, from the transition probability between the states; Means for calculating a frame error rate (Eint) in which a frame interleaved with distance Q symbols includes one error symbol from the interleaving probability when symbol errors are non-random, and the ratio of the Erdm and Eint. A means for calculating interleaving efficiency and a shortest interleaving length (Q op
t). Then, interleaving is performed by addressing a random access memory (RAM) that temporarily stores binary data at intervals of the calculated shortest interleaving length (Q opt), and by this addressing, the binary data output from the RAM is Data is sequentially recorded on a recording medium.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Actual state of bit error distribution FIG. 2 is an actual measurement example of the bit error distribution of an optical disk medium, that is, the relationship between the length of consecutive bits and the number thereof. The number of bit errors on the vertical axis is expressed as a number of times. It is generally known that in optical disk media, as shown in FIG. 2, there are relatively many short bit errors, and there are also a small number of very long bit errors. As shown by the broken line in FIG. 2, this bit error distribution has short bit error parts and long bit error parts separated by straight lines Q with different slopes, respectively.
It can be seen that it can be approximated by R.

Circuit Structure Figure 1 is a block diagram of one embodiment of the present invention, and shows a block diagram for calculating the optimum interleaving length Q opt from the bit error distribution of the optical disk medium and performing interleaving based on the Q opt. It shows. In Figure 1, 1
is a circuit for calculating the transition probability between states of the composite Gilbert model, 2
3 is a circuit for calculating the frame error rate when symbol errors are completely random, 3 is a circuit for calculating the probability of occurrence of a frame containing one symbol error when interleaving is performed when symbol errors are non-random, 4 is a circuit for calculating interleaving efficiency, and 5 is the optimal circuit. 5 is an address generation circuit, 7 is a RAM, 8 is an ECC circuit, and 9 is a recording circuit.

10 is an optical disk medium. In addition, in the following explanation,
The transition probability between states is expressed as state transition probability.

The input of the synthetic Gilbert model state transition probability calculation circuit 1 shown in FIG. 1 is a data group of bit error distribution curves of an optical disk medium, and the output is seven state transition probability values. The internal calculations of the state transition probability calculation circuit 1 will be explained below with reference to FIGS. 3 and 4.

First, the Gilbert model will be explained. FIG. 3 shows a state transition diagram of two mutually independent Gilbert models. Regarding the Gilbert model.

For example, Be1l Sys, Tech, published in 1960.
, J*Vo1.39, PP, 1253-1266
is described in detail. 3(a) is a Gilbert model expressing the bit error generation process shown by the straight line Q in FIG. 2, and FIG. 3(b) by the straight line R in FIG. 2.

In addition, in states Bs and BIl, the bit accuracy is 1-h, respectively.
, h. The stationary probability, which is the probability of existing in a certain state at any given time, is expressed as follows.

X > = qz x / (q□2+92□) (1)
Xz=qyo2/ (q12+92□)(2)y□=r1
□/(r□2 + r'zt)
(3)'/z = r□2/(r□2+r2□)
(4) In each model in Figure 3, the probability that i bits are continuously in state Bs or B is P q (i) = P
r(i) is derived as follows using equations (1) and (3).

Pq (1)”)h “lxz” qzx’−””
q2L ” (1h)” (5)Pr (
i)=yt'rtz'r22'-"rzt
” (1-h)' (6) Next, 2 in Figure 3
Consider a linear combination of Gilbert models. At this time, in each model in FIG. 3, the probability that one bit is continuously in state Bs or B is Pq (i), Pr
The probability P(i) obtained by linearly combining (i) with an arbitrary coupling constant k (0≦to≦1) is as follows.

P(, L) = −Pq (i) + (1k)・■ given (
i) qtz+qtz r12+r2
First, using the Gilbert model in Figure 3(a) as an example,
The procedure for obtaining the state transition probability from the bit error distribution etc. will be explained. The value of (1-h) is the ratio of bit "1" to bit "0" of the recording information. Normally, it is assumed that the probability of occurrence of bit "1" and bit 110 I+ is equal, and (1-h)
is set to 0.5. First, it is clear that 92□ can be found from the ratio of the probability of occurrence of j bit errors and (j+1) bit errors using equation (5). q21 is equal to (1'lz□). Next, q1□ is given by the following equation, which is a modification of equation (2).

q□2=x2・q z/ (t-(121)
(s) iday, x2 is the bit error rate (
1-h). Also, q2□ is (1-9□
2).

In this way, from the bit error distribution and bit error rate,
The state transition probability of the Gilbert model shown in FIG. 3(a) can be calculated. Similarly, the state transition probability of the Gilbert model shown in FIG. 3(b) can also be calculated.

Next, the synthetic Gilbert model will be explained.

FIG. 4 is a state transition diagram of a mathematical model obtained by linearly combining two known Gilbert models. In this case, this model will be referred to as a composite Gilbert model. State G is a state in which fixed bit errors due to defective portions on the recording medium do not occur.

Furthermore, even in state G, it is assumed that intermittent bit errors occur with a probability of (1-s) due to equipment noise or the like. In addition, state BS is a state in which a fixed short bit error appears to have occurred due to the small defect above, and state B is a state in which a fixed long bit error has apparently occurred due to the large defect above. state. Pi 1~ in these states BS, B
Let the error rate be (ih).

As a representation of the transition probability between states, from state G to state G again
Let the probability of transition to p 1. Let the probability of transition from state G to state B5 be p1□, etc. This is expressed as a matrix for ease of notation. The probability of transition from each state to the same state is placed in the first row of the matrix for state G, the second row for state B, and the third row for state B5. As a result, the state transition probability transition matrix P of this model is given by the following equation.

With this notation, as shown in equation (25).

From the state transition probability obtained by multiplying the transition probability after an arbitrary bit by the power of the matrix P, the stationary probability representing the probability of existing in a certain state at an arbitrary time t is expressed as follows. Ru.

t1= P x□p3□/Δ
(10)jz=Pt□p31/Δ
(11) ti=ptaPat/Δ
(12) However, Δ=P21p3L
+P engineering ZP3L + P engineering 3P2 □In this composite Gilbert model, the probability P that i bits will be in the state B3 or B continuously (i) is the following formula % formula %: 1) The state transition probability of the composite Gilbert model is as follows. calculate. At knee, a model obtained by linearly combining two independent Gilbert models is equivalent to a composite Gilbert model. For this purpose, equations (7) and (13) need to hold true. Accordingly, the following identity is derived.

pllEl (kXtptzqztrzx+(1k)
3'1rizrzt'TJ/rp1□=l(x1q12
q21 rzt/T” (1
5) Pxz= (1k) 3't r tz ri1q
zt/r' (16) Pz1='h
t (17) p2
□MiP2□
(18) P3t=r2m
(19) In this N, I'=qzzrzx kXt'Ttzrzx (l
k) yt'Tztrtz (21) Therefore, real i! If we know each state transition probability of the two basic Gilbert models from the +11 error distribution,
By using the identities of equations (14) to (20), 2
It is possible to calculate the state transition probability of a composite Gilbert model that satisfies both conditions.

As described above, the internal calculations of the state transition probability calculation circuit 1 of the composite Gilbert model shown in FIG. 1 are performed.

The fact that this model is a mathematical model that can accurately describe the bit error distribution of optical disk media as shown in Figure 2 has already been proven in the 1981 Ichiko Communication Society General Conference Lecture Proceedings. It is indicated by number 1760 of separate volume 7. The procedure for calculating the optimum interleave length by an analytical method in circuits 2 to 5 in FIG. 1 will be described below using the state transition probabilities that are the calculation results of the state transition probability calculation circuit 1 of the 1-synthesis Gilbert model.

Typical Interleaving Configuration Example FIG. 5 schematically represents a typical example of an interleaving configuration to which the present invention is applied. FIG. 5(a) shows the logical arrangement of data, and FIG. 5(b) shows the physical arrangement of data on the recording medium. These are depicted with symbols consisting of h bits as trophies. The addition of the FCC is
This is done in the row direction in FIG. 5(a). That is, the FCC code word is formed from n symbols obtained by adding the FCC check word (n-k) symbols to the original information symbol.

This is called a frame. Note that what kind of FCC to add is not a subject of the present invention.

Further, a column is composed of n symbols. The recording order on the recording medium is as indicated by the arrows, from the first column upper symbols to the lower symbols, and from the second column upper symbols to the lower symbols. In FIG. 5(b), it is shown that the FCC code words shown in FIG. 5(a) are arranged on the recording medium at intervals of n symbols in length due to interleaving. The method of determining the optimal value of this length is the core of the present invention,
The circuits 2 to 5 in FIG. 1 will be described in detail below.

When interleaving as shown in Fig. 5 is performed in a device using an optical disk medium with the bit error distribution shown in Fig. 2, the interleaving rate is calculated using the state transition probability to obtain the maximum error accounting ability. An analytical method for obtaining an interleaving configuration with the shortest interleaving length will be explained.

First, as a premise, the effect of correcting burst errors by interleaving will be evaluated using a quantity called interleaving efficiency η, which is defined linearly. That is, the interleaving efficiency η
is defined as the ratio of the probability of symbol error occurrence (Erdm) when errors occur completely at random to the probability of occurrence of a frame containing one or more symbol errors (Eint) when interleaving is performed at a distance of n symbols. In this case, the interleaving efficiency η is expressed by the following formula.

That is, the interleaving efficiency is evaluated using an index that indicates how much apparent symbol errors are randomized by interleaving. Note that η defined by N can be said to be the most severe evaluation index since it focuses on a frame containing one symbol error after interleaving.

Frame error rate when symbol errors are completely random This is determined by the Frake error calculation circuit 2 when symbol errors are completely random, using as input the state transition probability which is the output of the state transition probability calculation circuit 1 of the composite Gilbert model.

When the occurrence of errors can be considered completely random, the frame rate containing symbol errors (E rdm) is:
Letting the symbol error rate be pl, it is given by the following equation using the binomial distribution.

i=l n i The frame error calculation circuit 2 executes the calculation of the above equation (23) when the symbol error is completely random, and sends the calculation result Erdn+ to the interleaving efficiency calculation circuit 4.

The time required to produce one symbol after interleaving λtr7Lz--This is calculated by the occurrence probability calculation circuit 3 of a frame containing one symbol error when interleaving is performed when the symbol error is non-random, using the state transition probability as input.

First, when performing distance Q symbol interleaving, the probability of occurrence of a frame containing one symbol error (Eint) is determined by Peg, which is the probability that one of the symbols at both ends of the frame will be a symbol error, and If the probability of symbol error is Pmd, Eint=2Peg+ (n-2) Pmd
It is expressed as (24). Peg on the right side of the above equation
+P md is calculated by the following analytical method. That is,
In the composite Gilbert model, the state transition probability matrix Pk after k bits is as follows.

The notation of the transition probability when the state transitions as follows after an arbitrary bit is shown below.

Next, the expression of the conditional probability that the state transitions from the first bit to the b-th bit in a symbol as shown below and that no bit error occurs in the symbol is shown below.

These conditional probabilities are each expressed by the following equations.

+s'-P11'-1(26)Ngs=(s
Pil)' ” (plz ri/ p1□Pzz)
(27) Ngl” (S PJ'
” (fha ri/Put P33)
(28) Nsg= (s Pll)” (Pz
trz/ Pll Pll) (2
9) Nss=h'p 0'-'

(30) N1g= (s Pz,)' ” (Pzx
r'i/Ptz P33) (31
)N11=h”p,,b-'
(:32) Here, rt=hPzz/ S Pxx
(33) rz=h P33/
B fht
(34) r,: (rl-r, b) / (1-r,
) (35).

Using the above state transition variables, if the probability that one of the symbols at both ends of the frame becomes a symbol error is expressed as Peg, and the probability that symbols other than the symbols at both ends of the frame become a symbol error is expressed as Pmd, then b −1 = x.

b　(Q-1)+l=y, the following equation is obtained.

Pag= (Tgg −Ngg)”−2−(tt(Tg
g(x)-Ngg)4gg(y)・Ngg+t1(Tg
s(x)-Ngs) ・Tgs(y) ・Ngg+t1
(Tgl(x)-Ngl) ・Tgl(y) ・Ngg
10tz(Tsg(x)-Nsg) ・Tgg(y) ・
Ngg+t2(Tss(x)-Nsg)°Tsg(y)
ONgg+t3(Tlg(X)-N1g) 4gg(y
) ・Ngg tent, (Tll(x) N1g) ・T
lg(y) ・Ngg ) (36) Pmd= (
ttNgg) ・(Tgg(y))"-'CTgg(y
)(Tgg(x)-Ngg) ・Tgg(y) ・Nf
Cg + Tgg (y) (Tgs (x) Ngs) ・T
gs(y) fistNgg+Tgg(y)(Tgl(x)-
Ngl) ・Tgl(y) ・Ngg+Tgs(y)(
Tsg(x)-Nsg) ・Tgg(y) ・Ngg+
Tsg(y)(Tss(x)-Nsg) ・Tsg(y
) ・Ngg+Tgl(y)(Tlg(x)-'N1g
) ・Tgg(y) ・Ngg+Tgl(y)(Tll
(x)-N1g) ・Tlg(y) ・Ngg)
(37) Equation (36), the result of Equation (37) is expressed as Equation (24)
By substituting , the probability of occurrence of a frame containing one symbol error (Eint) when interleaving of length Q symbols is performed can be obtained. The circuit 3 sends E int, which is the result of this calculation, to the interleaving efficiency calculation circuit 4.

Calculation of interleaving efficiency η In the interleaving efficiency calculation circuit 4, the circuit 2,
The frame error rate (E rdm) in which the error occurrence is completely random calculated in step 3, and the frame occurrence probability (E rdm) in which only one symbol error occurs when interleaving of length Q symbols is applied.
E int) as input, the ratio E int / E
The interleaving efficiency η, which is rdm, is calculated and sent to the optimum interleaving length calculation circuit 5.

Optimum interleaving distance, apt, -output optimal interleaving length calculation circuit 5 receives interleaving efficiency η as input and calculates the minimum interleaving distance 1i1tQopt at which η becomes a predetermined value ηmaX.

Specifically, when η calculated for a certain Q is more or less than ηwax, which is known by numerical calculation method, Q is increased or decreased, and Eint is re-interleaved by one symbol when the symbol error is non-random. Q apt is obtained by repeating the method of calculation by the error-containing frame occurrence probability calculation circuit 3. As a result of the calculation, the relationship between interleaving efficiency η and interleaving length Q is obtained as shown in FIG.

As described above, the optimum interleave length calculation circuit 5
A value Q opt for realizing the interleaving configuration necessary to obtain the maximum error correction ability is calculated by a combination of analytical method and numerical calculation method, and this Q opt is output to the address generation circuit 6. .

Actual interleaving by QOρt The RAM 7 in FIG.
The system data is accumulated. The RAM 7 is addressed by the address generation circuit 6 for each Q opt symbol, which is the optimum interleaving length.

Each time, the binary data outputted from the RAM 7 is sequentially outputted to the recording circuit 9. Recording circuit 9 is input 2
The value data is appropriately modulated and recorded on the optical disk medium 10. Note that the RAM 7 is a random access memory such as a semiconductor memory.

[Other Examples]

In the above embodiment, in order to obtain the optimal interleaving length, several types of operations are executed in separate circuits in a time-series manner, but one circuit that can execute all operations, for example, a so-called micro Executed with one processor, calculation result Q
It goes without saying that it is a practical configuration to send only opt to the address generation circuit 6.

In addition, the optimal interleave length Q opt can be used to increase the interleave length Q beyond Q opt to increase the bit error rate due to aging of the recording medium or increase the intermittent bit error rate due to induced noise, etc. It is also possible to have a margin in the error correction capability for etc.

It goes without saying that the bit error characteristic data of the recording medium can also be obtained as device internal information based on the operating state of the FCC circuit of the recording/reproducing device itself.

Furthermore, it is clear that similar effects can be obtained by using a model that is a linear combination of three or more Kilbert models.

Although the embodiments have been described above with reference to an optical disk device, it is clear that the present invention can be applied to various other optical recording devices and magnetic recording devices such as magnetic disk devices and magnetic tape devices.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to perform interleaving with the shortest interleaving length to obtain the maximum error correction capability, so a recording/reproducing apparatus with good cost performance can be realized.

Furthermore, by measuring the bit error characteristics of the recording medium after deterioration through accelerated deterioration tests, etc., and storing the obtained bit error characteristics data in a separate means, we can create an interleave configuration suitable for the bit error characteristics after deterioration over time. It is also possible to realize this, which is highly effective in effectively extending the life of the recording medium.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing a bit error distribution of an optical disk medium. Figure 3 is a state transition diagram of two mutually independent Gilbert models, Figure 4 is a state transition diagram of a composite Gilbert model, Figure 5 is a typical interleaving configuration diagram, and Figure 6 is a diagram of interleaving efficiency and interleaving length. It is a relationship diagram. 1... State transition probability calculation circuit for a composite Kilbert model, 2... Frame error rate calculation circuit when symbol errors are completely random, 3... One symbol when interleaving is performed when symbol errors are non-random. Error-containing frame occurrence rate calculation circuit, 4. Interleaving efficiency calculation circuit, 5. Optimum interleaving length calculation circuit, 6. Address generation circuit, 7. RAM. 8...FCC circuit, 9...recording circuit, 10...
Optical disc media. One representative patent attorney: Makoto Suzuki, °ko)ζ- Figure 1 P, To Matsuri& (bat) Figure 3 (b) Figure 4 N-11) Figure 5 (α) Cb) 6 Figure 1 (Shish end, lsu)

Claims (1)

[Claims] (1) In a recording/reproducing device having a random access memory (RAM) that temporarily stores binary data, and a recording medium that sequentially records the binary data read from the RAM,
Means for calculating each inter-state transition probability (M≧4) of an N-state (N≧2) model expressing a bit error generation process from the bit error characteristic data of the recording medium, and a means for calculating a symbol error from the inter-state transition probability. Means for calculating a frame error rate (Rrdm) in which a frame consisting of n symbols includes one or more error symbols when is completely random, and a distance l symbol when symbol errors are non-random from the inter-state transition probability. The frame error rate (Eint
); means for calculating interleaving efficiency, which is the ratio of Eedm and Eint; and means for calculating the shortest interleaving length (lopt) that makes the interleaving efficiency equal to or greater than a predetermined value; 1. A binary data recording/reproducing device characterized in that interleaving is performed by addressing the RAM every 1.0 lopts, and binary data outputted from the RAM by the addressing is sequentially recorded on a recording medium.