JPS62179041A - Address setting circuit - Google Patents

Abstract

PURPOSE:To hold the universality of a circuit, and to easily utilize it for other purposes by constituting the circuit so that a series of addresses can be supplied continuously by providing and cascade-connecting a light receiving circuit, an adder, a light emitting circuit, and a decoder. CONSTITUTION:An address setting circuit detects whether a light reception has been performed with light receiving circuits 11 and 12, and adds the output signals on signal lines 101 and 102 on an adder circuit 13, and after adding +1 with the adder circuit 13, it drives light emitting circuits 16 and 17. The output signals outputted from the light receiving circuits 11 and 12 on the signal lines 101 and 102 are decoded with a decoder 18, and address signals z1-z4 are generated on signal lines 181-184 corresponding to the signals on the signal lines 101 and 102. In this way, the address of a device can be set automatically, and the usage for other purposes can be easily performed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an address setting circuit for a plurality of floppy disk devices, magnetic disk devices, and magnetic tape devices.

(Prior Art) This conventional address setting circuit will be explained with reference to FIG. 5, taking a floppy disk as an example. Fifth
In the figure, 1 is a floppy disk device, and 51 is a friend floppy disk control device fl that controls the floppy disk device 11.

511 to 520 are control (IL+ signal lines). In the floppy disk device 11, 120 is a terminal board for address straps, 191 is an internal circuit, and 531 to 536 are
are each an inverter, and 541 to 544 are each NA
ND gates %555 and 556 are AN and D gates, respectively.

In FIG. 5, the floppy disk controller @(flo
ppy disk controller (F D
O): Hereinafter referred to as FDO. ) 51 and a floppy disk drive (
J'DD): Hereinafter referred to as FDD. ) 11 are connected by control signal lines 511 to 520. The control signal branch lines 511 to 541 are also common to all other connected FDDs.

When transmitting and receiving commands from the FDC 51, the configuration is such that the commands are transmitted and received between FDDs to which device addresses are specified, for example, FDD11 and F'D051, via control signal lines 511 to 520. Control (1! The line 511 selects the first FDD o=2, the control signal line 512 selects the second PDD, the control signal line 513 selects the third FDD, and the control signal line 514 selects the third FDD. Fourth FDDi selection 4Rf.

Control 5t4 + signal lines 515 to 520 are used for sending and receiving information, operation,
and state.

By connecting one of the control signal lines 511 to 514 on the strap terminal board 120, the corresponding F
D1) is selected. For example, if FDDII is selected, data is input to the internal circuit 19.

(Problems to be Solved by the Invention) In the conventional address setting circuit described above, for example, when installing an FDO device, strap work is required to connect the address signal line, and a jig is also required for the work. The disadvantage is that the address of the friend device is fixed no matter when it is needed or installed, so it lacks versatility and is difficult to use for other purposes.

An object of the present invention is to provide an FDDi device with a light emitting circuit and a light receiving circuit, so that the optical signal sent from one device can be received by another device, and the received optical signal is used to output an adder circuit. The above-mentioned drawbacks are eliminated by incrementing the address signal and decoding the received light signal as an address signal for the corresponding device.
It is an object of the present invention to provide a friend address setting circuit configured to have general versatility.

(Means for elaborating the problem tM) The address setting circuit according to the present invention includes a light receiving circuit, an adding circuit, a light emitting circuit, and a decoder, which are connected in cascade to continuously give a series of addresses. It is configured so that it can be done.

The light receiving circuit is for receiving an optical signal giving address information sent from another vctIL.

The adder circuit increments the address information obtained from the light receiving circuit by 1 to obtain second address information.

The light emitting circuit is for transmitting the second address information obtained by the addition result of the edge calculation circuit as an optical signal.

The decoder is a sophisticated device that decodes the address information obtained by the light receiving circuit to determine the address of its own device.

(’i! Example) Next, the present invention will be explained with reference to the drawings.

The FJWI diagram is a circuit diagram showing one embodiment of an address setting circuit according to the present invention. According to FIG. 1, the present invention includes a light receiving circuit 11.12 for receiving an element, an adding circuit J3,
Light emitting circuits 16 and 17 for emitting source light, and light receiving circuit 1
1.12, and a decoder 18 for decoding signals of 1.12.

In FIG. 1, the light receiving circuit 11 is constituted by a phototransistor 111 which operates in response to a phototransistor 111 and an emitter resistor 112 of the phototransistor 111. The adder circuit 13 includes a gX-OR gate 14 and an inverter 15. The light emitting circuit 16 is the adder circuit 1
A transistor 161 operated by a signal output from the EX-OR gate 14 of No. 3 and a transistor 161
62, a light emitting diode 163 connected to the collector of the transistor 161 for emitting light by the collector current, and an anode resistor 164 of the light emitting diode 163. Note that, like the light receiving circuit 11, the light receiving circuit 12 includes a transistor 121 and a resistor 122.
It is composed of. Mayu, like the light emitting circuit 16, the light emitting circuit 17 includes a transistor 171 and a base resistor 1.
72, light emitting diode 173, and anode resistor 174
It is composed of.

Next, the operation of the address setting circuit shown in FIG. 1 will be explained.

Assuming that there is no incident light on the light receiving circuits 11 and 12, the phototransistor 111 of the light receiving circuit 11 does not receive +' and is in an off state. Therefore, the phototransistor 11
The emitter direct voltage of 1 is equal to the common potential (GND). Similarly, the voltage of the phototransistor 121 of the light receiving circuit 12 is also equal to the common potential (GND). Therefore, the logic between the signal on the output signal line 101 of the light receiving circuit 11 and the signal on the output signal H102 of the light receiving circuit 12 is The level is υ′. The signals on the output signal lines 1 (11, 102) are input to the adder circuit 13 and the decoder 18.The adder circuit 13 inputs the signals on the input signal lines 1 (11, 102)
Add 1 and output. ′T, that is, EX −OR,
14 and an inverter 15 perform addition.

(!!!) on the output signal line 101 of the EX-OR gate 14
fx, and the output of the inverter 15 is 1! ! Assuming the signal ty on the g line 104, their truth values are as shown in Table 1 given at the end of the detailed description of the invention.

As is clear from the truth table i1, the output signal xly of the 1 addition circuit 13 is transmitted from the light receiving circuits 11 and 12 to the signal line 10.
This is the value obtained by adding +1 to the outputs sent to 1 and 102, respectively. When the signals on the cutting edge flaw segment lines 101 and 102 are both '1', a carry occurs, so the output signals x and y are both 'O'. The output value +;X+Y of the adder circuit 13 is guided to light emitting circuits 16 and 17. The light emitting circuits 17 and 18 emit light according to the logic level of the signal XeY.

For example, when the logic value of the signal X is 1'', the resistor 162t
-Through the base to transistor 161! fi flows, transistor 161 is turned on, and tfL, which is fixed by resistor 164, flows to light emitting diode 163 and emits light.

When the logic value of the signal X is ON, the transistor 161
Since no base current is supplied to the light emitting diode 163, it is in an off state and the light emitting diode 163 does not emit light.

That is, the light emitting circuits 16 and 17 emit light according to the logical value levels of the output signals x and y of the adding circuit 13. On the other hand, the signals @lul obtained from the light receiving circuits 11 and 12,
The output signal on 102 is input to decoder 18 and one of four states occurs. The output of the decoder 18 is Fi signal line 1 (address signal z1 on signal line 181 which outputs a logic value "1" when signals on Fi signal line 11 and 102 are both 'O').

The signal on the signal line 101 is @on and the signal line io
When the signal on z is 11", the logical value "'1" is sent to signal line 1.
and address signal z2 output on 82.

The signal on the signal line 101 is '1'' and the signal on the signal line 102
The address signal z3 on the signal line 183 that outputs the logical value @1 when the upper signal is “ON” and the signal lines 101 and 1
There is an address signal z4 on signal line 184 that outputs a logical value ``1#'' when both signals on 02 are 1''.

That is, the address setting circuit detects whether or not light is received by the light receiving circuits 11 and 12, and connects the signal lines 101 and 1 (
The output signal on 12 is added to the adder circuit 13, and the adder circuit 13
After adding +1, the light emitting circuit 16.17t- is driven. Light receiving circuit 11. Signal lines 101, 10 from L2
The decoder 18 decodes the output value Ji837 onto the signal lines 181-184 in response to the signals on the signal lines 101 and 102. 1-Z4 occurs.

Next, an embodiment in which the address setting circuit of the present invention is applied to a floppy disk device will be described.

FIG. 2 is a block diagram showing the connection between a plurality of FDDs and an FDO for controlling FDD1. In FIG. 2, 1 is the first FD whose device address is set to 1.
D, z are the second FDs whose device address is set to 2
D, 3 is the third PD whose device address is set to 3
D.

4 is the fourth FDD whose device address is set to 4;
5 is FDO. FDO5 and each FDD1~4
are connected by control signal lines 511 to 520. The control signal lines 511 to 520 are common to all FDDKs, and when commands are transmitted and received from the FDC 5, a specific FDD designated by the device address executes the transmission and reception.

FIG. 3 shows details of the control signal line and a block diagram of an FDD constructed by applying an address setting circuit. In FIG. 3, 1 indicates the entire first FDD, 5 indicates the FDOi
show. Control signal lines 511 to 520 are a signal line 511 for selecting the first FDDt among the four FTs)D,
Signal line 512 for selecting second 1'i'DD Z
and a refined signal line 513 for selecting the third FDD 3,
It is composed of a signal line 514 for selecting the fourth FDD and signal lines 515 to 520. Signal line 51
5 to 520 are used for transmitting and receiving information between the FDC 5 and the FDDs 1 to 4, giving operation instructions, and displaying status. Signal lines 515 to 52θ become valid when one of the FDD selection signals on signal lines 511 to 514 becomes valid.

The first FDDl includes an address setting circuit 10, inverters 531-536 which receive control signals 16 from FDO5 via signal lines 511-516'i, and signal lines 517-520.
Open collector type NAND gates 541 to 544 for sending control signals through t, an address setting circuit 1o, and an address signal zl from the address setting circuit 1o.
-24 and the output of inverters 531 to 534 and '1AND
AND gates 551 to 554 to OR gates 551 to 554, an OR gate 557 to OR the outputs of the AND gates 551 to 554, and the output of the OR gate 557 and the inverter
, 536 output and IAND gate 5
55, 556, and an internal circuit 19 of PI')Dl.

FIG. 4 is an explanatory diagram showing the implementation of F'DDs 1 to 4.

In FIG. 4, 1 is the first Ii'DD.

2 is the second FDD, 3 is the third FDD, 4 is the fourth Jl
"DD, 111, 121, 211, 221
, 311, 321° 411 and 421 are phototransistors % 163° 173 and 263.273, respectively.
363, 373, 463, and 473 are light emitting diodes, respectively.

The important point here is that, as is clear from Figure 4,
- The transistors are arranged so that they each receive light from the light emitting diode adjacent to the left. For example, the second
The phototransistor 211 of the FDD2 is the first FDDI
is arranged to receive the base of the light emitting diode 163. In this arrangement, the address signal of the FDD is not received by the phototransistors 111 and 121 in the first FDDl because no FDD is placed next to them. Therefore, the phototransistor 111,
121 are both turned off. That is, the output logic values of the light receiving circuits 11 and 12 shown in FIG. 1
The light emitting diode 163 emits all light and the light emitting diode 173 receives light through the light receiving circuits 16 and 17.

Therefore, the phototransistor 121 of the second F'DD 2
is off, and the phototransistor 221 is on.

At this time, the logical values become "0" and "1", respectively. The address signal z2 becomes active and the adder circuit 13 increments the address value by +1, so the light emitting circuit 1
The light emitting diodes 263 of 6 and 17 emit light, and the light emitting diode 273 does not emit light. This relationship is shown in Table 2 given at the end of the detailed description of the first invention.

The address signals 11 to Z4 of the address setting port wr10 shown in FIG.
2, the logic value of z2 becomes 23, and the logic value of z4 becomes 1' in the fourth FDD4, and the FDO5 selected
'AND logic is performed with DD to set the address.

In this embodiment, four devices are described, but in the case of two devices, only one light receiving circuit and one light emitting circuit are required.
In the case of 8 machines, 3 are required. If this embodiment is further developed, the optical transmission lines shown by the arrows between the FDDs in FIG. 4 can be connected using original fiber cables. Even if the distance between devices configured in this manner is long, it is possible to reduce loss.

(Effects of the Invention) As explained above, the present invention includes a light emitting circuit and a light receiving circuit in the FDD4A, and is arranged so that other devices can receive optical signals sent from one device. The address of the device is automatically determined by incrementing the adder circuit using the received optical signal, and disposing the resulting address so that it can emit light, and decoding the received light signal and using it as the address signal of the corresponding device. It has the effect of being configurable.

Furthermore, since there is no need for strap work when setting the address as in the past, there is no need for on-site adjustments when installing the device, and versatility is maintained no matter where the device is set, making it easy to use it for other purposes. There is an effect that it becomes.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an address setting circuit according to the present invention. FIG. 2 is a block diagram showing an example of a system in which a plurality of FDDs are connected to an FDO. FIG. 3 is a block diagram showing an example of signal line connections between FDO and FDD shown in FIG. 2. FIG. 4 is a block diagram showing the signal transmission/reception relationship between a light emitting diode and a phototransistor provided in the FDD. FX56 is a block diagram showing an example of signal line connection between FDc and FDD according to the prior art. 1 to 4.11...FDD 5.51...FDO1o...Address setting circuit If
, 12... Light receiving circuit 13... Adding circuit 14
...EX-OR gate 15, 531-536...inverter 16, 17
... Light emitting circuit 1-8 ... Decoder 19, 191
...internal circuit 111, 121, 161, 171, 211, 221,
311, 321° 411, 421... Phototransistor 163, 173, 263, 273, 363, 373
,463,473...Light emitting diode 112,122.162.164.172,174...
・Resistor 120...Terminal board for strap 541-544...NAND gate 551-556...AND gate 557...OR gate

Claims (1)

[Claims] a light receiving circuit for receiving an optical signal giving address information transmitted from another device; an adding circuit for incrementing the address information obtained from the light receiving circuit by 1 to obtain second address information; A light emitting circuit for transmitting second address information obtained by the addition result of the adding circuit as an optical signal, and a decoder for decoding the address information obtained by the light receiving circuit to obtain the address of the device itself. What is claimed is: 1. An address setting circuit comprising: an address setting circuit configured to be capable of providing a continuous series of addresses by cascade connection.