JPS62178038A - Digital transmission system - Google Patents

Abstract

PURPOSE:To reduce the cost of a interface circuit of a terminal equipment by providing a means applying clock synchronization in a transmission speed at each interface circuit and a means discriminating whether or not a frame synchronization is taken to the synchronized signal. CONSTITUTION:An optical signal incident in a photoelectric conversion circuit 16 via a half mirror circuit 39 is converted into an electric signal, the data of a low speed frame is separated by a low speed data reception circuit 30 and the result is sent to a terminal equipment from a terminal 42. Further, the circuit 30 generates a frame pulse and gives the pulse to an optical switch drive circuit 45 and a low speed frame generation circuit 48. The circuit 45 drives an optical switch 46 according to the pulse. Thus, the switch 46 goes off the incident light signal for the low speed frame section received by the said terminal interface circuit. On the other hand, the circuit 48 combines the low speed frame, converts 11 it into the optical signal, which is fed to a half mirror circuit 51. The circuit 51 adds the optical signal from an electrooptic transducing circuit 11 to the optical signal from the switch 46 and sends the result to a terminal 52. Thus, the circuit handling the low speed data is constituted by the low speed circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is used for transmitting digital information. In particular, a local area network (Local Area Network) accommodates multiple terminal devices on one transmission path.

Conventional LAN devices (hereinafter referred to as rLANJ) and other digital transmission systems (hereinafter referred to as rLANJ), etc., set the transmission speed of bit strings on the transmission path constant, and time-division transmission and reception of information between the terminal device and the transmission path by channel assignment. Multiplex transmission method, CS
M A -CD (Carrier SenseMu
ltiple Access with Co11is
This is done using a packet transmission method such as ion detection). In the time division multiplex transmission system, by changing the number of channels used on the transmission path, it is possible to change the information transmission speed for transmission and reception between the terminal device and the transmission path. Furthermore, in the packet transmission method, by changing the packet length and packet generation frequency, it is possible to change the information transmission speed for transmission and reception between the terminal device and the transmission path.

[Problem that the invention seeks to solve]

However, in conventional LAN devices, the clock speed of the bit string on the transmission path is constant, and both terminal devices that require high-speed information transmission and terminal devices that are sufficient for low-speed information transmission operate at a high clock speed. Requires interface circuit. Therefore, even a terminal device that requires only low-speed information transmission has the drawback of having to use an expensive interface circuit that operates at high speed. For example, 32
A high-speed terminal device that transmits video at megabits per second, and 64
A LAN device that accommodates a mixture of low-speed terminal devices that transmit data at kilobits per second has the disadvantage that the low-speed terminal devices require an interface circuit that operates at a speed 500 times faster than the required information transmission speed.

The present invention solves the above problems and connects a high-speed terminal device and a low-speed terminal device to one transmission path to transmit information without using an interface circuit that operates at high speed in the low-speed terminal device. The purpose is to provide a digital transmission method.

[Means for solving problems]

The digital transmission method of the present invention includes one wired transmission path,
In a digital transmission system that connects a data processing device to this transmission path and includes a plurality of interface circuits that discretely transmit and receive digital signals, the interface circuit connects the signals on the transmission path to the interface circuit. The present invention is characterized in that it includes means for synchronizing clocks at a transmission rate set in advance for each time, and means for determining whether frame synchronization can be achieved for signals synchronized by this means.

[For production]

In the digital transmission system of the present invention, multiple types of frames having different transmission speeds are discretely transmitted through one transmission path. An interface circuit is provided to connect a data processing device such as a control device or a terminal device to this transmission path.

This interface circuit is configured to perform clock synchronization and frame synchronization with frames of a preset transmission rate.

In other words, when the signal arriving from the transmission path is identified and reproduced using a clock signal of the frequency set in the interface circuit, and the frame pattern included in the frame can be accurately reproduced, this frame is recognized as Detects arrival at the transmission rate set to . At this time, information can be received by branching the information bit string included in this frame, and furthermore, information can be transmitted by inserting the information bit string into this frame at the transmission rate set for the interface circuit.

〔Example〕

FIG. 1 is a block diagram of a digital transmission device according to an embodiment of the present invention. This digital transmission device shows an example in which one control device and three terminal devices are connected to one loop-shaped transmission path.

A control device interface circuit 2 and terminal interface circuits 4a, 4b, and 4c are connected to one transmission line 1 made of optical fiber. The control device interface 2 is connected to the control device 3. Terminal interface circuits 4a, 4b, and 4c are connected to terminal devices 5a, 5b, and 5c, respectively.

A plurality of types of frames having different bit rates are transmitted on the transmission path 1. These frames are created by the control device interface circuit 2.

Here, for ease of explanation, it is assumed that two types of frames, high-speed and low-speed, are transmitted on the transmission path 1.

FIG. 2 is a schematic diagram of the frame structure on the transmission line 1. In this figure, the frame configuration is shown in a pseudo manner as an eye pattern.

On the transmission path 1, high-speed frames FAI, FA□, . . . and low-speed frames F0, F8□, . That is, the control device 3 specifies the transmission time of the signals from the terminal devices i5a, 5b, and 5c, and
Control so that signal collisions do not occur.

FIG. 3 shows the bit structure within the frame.

The frame is composed of an information bit string D3 and two bit strings D+ and Dz provided in front of it. The bit string is a focus string of the guard time section provided at the front of the frame, and is configured into a bit pattern that makes it easiest for the receiving side to obtain timing information. The guard time interval is a guard time area for preventing bit errors in the boundary area of each frame caused by a change in bit rate between adjacent frames. The bit string D2 is a frame pattern for identifying the beginning position of the frame and the information bit string D3. On the receiving side, frame synchronization can be achieved by periodically detecting this frame pattern.

Each terminal device 5a, 5b, 5c transmits a frame (high speed frame F AI, FA!, . . . - or low speed frame F□, Fl) having a bit rate corresponding to its required information transmission rate.
12, -...), and transmits and receives information to and from the control device 3 or other terminal devices using this frame. Further, by setting an address display bit for identifying a terminal device number in the information bit string, the same type of frame can be shared by a large number of terminals.

The control device 3 has a time division exchange function and can communicate between terminal devices by exchanging information bit strings between frames. Each terminal device 5a, 5b, 5c transmits a signal at the time assigned by the control device 3, so when communicating between the terminal devices, it is necessary to exchange frames with each other.

FIG. 4 is a block diagram of the transmitting circuit of the control device interface circuit 2. As shown in FIG.

The clock output terminal 35, the high-speed data input terminal 3G, and the low-speed data input terminal 37 are connected to the control device 3.

Clock output terminal 35 is connected to clock generation circuit 6. The high-speed data input terminal 36 is connected to the high-speed frame creation circuit 7
connected to. The low-speed data input terminal 37 is connected to the low-speed frame creation circuit 8.

The high-speed frame creation circuit 7 is a code conversion circuit 9 for high-speed data.
connected to. The low-speed frame creation circuit 8 is connected to a code conversion circuit 10 for low-speed data. The code conversion circuit 9 for high-speed data and the code conversion circuit 10 for low-speed data are connected to an electro-optical conversion circuit 11. The electro-optical conversion circuit 11 is connected to an optical signal transmission terminal 12.

Optical signal transmission terminal 12 is connected to transmission line 1 .

The clock generation circuit 6 supplies a high-speed data clock signal of frequency fA to the high-speed frame creation circuit 7 and the high-speed data code conversion circuit 9, and supplies a clock signal of frequency r to the low-speed frame creation circuit 8 and the low-speed data code conversion circuit 10. Provides a clock signal for low-speed data.

High speed data input terminal 36 and low speed data input terminal 37
, high-speed data and low-speed data from the control device 3 arrive alternately as a burst data string. These data strings are assembled into the frame configuration shown in FIG. 3 by a high-speed frame creation circuit 7 and a low-speed frame creation circuit 8, respectively.

The assembled frame is a periodically repeated burst-like NRZ signal, which is converted into a transmission line code by a code conversion circuit 9 for high-speed data and a code conversion circuit 10 for low-speed data, and these are added to generate an electro-optical signal. It is supplied to the conversion circuit 11. The electro-optical conversion circuit 11 converts this electrical signal into an optical signal and sends it to the transmission line 1 from the optical signal transmission terminal 12. As a result, high-speed frames and low-speed frames are periodically and alternately sent to the transmission path 1.

FIG. 5 is a block diagram of the receiving circuit of the control device interface circuit 2. As shown in FIG.

The optical signal receiving terminal 15 is connected to a photoelectric conversion circuit 16. The photoelectric conversion circuit 16 is connected to an amplifier circuit 17. The output of the amplifier circuit 17 is supplied to a high-speed data receiving circuit 29 and a low-speed data receiving circuit 30.

The high-speed data receiving circuit 29 includes a tank circuit 19, a phase synchronization oscillation circuit 21, an identification reproduction circuit 23, and a frame synchronization circuit 25. Amplification circuit I7 is connected to tank circuit 19 and identification regeneration circuit 23. Tank circuit 19 is connected to phase synchronized oscillation circuit 21 . The phase synchronization oscillation circuit 21 is connected to the identification reproduction circuit 23, the frame synchronization circuit 25, and the clock output terminal 33. Identification playback v! 23 is connected to a frame synchronization circuit 25.

The frame synchronization circuit 25 is connected to the high-speed reception data output terminal 31.

The low-speed data receiving circuit 30 includes a tank circuit 20, a phase synchronization oscillation circuit 22, an identification reproduction circuit 24, and a frame synchronization circuit 26. The amplifier circuit 17 is connected to the tank circuit 2o and the identification regeneration circuit 24. Tank circuit 20 is connected to phase synchronized oscillation circuit 22 . The phase synchronization oscillation circuit 22 is connected to an identification reproducing circuit 24, a frame synchronization circuit 26, and a clock output terminal 34. The identification reproduction circuit 24 is connected to a frame synchronization circuit 26.

The frame synchronization circuit 26 is connected to the low-speed received data output terminal 32.

High-speed data receiving circuit 29 and low-speed data receiving circuit 30
The only difference is the operating speed, but the circuit configuration and operation are the same. Therefore, the operation of the high-speed data receiving circuit 29 will be described below.

The high-speed frame and low-speed frame signals on the transmission path (3) are converted into electrical signals by the opto-electrical conversion circuit 16 and supplied to the amplifier circuit 17. The amplifier circuit 17 amplifies this electrical signal and supplies it to the tank circuit 19 and the identification/reproduction circuit 23 .

The tank circuit 19 and the phase synchronized oscillation circuit 21 constitute a timing circuit, and output a stable lock signal of the frequency fA. This clock signal is supplied to the identification and reproduction circuit 23 and the frame synchronization circuit 25, and is sent to the control device 3 via the clock output terminal 33. Details of stabilizing the clock signal will be described later.

The identification and reproduction circuit 23 identifies and reproduces the high-speed frame signal using the clock signal output from the phase synchronized oscillation circuit 21, converts the high-speed frame from a transmission path code to an NRZ signal,
This is supplied to the frame synchronization circuit 25. Here, when switching between the high-speed frame and the low-speed frame, there is a possibility that the clock signal output from the phase synchronized oscillation circuit 21 and the input signal of the identification and reproducing circuit 23 do not match in phase. In such a case, there is a possibility that erroneous identification and reproduction will be performed.

In order to prevent such errors, a guard time section consisting of a bit string is provided at the beginning of the frame.

The identification and reproduction circuit 23 also identifies and reproduces signals in low-speed frame sections, but because it is not synchronized with the clock signal, it outputs irregular and meaningless data strings. In order to remove such data strings, the frame synchronization circuit 25
Frame synchronization is achieved using the clock signal output from the phase synchronized oscillation circuit 21 and the pit turn indicated by the bit string D2. As a result, the data string in the low-speed frame section can be removed, and high-speed received data can be extracted from the high-speed frame. The retrieved high-speed reception data is
The data is sent to the control device 3 via the high-speed reception data output terminal 31.

Next, stabilization of the clock signal by the tank circuit 19 and the phase synchronized oscillation circuit 21 will be explained.

FIG. 6 shows operating waveforms of the tank circuit 19 and the phase synchronized oscillation circuit 21.

The tank circuit 19 has its resonance frequency set to match the clock frequency of the high-speed frame, and extracts the clock component in the high-speed frame. However, since there is no clock component in the low-speed frame section, the amplitude of the output signal of the tank circuit 19 decreases and disappears, as shown by the broken line ■ in FIG. That is, the amplitude is small in the leading section of the fast frame FAI% FA2 and in the sections of the slow frames FIII and FBZ.

In order to stabilize the clock signal output at this time, a phase synchronized oscillation circuit 21 is provided. When the output of the tank circuit 19 disappears during the low-speed frame period, the phase synchronized oscillation circuit 21 runs free. As a result, the output of the phase synchronized oscillation circuit 21 has a constant amplitude, as shown by the solid line ■ in FIG. If the free-running frequency of the phase-locked oscillator circuit 21 is set to a value sufficiently close to the clock frequency fA of the high-speed frame,
The frame synchronization circuit 25 operates normally even during free running.

However, when the phase synchronized oscillation circuit 21
Self-propelled in the F'sz section, high-speed frame FA
Since the phase is synchronized with the output of the tank circuit 19 in the leading section of z, the frequency of the phase synchronized oscillation circuit 21 fluctuates as shown in the lower part of FIG. To remove this effect, a guard time is provided at the beginning of the frame.

In the above description, the operation of the high-speed data receiving circuit 29 was explained as an example, but the operation of the low-speed data receiving circuit 30 is also similar.

As explained above, the control device interface circuit 2 includes the high-speed data receiving circuit 29 and the low-speed data receiving circuit 30, but the terminal interface circuit 4 only needs to include one of them.

In the following, a terminal interface circuit that transmits and receives low-speed data will be explained as an example.

FIG. 7 is a block diagram of the terminal interface circuit.

The optical signal transmitted through the transmission line 1 is 1. The light enters the semi-transparent mirror circuit 39 via the optical signal receiving terminal 38. The semi-transparent mirror circuit 39 branches the optical signal into two and sends one of them to the opto-electric conversion circuit 1.
6 and the other to the optical switch 46.

The photoelectric conversion circuit 16 is connected to an amplifier circuit 17.

The amplifier circuit 17 is connected to the tank circuit 20 and the identification regeneration circuit 24.
connected to.

Tank circuit 20 is connected to phase synchronized oscillation circuit 22 .

The phase synchronization oscillation circuit 22 is connected to the identification reproduction circuit 24 , the frame synchronization circuit 26 , the code conversion circuit 49 , the low-speed frame creation circuit 48 and the low-speed clock output terminal 41 .

The identification reproduction circuit 24 is connected to a frame synchronization circuit 26. The frame synchronization circuit 26 includes an optical switch drive circuit 45,
It is connected to the low-speed frame creation circuit 48 and the low-speed received data output terminal 42. Tank circuit 20, phase synchronization oscillation circuit 22, identification regeneration circuit 24, and frame synchronization circuit 26
constitutes the low-speed data receiving circuit 30. The operation of the low-speed data receiving circuit 30 is the same as that of the control device interface circuit, and a description of the operation will be omitted.

Optical switch drive circuit 45 is connected to optical switch 46 . The low-speed frame creation circuit 48 is connected to the low-speed transmission data input terminal 47 and the code conversion circuit 49.

The code conversion circuit 49 is connected to the electro-optical conversion circuit 11.

The optical signal output from the optical switch 46 and the electrical-optical conversion circuit 1
The optical signal outputted by 1 is combined with the semi-transparent mirror circuit 51 and transmitted to the transmission line 1 via the optical signal transmission terminal 52.

The optical signal that enters the opto-electric conversion circuit 16 via the optical signal receiving terminal 38 and the semi-transparent mirror circuit 39 is converted into an electrical signal, and the low-speed data receiving circuit 30 separates the low-speed frame data. The separated low-speed reception data is sent to the terminal device 5 via the low-speed reception data output terminal 42 together with the clock signal of the low-speed clock output terminal 41.

The frame synchronization circuit 26 of the low-speed data receiving circuit 30 creates a frame pulse, which is sent to the optical switch drive circuit 45.
and low-speed frame creation circuit 48.

The optical switch driving circuit 45 drives the optical switch according to the frame pulse from the frame synchronization circuit 26, and extinguishes the optical signal input from the semi-transparent mirror circuit 39 when the frame pulse is positive. As a result, the optical signal input from the optical switch 46 to the semi-transparent mirror circuit 51 is extinguished only during the low-speed frame period received by this interface circuit.

Burst-like low-speed transmission data is supplied to the low-speed transmission data input terminal 47 from the terminal device. The low-speed frame creation circuit 4 uses the clock signal output from the phase synchronization oscillation circuit 22 and the frame pulse output from the frame synchronization circuit 26 to assemble a low-speed frame composed of NRZ signals. This low-speed frame signal is converted into a transmission path code by the code conversion circuit 49, and the electro-optical conversion circuit 11
The signal is converted into an optical signal and supplied to the semi-transparent mirror circuit 51.

The semi-transparent mirror circuit 51 adds the optical signal from the electro-optical conversion circuit 11 to the optical signal that has passed through the optical switch 46 and sends it to the optical signal transmission terminal 52. The signal addition by the semi-transparent mirror circuit 51 is performed at the extinction position of the optical signal that has passed through the optical switch 46.
This is done so that the optical signal output from the electro-optical conversion circuit 11 is inserted.

FIG. 8 shows an operation time chart of the terminal interface circuit. (a) shows an optical signal incident on the optical signal receiving terminal 38. This optical signal is a low-speed frame FBR+,...
FalIt and fast frames F AI −, F A
Contains t. (b) shows the signal output from the identification and reproducing circuit 24. This signal is the slow frame FIRI %
The FalIt signal is included as a normal NRZ signal, and an NRZ signal composed of an irregular data sequence is included between high-speed frames FAI and FA2. High speed frame FAI%F
Data strings between AzOs can be removed by the frame synchronization circuit 26. (C) shows a frame pulse output from the frame synchronization circuit 26. (d+ indicates the optical signal output from the optical switch. This optical signal is converted from the optical signal in (a) to (C)
The frame pulse causes the slow frame FIIRI,F
RRZ is removed and fast frame F AI% F A
Contains only z. (81 indicates an optical signal output from the semi-transparent mirror circuit 51. This optical signal includes an optical signal of +dl and optical signals of low-speed frames Fns+ and Fasz for transmission.

As explained above, the digital transmission of the present invention.

In this method, the terminal interface circuit, which sends and receives low-speed frames to and from the transmission path, can be configured only with low-speed circuits. Here, the terminal interface circuit that transmits and receives high-speed frames can be configured in the same manner as the low-speed one by using a high-speed circuit.

In the above embodiments, an example is shown in which an optical fiber is used as a transmission line, but the present invention can be similarly implemented using a coaxial cable, a pair cable, or a transmission line other than these.

Further, in the above embodiments, frames composed of bit strings having the same transmission rate are periodically transmitted, but the present invention can also be implemented with a configuration in which such frames are transmitted randomly. In this case, it may take a longer time than in the case of periodic transmission until the output of the tank circuit of the receiving circuit stabilizes. Therefore, it is necessary to lengthen the guard time interval. Further, in this case, since the clock phase for identifying and reproducing the received signal differs from frame to frame, a phase synchronized oscillation circuit is not used.

Simply, the frame synchronization circuit identifies the frame pattern position for each frame and separates the received data. The configuration and operation of other parts of the interface circuit are the same except that frames are transmitted and received randomly and discretely.

〔Effect of the invention〕

As explained above, the digital transmission method of the present invention is
A terminal device that sends and receives high-speed data and a terminal device that sends and receives low-speed data can be accommodated in one transmission path, and the interface circuit of the terminal device that sends and receives low-speed data can be configured with a low-speed circuit. . Low-speed circuits are generally cheaper to manufacture than high-speed circuits, and in particular, the ability to utilize CMO3 technology allows for lower power consumption and smaller circuits through greater integration. Therefore, it is possible to reduce the manufacturing cost and running cost of an interface circuit of a terminal device that transmits and receives low-speed data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital transmission device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of the frame configuration. FIG. 3 is a diagram showing the bit structure within a frame. FIG. 4 is a block diagram of the transmitting circuit of the control device interface circuit. FIG. 5 is a block diagram of the receiving circuit of the control device interface circuit. FIG. 6 is a diagram showing operating waveforms of the tank circuit and the phase synchronized oscillation circuit. FIG. 7 is a block diagram of the terminal interface circuit. FIG. 8 is a diagram showing an operation time chart. DESCRIPTION OF SYMBOLS 1... Transmission path, 2... Interface circuit for control device, 3... Control device, 4a, 4b, 4c... Interface circuit for terminal, 5a, 5b, 5c... Terminal device, 6... Clock generation circuit, 7... High speed frame creation circuit, 8... Low speed frame creation circuit, 9... Code conversion circuit for high speed data, 10... Code conversion circuit for low speed data, 11. ...Electro-optical conversion circuit, 12... Optical signal transmission terminal, 15... Optical signal reception terminal, 16... Photoelectric conversion circuit, 17... Amplification circuit, 19.20... Tank circuit, 21.22... Phase synchronized oscillation circuit, 23.
24...Identification reproduction circuit, 25.26...Frame synchronization circuit, 29...High-speed data reception circuit, 30...
Low-speed data reception circuit, 31... High-speed reception data output terminal, 32... Low-speed reception data output terminal, 33.34
．． 35... Clock output terminal, 36... High speed data input terminal, 37... Low speed data input terminal, 38...
Optical signal reception terminal, 39... Half-transparent mirror circuit, 41... Low-speed clock output terminal, 42... Low-speed reception data output terminal, 45... Optical switch drive circuit, 46... Optical switch, 47... ...Low speed transmission data input terminal, 48...
Low-speed frame creation circuit, 49... code conversion circuit, 51
. . . Semi-transparent mirror circuit, 52 . . . Optical signal transmission terminal. yA 1st Honkotsui University Asahi Reiatsu 2 Figure Immu Wakugai. M3112 Frame focus 4, Salt 2 words Relaxation J ¥ 14 Diagram Receiving circuit 5 Diagram operation; L type γ 6 Diagram Akane interface population Nishi rough 7 Diagram operation time + Yard rough 8I2I

Claims (1)

[Claims] (1) In a digital transmission system that includes one wired transmission path and a plurality of interface circuits that connect a data processing device to this transmission path and discretely transmit and receive digital signals, the above interface circuit is , means for clock synchronizing the signals on the transmission line at a transmission rate set in advance for each interface circuit, and means for determining whether or not frame synchronization can be achieved for the signals synchronized by this means. Characteristic digital transmission method.