JPS62177961A - Semiconductor device - Google Patents

Abstract

PURPOSE:To readily electrically separate a memory cell of operating state and a memory cell of standby state by using a word line for the base of a coupling transistor of an RAM cell using I<2>L and bit lines for the collector. CONSTITUTION:The potential of a word line W is a low level and the potential of bit lines B, -B are high level at a point (a). Thus, information in a memory cell is held in a standby state. The emitter and the base of a transistor Q24 are not forwardly biased therebetween at a point (b), forcibly interrupted to be written. The emitters of transistors Q25, Q26 at a point (c) become low and high levels, respectively by the writing performed at the point (b). At this time, the potential difference of the bit lines B, -B is detected to read out it. Reverse information to that at points (b), (c) is written or read out at points (d), (e).

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an integrated circuit using I"L, and in particular to a RAM (Random Access
ssMemory).

[Background of the invention]

Conventionally, regarding the built-in T2LRAM in analog and digital coexistence T, and SI, the Journal of the Institute of Electronics and Communication Engineers V
High voltage analog circuit coexistence 256-bit T2T by Kaneko et al. in OL, J66-CNα9.

Discussed in the document entitled RA　M　J.

FIG. 1(a) is a circuit diagram of a memory cell based on a conventional I2T-device.

The memory cell in FIG. 1(a) has two collectors I"L, 2
The base of each I2L and one collector of each of the two collectors are cross-connected to each other using an element, and the remaining one collector is connected to the bit line i (, hill). Injector word line W
The emitter of +l I2 is set as word line W-.

Qll, 1Q12 are pnpl-transistors, respectively.
Q 1 a + Q 14 is a two-collector npn transistor that operates in the opposite direction.

FIG. 1(1)) is an equivalent circuit for explaining the operation of FIG. 1(a). 2-corefta reverse npn in Figure 1(a)
In FIG. 1(b), the l-transistor Q1BI Ql,4 is equivalently an inverse n p n I-transistor Qx7rQrs whose base and collector are cross-connected to the phase 77), and the external connection for reading and writing. An inverse npnl-transistor QI11. acting as a coupling element. Ql, 7 and Qlll are shown separately in Qts, Ql
ll and Q hlo correspond to Q14.

A constant current source I lnj is connected to the word line W+, and pn
The p transistors Q I R and Q I B are each inverted n
It acts as a load for pn transistors Q s 7 and Q I B. Also, JI91 to reverse NPNL-transistor
QIIO's 1-noctor is each pitch 1-line l<, i'
<-, and B and bar are connected to the power supply VRH through a load resistor Rn.

The 11 extraction operation and its conditions will be described below using the equivalent circuit diagram shown in FIG. 1(I).

Now, if the reverse npn transistor Q171 Qse is conductive, Qlδ and QIIO are non-conductive.

A collector current corresponding to the base current supplied through the pnp transistor Qzo flows through Qle.

In this case, the collector current flows through the power supply V through the load resistor RB.
The potential VR of the bit line B is lower than VRB by the voltage drop across the load resistor RR.

On the other hand, the potential of the bit line π- is the same as VBB since Q 1 to is non-conductive. By detecting the potential difference between the pin 1-line B and 1, it is possible to read the information inside the memory.

The read operation of only 1 pin 1- was described above, but
In an actual RAM, there are a plurality of memory cells that share the bit lines R and 81.

Therefore, in the conventional memory cell shown in FIG. 1, the selected and unselected memory cells cannot be electrically isolated, so the unselected memory cells also absorb collector current from the bit line.

Therefore, as a method for selecting and non-selecting memory cells,
Injector current of selected cell], increase InJ,
Measures are taken to differentiate the current drawn by non-selected cells. In this case, the worst condition in which the potential difference between the bit lines is the smallest is when all unselected memory cells hold information opposite to that of the selected memory cells. The injector current of the selected memory cell is
, when the injector current of an unselected memory cell is Ius, the sink current In of the selected cell and the total sink current Iust of the unselected cell are IR=-αPβ.
(1) becomes.

Here, α is Pnp transistor Q 13°Ql[
The common base current increase [1] rate of 1, β, is the inverse npn transistor Q19. Q] It is the current increase in ko + iJ rate.

Further, N is the number of memory cells connected to the bit lines B and H. The condition under which the information of the selected memory cell can be read is Is > IUST (3
), so the relationship between the injector current, Ius, and Is is: Is > Ius (N 1)
(1, 4).

For example, if an i K-bit RAM is constructed with 8 bits per word, the number of memory cells that share a bit line will be 128, and TS must be 1- or more than 127 times Ius. As a result, if the size and configuration of the RAM differ, the number of memory cells that share a bit line will differ, so peripheral circuits must be designed each time. Also, for stable operation, Is/Nus is 102
It is desirable to do the following. Therefore, the conventional I2LRAM circuit is not suitable for a RAM of IK bits or more.

[Purpose of the invention]

The purpose of the present invention is to create a T"LRAM with excellent designability and expandability.
Our goal is to provide the following.

[Summary of the invention]

In the present invention, by replacing the conventional I"T and RAM coupling transistors with npn transistors, and using the base of the npn transistor as a word line and the collector as a bit line, an I"L RAM with excellent designability and expandability is realized. did.

[Embodiments of the invention]

A first embodiment of the present invention will be described below with reference to FIG. FIG. 2 is an equivalent circuit diagram of one bit of an IIL memory cell according to the present invention.

In FIG. 2, mutually cross-connected npn transistors Q2! +1 Q114 and the ρnp transistors Qxx and Qzx, which act as a load, are ■2L in the first embodiment.
It is constructed by interconnecting two gates.

I'' in Qzx, Qxa and Q22 and QzB respectively
Compatible with LI gate. Also, Qsr+,
It is an n transistor. Also Q211 and 02. t is I2
L is a reverse operating transistor in the gate.

Therefore, QzI5t Q2B operates in the opposite direction to Q211 and Qxt.

The injector line INJ also serves as a power source for the memory cells.

During operation, a current source is connected to the injector line INJ.

Next, the operation of the memory cell according to the present invention will be explained.

FIG. 3 is a timing chart showing the potential changes of the word line W and bit lines B, B of the memory cell of FIG. 2, and clarifying the operation of the memory cell according to the present invention. At point a in FIG. 3, the potential Vw of the word line W is at a low level of approximately Ov, the potentials VB and VB of the bit lines B and B- are both at a high level, and the switch transistor QxI
S, QzB are in the off state.

Therefore, the information inside the memory cell is maintained and is in a standby state. At point b, the potential Vw of the word line W is set to a high level, and the potential VB of the bit line B is set to a low level. As a result, the base of the switch transistor Q211
The collector is forward biased, and the switch transistor Q
z6 operates in the opposite direction. Therefore, the emitter potential of Q2.5 is at a low level, which is approximately the same potential as the collector. Therefore, Q
The base and emitter of za are no longer forward biased,
It is forced into a non-conductive state and writing is performed.

At point C, the potential Vw of the word line W is set to a high level. At this time, inside the memory cell, due to the writing performed at point b, the npn transistor Q24 is non-conductive and 02g is conductive, the emitter of the switch transistor Q25 is at a low level, and the emitter of Qze is at a high level. There is. Therefore, the base-emitter of the switch transistor 02B is forward biased, operates in the forward direction, and lowers the potential VB of the bit line B to a low level.

Reading becomes possible by detecting the potential difference (Vn-VB) between bit lines B and H at this time.

At point d, the state of the word line W is the same as at point b, and is in a high-level selected state, but the bit line is -h, contrary to point b.
- is at a low level. This causes Qze to operate in the opposite direction and Qzs to become non-conductive.

If the write performed at point b is “1”, then at point d it is “1”.
This means that 0'' is being written.

Also, at point 0, like at point C, reading is performed with the word line set to high level, but the information being read is
This is the opposite of point C, with Ding being at a low level and B being at a high level.

If the information read at point 0 is N i I+,
Information being read at point 0 corresponds to 10''.

In this example, Q 21 y Q 24 and Qzz, Q
Since each transistor 211 is formed with a gate of T''l, two transistors can be constructed with a small area almost equal to one element.

Therefore, the cell area has the effect of being small. Furthermore, since the base of the coupling transistor is the word line W, the cell and the bit line can be reliably separated when not selected.

FIG. 4(a) is an example of a planar pattern when the memory cell according to the present invention is constructed from an integrated circuit. Fourth
FIG. 4(b) is a cross-sectional structural diagram taken along the line X-X1 in FIG. 4(a). FIG. 4(a) shows a memory cell of 1 pin 1-min, and the transistor pair Q 21 + Q in FIG.
24 and Q 22 HQ z s +; J: I z
In the L region, Q231028 is formed in the npn region. Further, the I2T region and the individual npn transistors in the npn region are mutually interconnected by one L electrically separated by an element isolation region 41°419. In the memory cell of this embodiment, a coupled 1-transistor can be formed in the same element isolation region between memory cells sharing a bit line, and the bit line n,'-i3 is connected to the n p n region r]→buried. Layer 4-46 r 4 J 5 L: Wiring is possible by providing extraction electrodes 46, 41.4,
The number of wiring lines in the element region -1- is not eight.

FIG. 5 is a circuit diagram showing the second embodiment.

FIG. 5 shows a memory cell for one pin+-, in which the pn p l- transistor Q 21 r Q 22 serving as the load of the memory cell in FIG. 2 is replaced with load resistors R51 and R82. Also, the same as in Fig. 2 (S<, 1 transistor QBI, Q52 reverse direction, QR8, Qllll
is an npn transistor operating in the forward direction.

FIG. 6 is a circuit diagram showing the second embodiment.

FIG. 6 shows one bit of the memory cell, and the load of the memory cell in FIG. 2 is p n p l-transistor Q.
211 Q22 to diode D61. I)ez
It has been replaced with . Also, as in Fig. 2, 1- transistor Q61+ Q82 is in the opposite direction, Qoa+ Q84
is an npn transistor operating in the forward direction.

Next, in the first embodiment according to the present invention, Q in FIG.
21. Qzz is a normal pnpn transistor, Q28
1 Q241 Q2111 It is clear from the above description that even if all Q2B are formed of forward-direction npn l-transistors, there will be no problem in circuit operation, and the memory function will be the same as in the first embodiment. In this case, since Qz8+ 024I Ql[1 and Qze all have high gains, there is plenty of room even if the gains decrease due to manufacturing variations or the like. This has the effect of widening the manufacturing margin.

However, the cell area is slightly larger than that of the first embodiment.

〔Effect of the invention〕

According to the present invention, by making the base of the coupling transistor of the RAM cell using the conventional III the word line and the collector the bit line, the memory cell in the operating state and
It is easy to electrically isolate memory cells in standby state.
It is possible to standardize peripheral circuits and increase the degree of freedom in RAM configuration. Therefore, it is effective in terms of designability and extensibility.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional Izl RAM cell and its equivalent circuit diagram, and FIG. 2 is a first diagram of a memory cell according to the present invention.
FIG. 3 is a diagram showing the control pulse chart 1 of the memory cell according to the present invention, FIG. 4 is a diagram showing the planar pattern and cross-sectional structure of the memory cell of the first embodiment, and FIG. 6 and 6 illustrate the second embodiment according to the present invention. FIG. 3 is a circuit diagram of a third embodiment. Qllll Q121 Q131 QxepaP n P
Transistor, Qxs, Qlat Q17I Qla
t Ql[11QIIO-n p n transistor, Q
10IQ112...Diode, IN, 1...Injector line, W...Word line, Q21゜Q22・
... Pnpn transistor, -B... Pi1- line, Q
211. Q2tt Q2111 Qze-n p n
Transistor, Vw...word line potential, Vn, Vw
...Bit line potential, 41.419,444,436,4
30... Element isolation region, 43, 411, 417, 42
1.4-49°442.439,438,433...
p-type diffusion region, 44.47,48,416,414,4
45゜443.437,434,431-...n ten diffusion regions, 42.45.46.49,420,412,4
18゜415.414...Contact hole, INJ...
・In-die phthalate line, Fl, B...bit line, W・
...Word line, 448, 441, 432. ... n-type epitaxial layer, 446, 440, 435-n+
Buried layer, 447...p-shaped part plate, 429, 424...
...Insulating film, 423.425, 426, 427, 428
...AQ. 1st layer wiring, 422...A22nd layer wiring, Rat, Rs
2...Resistance, Qsl, Q+bzt QBs, QB
s-n pn transistor, IN, J...Injector line, W...Word line, B, B-...Pimmyl line, D81, D82...Diode, Q
e 1 , Q e 2. Q ea , Q 84
°=npnl-transistor, TNJ...injector line, W...word line, B. ■...Bit line. Item 1 Mouth C mountain tb) Figure 2 ■ Rod 30

Claims (1)

[Scope of Claims] 1. A first polarity-containing device having a base and a collector cross-connected to each other and having their emitters connected together to a first word line.
, a second transistor serving as a load for the first and second transistors, both having their bases connected to the first word line, both having their emitters connected to the second word line, and having their respective collectors connected to the first, second and second transistors. Third and fourth transistors of second polarity were connected to the collector of the second transistor, and their emitters were connected to the collectors of the first and second transistors, respectively, and their bases were connected to the third word line. A semiconductor device comprising fifth and sixth transistors of a first polarity, and first and second bit lines connected to the collectors of the fifth and sixth transistors, respectively. 2. The above first, second, third, and fourth transistors are I^
2L(￥I￥integrated￥I￥njectio
The fifth and sixth transistors are transistors that operate in the opposite direction to the first and second transistors. A semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the third and fourth transistors are replaced with resistors. 4. The semiconductor device according to claim 1, wherein the third and fourth transistors are replaced with diodes. 5. The semiconductor device according to claim 1, wherein the first, second, fifth, and sixth transistors are transistors that operate in the same direction.